TWI336501B - Method for making a direct chip attach device and structure - Google Patents

Method for making a direct chip attach device and structure Download PDF

Info

Publication number
TWI336501B
TWI336501B TW093117232A TW93117232A TWI336501B TW I336501 B TWI336501 B TW I336501B TW 093117232 A TW093117232 A TW 093117232A TW 93117232 A TW93117232 A TW 93117232A TW I336501 B TWI336501 B TW I336501B
Authority
TW
Taiwan
Prior art keywords
conductive
opening
electronic
electronic chip
wafer
Prior art date
Application number
TW093117232A
Other languages
English (en)
Other versions
TW200504896A (en
Inventor
Yeu Wen Lee
Chuan Kiak Ng
Guan Keng Quah
Original Assignee
Semiconductor Components Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Ind filed Critical Semiconductor Components Ind
Publication of TW200504896A publication Critical patent/TW200504896A/zh
Application granted granted Critical
Publication of TWI336501B publication Critical patent/TWI336501B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
    • B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
    • B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73151—Location prior to the connecting process on different surfaces
    • H01L2224/73153—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

九、發明說明： 【發明所屬之技術領域】 本發明大體係關於電子裝置封裝，且更具體言之，係關 於用於在覆晶封裝内形成互連之方法及設備。 【先前技術】 . 覆晶微電子封-裝技術已存在30多年，其涉及將面朝下（所 以被稱為"覆"）的電子組件或晶片直接電連接至基板、電路 板或載體》該電連接是藉由連接至晶片及基板兩者上的結 合襯墊之導電凸塊或球而得以建立。相反，屬於較舊技: 之導線結合採用的.是面·朝上的晶.片，.該等·晶片.具有在每個 結合襯墊與引線框上一相應引線或插腳之間的導線。 覆晶組件主要是半導體裝置。但諸如被動渡波器、债測 器陣列及感測器裝置等之組件亦開始以覆晶形態加以使 用。覆晶也可稱為直接晶片安裝（DCA)，此術語更具說明 性，因為晶片係藉由導電凸塊而直接安裝至基板、電路板 或載體。 儘官覆晶技術已經取得進步而包括了用於對裝置進行凸 塊化（bumping)、安裝及底部填充之很多不同的材料及方 法，然而在解決有關更嚴格的空間要求、減少成本及提高 裝置效能及可靠性之難題方面仍然存在挑戰。 因此，存在對用於形成覆晶類型封農之改良結構及方法 之需要。 【發明内容】 大體而言’本發明係關於—種在模製成的直接晶片安裝 93799.doc 1336501 (DCA)結構令形成開口 > 一 仏將知枓凸塊連接至經封裝裝置 方法。洋g之，將雷 θ € Λ ^ ^ ^ 電子ΒΒ片文裝至引線框結構，並將導 電凸塊女裝至該晶片 .片之表面上的結合襯墊。然後將引線框 基板及電子晶片封裝扃 在杈八内。在封裝步驟期間，模穴内 之插腳、栓或突起與導 V電凸塊接觸以防止封裝材料形成於 導電凸塊上，以便提供開 隹進步步驟中，藉由開口 將知料球安裝至導電凸塊上。 當前，DCA裝置的製造流程如下。將電子晶片安裝至引 線框結構。然後利用習知射出成形技術藉由鈍化材料或模 製化合物將該晶片封裝起來。當模製過程Μ並且該等裝 置自模製設備中移除後，開口形成於該模製成的裝置之外 表δ L露電子晶片上的接觸區域。然後安裝燁料球以 提供經封裝晶片與下—級總成之間的互連。 -種在該模製成的裳置之外表自中形纟開口之途徑是使 用雷射燒灼。雷射燒灼具有若干缺點，包括：加卫時間長、 設備昂貴及提供適當校直之技術繁瑣。化學蝕刻是用以形 成開口之另一種技術。此技術需要非常昂貴及危險之專用 化學品。此外，化學蝕刻技術需花費大量時間，並需要昂 貴的加工設備。 【實施方式】 可藉由參看圖1〜8連同以下詳細的描述來更好地瞭解本 發明。為了易於瞭解’在整個詳細描述及圖式中類似的元 件及區域標有相同的標號。 圖1展示根據圖2〜7所描述之方法製造的直接晶片安裝事 93799.doc 1336501 置或結W之放大的等角視圖。DCA裝置i包括_引線框或 支樓基板2; -電子晶片、裝置或組件3(如圖2所示及具 有於上表面7上形成的開口 6之封裝劑或保護層4。藉由開口'
6或在開口 6内，將焊料或導電球、球體或凸塊9耦接至晶片 3及引線框2。 M 圖2說明DCA裝置！在製造早期階段沿^之參 取之放大的橫截面圖。以實例說明之，晶片3包 MOS而（金氧半導體場效電晶體）、邏輯、_器裝置、被 動裝置或雙極裝置。晶片3包括在上表面14上之結合襯墊或 接點13。結合襯墊13包含（例如）鋁/鋁-矽/鋁-矽-鋼。利用諸 如易熔晶粒安裝、導電環氧樹脂或軟焊料加工等之習知技 :將晶片3安裝至引線框2以形成晶粒安裝層17。舉例而 吕，利用鉛/錫（Pb/Sn)軟焊料加工來安裝晶片3。 如圖2所示，引線框2進一步包括一旗標18，言亥旗標為晶 片3之下表面19提供一上部或頂面接點。舉例而言，當晶片 3包括一功率M0SFET時，接點13形成源極接點，而=18 提供一頂面没極接點。包括旗標18之引線框2較佳包含銅、 銅合金（例如T0MAC4、TAMAC 5、2ZFR〇F(^cda⑼）、 鍍銅之鐵/鎳合金（例如鍍銅合金42)或其類似物。 接著，如圖3所示，將導電凸塊、球或栓22安裝至接點13〇 在—較佳實施例中，亦將導電栓22安裝至旗標18。在一替 代實施例中，將旗標18之高度設計成與栓22及接點Μ之高 度相匹配’且旗標18上不置放栓22。 (例如）超音波、熱塵縮或熱音波（thermosonic)結合技 93799.doc 1336501 術來安裝導電栓22。導電栓22包含（例如）金或銅。在一實施 例中，利用習知之接線結合技術藉由導線結纟球來形成導電 栓22。較佳將導線結合球上方導線的所有騎部分移除，這 樣在結合襯塾13及旗標18上只留有導電栓以，如圖3所示。 或者’利用被回焊以供電及機械地安裝至結合襯塾似 旗標18之焊料球來形成導電栓22。在另—實_+，利用 導電環氧樹脂形成導電栓22。導電栓22的高度較佳自約乃微 米至約I500微米。安裳了導電栓22後，子總成24就形成了。 圖4展示子總成24在下一個加工階段開始時之放大的橫 截面圖。將子總成24置放在模製設備27中以進行封裝。模 製設備27包括上半部分、上部板或第一半部分“及下半部 分、下部板或第二半部分3 1。在一較佳實施例中，下部板 31進一步包括形成於上表面或主表面34中用於接收或容納 晶片3及旗標18之腔體、井或井部分32。 根據本發明，井32包括形成、耦接或安裝於其表面”上 之插腳、栓、突起或凸塊36。舉例而言，插腳36係形成於 井32之製造或加工期間當自下部板3〗移除周圍材料時。意 即，插腳36及下部板31係由單塊材料加工而成。或者，利 用焊接或銅焊（brazing)技術來將插腳36安裝至表面37。在 一較佳實施例中，插腳3 6包含碳鋼。 根據本發明，插腳36係形成或置放於井32内與子總成24 上的導電栓22對準之位置處，使得當上部板29降低而抵住 子總成24時，插腳36可如圖5所示與導電栓22接觸。在模製 或封裳步驟期間，該接觸提供了一遮罩或阻塞結構或裝 93799.doc 1336501 置，其可防止模製化合物或封裝材料覆蓋栓22之上表面， 以便形成開口 6。在替代實施例中，腔體及插腳形成於上部 板29中，且當置放在模製設備27中時子總成24被翻轉朝上。 然後利用習知構件將模製化合物注入井3 2以封裝晶片3 及旗標18，以便形成如圖1所示的保護層4。保護層4包含（例 如）酚醛基環氧樹脂。 在一較佳實施例中，並如圖4所示，插腳36之上表面係扁 平的，同時上邊緣被切成斜面或圓化以便在DCA裝置丨之開 口 6中長：供斜面化或圓化邊緣。此更清楚地展示於圖6中， 圖6係子總成24在經過模製加工步驟後之放大的橫截面 圖。該斜面化或圓化邊緣在將焊料球9置放於開口 6中期間 提供了增強的對準。以實例說明之，當DCA裝置丨包括（例 如）一功率MOSFET晶片時’插腳36之高度大約為〇 〇5至〇 15 毫米（mm)’且直徑為〇.20至〇.5〇111111。該等尺寸係可變的， 且可根據個別裝置及封裝約束來加以調整。 藉由在封裝加工期間形成開口 6，模製設備27比其它諸如 雷射燒灼或化學蚀刻之技術都有優勢，因為消除^使用額 外的加工設備及消耗品（例如化學品、工具等等）之必要。此 外，此減少了循環時間，因而進一步降低了dca裝置丨的製 造成本。 在模製加工後，封裝劑4受到後固化（p〇st_cured),並接著 在開口6内之栓22上形成一障壁層41。障壁層“較佳包含盥 栓22及焊料球9在冶金學上相容之材料。意即，障壁層:; 防止栓22及焊料球9之元素互相擴散。舉例而言，當栓u 93799.doc • 10· 1336501 包含金’且㈣球9包含心料，障㈣41較佳包含使用 無電鎳鍍敷或電解鎳鍍敷而形成之鎳層。 已安裝焊料球9後之放大的橫截面 圖7展示DCA裝置1在 圖焊料球9包含（例如）錯/錫合金並利用習知之上助焊劑 ( — Μ)及回焊技術來加以安裝。纟回焊之後1㈣9_ 般呈半球狀》 圖8展示根據本發明之-第二實施例之模製設備47之放 大的橫截面圖。模製設備47包括一上半部分或板49及一下 半部分或板51。下部板進-步包括形成於上表面54中之腔 井或井。P刀52。在該第二實施例中插聊％係置放於 在井52中形成之開口 57中。該實施例允許視特定裝置及封 裝要求而定來使用具有不同頂端幾何形狀(例如圓化的、扁 平的、正方的等等）之插腳。此外，模製設備Ο允許當較舊 的插腳磨損或損壞時 、气手以具成本效益之方式添加新的插腳。 因此’很明顯的是根據本發明提供了一種用於形成直接 晶片安裝裝置之方法，該裝置在模製成的封裝中具有開口 1:::焊經封裝晶片接觸。此外，已提供了-種模 ^ /、匕括插腳以在模製加工期間有利地形成開口。 :亥方法及結構藉由消除需要昂貴設備及材料之加工步驟而 供了與其它技術相比之改良。 儘s已參考其特定實施例描述並說明了本發明，但吾人 明限制於該等說明性實施例。熟悉此項技:者 2解可在不偏離本發明之精神之情況下進行各種修改與 例如’可將模製設備27倒置，使得在上部板中形成 93799.doc 1336501 腔體及插腳。因此，吾人希望本發明涵蓋屬於附加之申請 專利範圍之範疇内的所有此等變更及修改。 【圖式簡單說明】 圖1說明根據本發明製造的直接晶片安裝裝置之放大的 等角視圖； 圖2說明圖1之實施例在製造早期階段沿參考線1_丨截取 之放大的橫截面圖； 圖3說明圖1之實施例在製造進一步階段之放大的橫截面 圖； 圖4說明用來形成圖丨之實施例的根據本發明之設備的放 大的橫截面圖； 圖5說明圖4之設備之另一放大的橫截面圖； 圖6說明圖1之實施例在製造隨後階段之放大的橫截面 圓； 圖7說明圖1之實施例在製造更進一步階段之放大的橫截 面圖；及 圖8說明根據本發明之設備之第二實施例之放大的橫截 面圖。 【主要元件符號說明】 1 2 3 4 6 直接晶片安裝裝置 引線框結構 電子晶片 封裝材料 開口 93799.doc 1336501 7 上表面 9 焊料球 13 結合襯墊 14 上表面 17 晶粒安裝層 18 旗標 19 下表面 22 導電栓 24 子總成 27 模製設備 29 第一板 31 第二板 32 腔體、井或井部分 34 主表面 36 插腳 37 井32之表面 41 障壁層 47 模製設備 49 第一板 51 第二板 52 腔體、井或井部分 54 上表面 56 插腳 57 開口 93799.doc -13-

Claims (1)

  1. D!30501^ 〇93117232號專利申請案 月4日祭(更)正本 中文申請專利範圍替換本(99年10月） 十、申請專利範圍： 丨丨-.|丨 1. 一種用於形成一直接晶片安裝梦窨 文发哀置之方法，包括如下步 驟： 將-電子晶片安裝至一引線框結構，其中該電子晶片 包括一結合襯墊； 將一導電凸塊安裝至該結合襯墊； 將該電子晶片及引線框6士错X 深亿 構置放入—模製設備中，其 中該模製設備具有一井部分，' 3开口p刀具有一耦接至該 井部分之一第一表面之可移除插腳； 使β亥可移除插腳與該導電凸塊接觸； 藉由-封裝材料來模製該電子晶片，其中該可移除插 腳遮蔽該導電凸塊’以在該導電凸塊上之封裝材料中提 供開口，且其中該導電凸塊被嵌入該開口之内；且 之後形成一疊加於該導電凸塊上之障壁層。 2.如清求項1之方法，其中將該電子晶片及該引線框結構置 放入該模製設備中之該步驟包括：將該電子晶片及該引 線框結構置放入該模製号·播φ : 惧I 口又備中，其令該井部分具有耦接 至該第-表面之複數個可移除插腳。 3·如明求項1之方法，進一步包括將一焊料球搞接至該開口 内的該電子晶片之步驟。 4.如。月求項1之方法，其中將該電子晶片及該引線框結構置 放入該模製設備中之該步驟包括：將該電子晶片及該引 ^構置放入该模製設備中，其中該可移除插腳具有 扁平上表面及圓化的上邊緣。 93799-99J026.doc 5. :於形成—覆晶裝置之方法，包括如下步驟： 不+總成置放入一具有—腔體的模製設備内， 成匕括—t裝至一支樓基板之電子晶片，且其中 ^子晶片具有—耦接至該電子晶片之第^ 你兮― 弟—導電栓； 二弟-導電检.該腔體内之第—阻塞裝置接觸； 封裝材料注入該腔體内以封裝該電子晶片，其中 阻塞裝置遮蔽該第一導電栓以在該覆晶裝置：形 二開° ’其中該開口包含-斜面化邊緣，且其中該第 一導電栓被嵌入該開口之内；及 形成一疊加於該第一導電栓上之障壁層。 6. 7. 8. 9. 如請求項5之方法’進一步包括將一焊料球藉由該開口安 裝至该覆晶裝置之步驟。 如凊求項5之方法，其中該接觸步驟包括：使該第—導電 栓與-具有-扁平上表面及圓化上邊緣之可移除插腳接 觸’以形成該斜面化邊緣。 如喷求項5之方法，其中置放該子總成之該步驟包括：置 八有女裝至一支撐基板之電子晶片之子總成，其 中該支撐基板包括一旗標。 〃 一種用於形成一半導體裝置的方法，其特徵在具有以下 步驟： 將一子總成置放入一具有一腔體的模製設備内，其中 該子總成包括一安置於一支撐基板之電子晶片，且其中 S亥電子晶片具有一與其耦接之第一導電栓，且其中該支 撐基板進一步包括一旗標，該旗標具有一與其耦接之第 93799-99l026.doc 1336501 二導電栓； 使:弟一導電栓與該腔體内之一第一可移除插腳接觸; 使:第二導電拾與該腔體内之—第二可移除插腳接觸； *將：封裝材料注入該腔體内以封裝該電子晶片及該旗 標？、中該第一可移除插腳遮蔽該第一導電栓以形成一 第一開σ，該第-開口具有在該封裝材料中之 邊緣且疊加於兮梦 ^ Α ϋ :加於該第一導電栓上’且其中該第二可移除插 腳遮“第二導電栓以形成一第二開口，該第二開口具 有在-亥封裝材料中之一斜面化邊緣且疊加於該 栓上； 守电 形成疊加於該第-及第二導電栓上之—導電障壁層； 將：第一焊料球藉由該第一開口安裝至該第 =Ί該第-開口之該斜面化邊緣經粗態以增強在兮 弟一開口内之該第一焊料球之對準；且 " 將：：二焊料球藉由該第二開口安裝至該第二導電 笛第二開口之該斜面化邊緣經組態以增強在該 第一開口内之該第二焊料球之對準。 〇 他如請求項9之方法，其中形成疊加於該第—及第二導電拾 之〇亥導電障壁層之該步驟包括 王 障壁層。 肜成—包含鎳之導電 93799-991026.doc
TW093117232A 2003-06-26 2004-06-15 Method for making a direct chip attach device and structure TWI336501B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/603,257 US7144538B2 (en) 2003-06-26 2003-06-26 Method for making a direct chip attach device and structure

Publications (2)

Publication Number Publication Date
TW200504896A TW200504896A (en) 2005-02-01
TWI336501B true TWI336501B (en) 2011-01-21

Family

ID=33539693

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093117232A TWI336501B (en) 2003-06-26 2004-06-15 Method for making a direct chip attach device and structure

Country Status (4)

Country Link
US (1) US7144538B2 (zh)
CN (2) CN100463152C (zh)
HK (2) HK1073725A1 (zh)
TW (1) TWI336501B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7928550B2 (en) * 2007-11-08 2011-04-19 Texas Instruments Incorporated Flexible interposer for stacking semiconductor chips and connecting same to substrate
US10251273B2 (en) * 2008-09-08 2019-04-02 Intel Corporation Mainboard assembly including a package overlying a die directly attached to the mainboard
US8383457B2 (en) 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
USRE48111E1 (en) 2009-08-21 2020-07-21 JCET Semiconductor (Shaoxing) Co. Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8169058B2 (en) 2009-08-21 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
US8304900B2 (en) * 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US9401338B2 (en) * 2012-11-29 2016-07-26 Freescale Semiconductor, Inc. Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
US9397074B1 (en) * 2015-04-29 2016-07-19 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
FR3041625B1 (fr) * 2015-09-29 2021-07-30 Tronics Microsystems Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support
CN108249385A (zh) * 2018-01-15 2018-07-06 烟台艾睿光电科技有限公司 一种mems封装焊接组件
DE102020208862A1 (de) * 2020-07-15 2022-01-20 Zf Friedrichshafen Ag Formwerkzeug zum verkapseln eines pin-fin-artigen leistungsmoduls und verfahren zum herstellen eines leistungsmoduls

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW344109B (en) * 1994-02-10 1998-11-01 Hitachi Ltd Methods of making semiconductor devices
US5766972A (en) * 1994-06-02 1998-06-16 Mitsubishi Denki Kabushiki Kaisha Method of making resin encapsulated semiconductor device with bump electrodes
MY112145A (en) * 1994-07-11 2001-04-30 Ibm Direct attachment of heat sink attached directly to flip chip using flexible epoxy
US5757073A (en) * 1996-12-13 1998-05-26 International Business Machines Corporation Heatsink and package structure for wirebond chip rework and replacement
US6081997A (en) * 1997-08-14 2000-07-04 Lsi Logic Corporation System and method for packaging an integrated circuit using encapsulant injection
JP2001230520A (ja) * 2000-02-14 2001-08-24 Sony Corp 配線基板の製造方法及びそれにより得られた配線基板
US6717245B1 (en) * 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6660565B1 (en) * 2000-08-17 2003-12-09 St Assembly Test Services Pte Ltd. Flip chip molded/exposed die process and package structure
US6436736B1 (en) * 2000-11-13 2002-08-20 Semiconductor Components Industries Llc Method for manufacturing a semiconductor package on a leadframe

Also Published As

Publication number Publication date
CN1577824A (zh) 2005-02-09
HK1073725A1 (en) 2005-10-14
HK1128989A1 (en) 2009-11-13
CN100463152C (zh) 2009-02-18
US7144538B2 (en) 2006-12-05
TW200504896A (en) 2005-02-01
CN101383294A (zh) 2009-03-11
US20040262811A1 (en) 2004-12-30
CN101383294B (zh) 2010-06-16

Similar Documents

Publication Publication Date Title
US11652038B2 (en) Semiconductor package with front side and back side redistribution structures and fabricating method thereof
US20240088059A1 (en) Semiconductor device having emi shielding structure and related methods
US7081678B2 (en) Multi-chip package combining wire-bonding and flip-chip configuration
KR100319609B1 (ko) 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법
TWI360188B (en) A semiconductor package assembly and methods of fo
TWI277192B (en) Lead frame with improved molding reliability and package with the lead frame
US20080157328A1 (en) Semiconductor device and method for manufacturing same
US6835580B1 (en) Direct chip attach structure and method
KR20060044637A (ko) 반도체 장치의 제조 방법, 반도체 장치 및 반도체 칩
JP2015523743A (ja) Ｂｖａインタポーザ
US11488892B2 (en) Methods and structures for increasing the allowable die size in TMV packages
US20090115026A1 (en) Semiconductor device having through-silicon vias for high current,high frequency, and heat dissipation
TW200531188A (en) Land grid array packaged device and method of forming same
TWI336501B (en) Method for making a direct chip attach device and structure
TWI397164B (zh) 矽穿孔連通延伸之晶片封裝構造
US20080303134A1 (en) Semiconductor package and method for fabricating the same
JP2010263108A (ja) 半導体装置及びその製造方法
JP2007123719A (ja) 半導体チップとその製造方法ならびに半導体装置
US6160311A (en) Enhanced heat dissipating chip scale package method and devices
WO2017160235A1 (en) Electrical connection structure, semiconductor package and method of forming the same
US7229849B2 (en) Method for packaging a semiconductor device
JP2001007238A (ja) ウエハーレベルの集積回路装置のパッケージ方法
KR100753795B1 (ko) 반도체 패키지 및 그 제조 방법
KR20020044274A (ko) 칩 스케일 패키지 및 그 제조방법
KR20070000722A (ko) 플립 칩 패키지

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees