CN101080816A - 覆晶接点的功率组件封装 - Google Patents

覆晶接点的功率组件封装 Download PDF

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CN101080816A
CN101080816A CNA2005800430795A CN200580043079A CN101080816A CN 101080816 A CN101080816 A CN 101080816A CN A2005800430795 A CNA2005800430795 A CN A2005800430795A CN 200580043079 A CN200580043079 A CN 200580043079A CN 101080816 A CN101080816 A CN 101080816A
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bumpless
lead frame
power
directly
lead
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CN100499104C (zh
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孙明
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Alpha and Omega Semiconductor Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

一种功率组件封装(100)包含有一以供直接无凸块依附于功率晶体管(105)的顶面(120)与底面(110)引线架。功率晶体管(105)依附于底面引线架(110)上，如同一具有源极接触点(112)与栅极接触点(114)的覆晶直接无凸块依附于底面引线架(110)上。功率晶体管(105)具有一依附于顶面引线架(120)之底面漏极接触点(106)。顶面引线架(120)更包含有一作为底面漏极电极的延伸部，其是与该底面引线架(110)同侧。

Description

覆晶接点的功率组件封装
                        发明背景
1、技术领域
本发明是关于一种半导体组件，特别是关于一种能达成具较低封装消耗的半导体组件的新颖性、改良制程方法与组件配置，如具有金属氧化物半导体场效应晶体管(MOSFET)芯片的功率组件。
2、背景技术
传统用来容纳并保护芯片所形成的集成电路(IC)装置在封装上面临了许多极限。第一极限是在面积上，这样封装方式所占据的面积是数倍大于该IC芯片。这样的封装尺寸增加了执行封装时电子组件微型化限缩的负担。而且，现有技术的芯片封装所发费的成本相对是较高的，这是起因于必须依赖装卸技术将每一芯片装设于单一组件上。
半导体组件传统封装中的特殊范例是一功率金属氧化物半导体场效应晶体管组件的打线封装。此封装步骤是耗时间且昂贵的。额外的连接线更导致电阻的增加并使之性能降低，此外更在组件运作时同时产生较多的热。为了克服这样的缺点与限制，许多现有技术专利揭露不同的配置与封装过程以减少制造的尺寸与花费。许多现有技术更提供由减少连接线电阻与电感，以改善特征性能的方法与组件配置。
在美国专利6,166,434“Die Chip Assembly for Semiconductor Package”中，发明人Desai，et al.揭露一种粒装芯片，其能使用在半导体覆晶封装上，以取代传统散热片与加固物组合，一种使用粒状芯片的封装方法与一种包含该粒状芯片的半导体封装。在一具体实施例中，粒状芯片是由一片具有高模数与高热传导材料所构成的外壳于封装基质的表面上装设覆盖一晶粒。粒状芯片紧密的贴合于晶粒，仅保留一些环绕在周缘的空间开口，以用来接近晶粒。该如同所揭露的封装结构配置无法很便利应用在动能MOSFET芯片上，起因于实际上没有栅极与源极路径。在此揭露的封装结构所具有的电阻将高于现今使用于MOSFET芯片的金线或者铝线。较小尺寸的凸块或者锡球引起较高的电阻值，起因于晶粒尺寸的限制。较高的电阻是由于附加于板上的小尺寸凸块或者锡球，当凸块或锡球对应于板具有非常有限的接触区域。更者，已揭露的封装结构配置其是利用较难装配的层状板配件接点，因为在覆晶芯片上的凸块与锡球及罩盖于装配过程中各自具有不同的碰触高度。层状板可靠度所潜藏的问题将因为高度差异而产生。
在美国专利6,624,522，“Chip scale surface mounted device and process ofmanufacture”，发明人Standing，et al.揭露一种具有一半导体MOSFET晶粒的芯片尺度封装，其具有一覆盖有一光敏感液态环氧树脂的顶面电极表面，此光敏感液态环氧树脂被图案化以显露出部分电极表面并且扮演钝化层与焊锡罩幕的角色。随后一可焊的接触层形成于该钝化层上。个别的晶粒以漏极端向下于一金属夹上镶嵌或者于一具有漏极电极设计为与沿着容器底端延伸的凸缘共平面的容器镶嵌。然而，此已揭露的封装结构配置的热消散区域是相当有限的。更者，电极表面显露出用来作为锡焊接处的部分将产生降低动能MOSFET组件效能的电阻与电感。
因此，在这技术领域内仍存在对于提供能解决上述限制与缺点的新改善封装结构配置与制程方法的需求。特别是一种能够达到令人满意的改良封装结构配置与制程方法，其能够达成对功率MOSFET组件降低花费、缩小尺寸与改良性能。
发明内容
本发明的主要目的，在于提供一种新的设计与制程方法以及组件结构配置，以供包含、防护与提供电极给予功率MOSFET晶体管，由直接装设引线架于晶体管上，而无需凸块制程，来克服现有技术的限制。
本发明的另一目的，在于提供一种顶面与底面引线架条，其每一个包含有数个用以接收数个镶嵌于底面引线架上如同覆晶的功率晶体管的数个引线架。顶面引线架被镶嵌于具有延伸至底面引线架的延伸电极的底面漏极接触点，因此漏极、栅极与源极电极能形成于引线架条封装的同侧，以便于在不同回路布局使用。
简要的来说在本发明的具体实施例中公开一种包含、防护与提供电性接触点给予一功率晶体管的功率组件封装。此功率组件封装包含有一顶面与一底面引线架，以无凸块的形式直接地依附于功率晶体管上。功率晶体管依附于底面引线架，就像一源极接触点与一栅极接触点直接无凸块依附于底面引线架上的覆晶。功率晶体管具有一用以依附于顶面引线架的底面漏极接触点。顶面引线架更包含有一延伸部，以提供一与底面引线架同侧的本质底面漏极电极。在一具体实施例中，功率晶体管封装更包含有一直接金属熔融接合层或者导电环氧树脂层或者黏着层、焊锡胶、碳胶或者其它形式的依附媒介，以供直接无凸块将功率晶体管依附于底面或者底面引线架其中之一。
为使审查员对本发明的目的、技术内容、特点及所达成的功效有更进一步的了解与认识，通过较佳的实施例图及配合详细的说明，说明如后。
附图说明
图1为本发明的具有顶面与底面引线架且可直接无凸块装配于功率晶体管上图的功率组件封装的剖视图；
图2与图3A～3B为本发明的功率组件封装俯视图与仰视图；
图4与图5为本发明的功率组件封装的两个透视图；
图6A～6C为本发明的列状功率组件封装之一具体实施例制程步骤示意图；
图7A～7C为本发明的列状功率组件封装的另一具体实施例制程步骤示意图；
图8A～8C为本发明的列状功率组件封装的又一具体实施例制程步骤示意图；
图9～图13为数个本发明的功率组件封装的不同电极布局仰视图。
具体实施方式
如图1所示，其是一半导体组件的封装100侧面剖视图，此半导体组件可以如MOSFET组件。此封装100的结构包含有一IC芯片，例如晶粒105覆盖在一导电引线架110上。引线架是一由镀有铝、铜、金与镍的框架所组成或者是其它任何导电架。不像传统的覆晶结构配置，覆晶105被连接至引线架110，而不需要先前技术步骤需于IC芯片上形成作为相互连续的凸块。对于一MOSFET封装，封装100包含三层。顶面导电架120被连接至MOSFET的漏极。MOSFET芯片105是被设置于顶层与底层间。底面导电架110被连接至MOSFET的源极与栅极。
图2是该组件的仰视图。底面引线架110分成一源极部112与一栅极部114。当组件利用铸模化合物进行铸造时，仅有遮蔽区域112、114与120将被暴露出以供接触。为了提高应用的方便性，底面框架110可进一步配置并且线性化，因此能够直接镶嵌于一印刷电路板(PCB)上、卡片或者模块等等上。顶面框架与底面框架也可设计为90°的方式，来取代图2所示。这直接的镶嵌过程可以由焊接、胶黏剂黏着或者任何能够现存的板层配件的技术，例如SMT。
特别是，顶面与底面导电架120与110可包含有一金属结构或者任何其它低电阻传导材料。顶面框架120传输漏极电流。底面框架110包含有两分隔电力引线。引线的其中一传输源极电流，而另一引线传输栅极控制电压。图3A与图3B中呈现出典型的晶粒105的顶表面与底表面布局。不像表面覆盖有一钝化层与接触点的大多数IC晶粒是由穿过接触孔的球状凸块所形成，晶粒105表面不具有钝化层，因此可在晶粒表面上的接触垫上直接制得接触点。在顶面晶粒具有直接连接至半导体结构源极与栅极的源极垫102与一栅极垫104，其是铝或者其它金属接触点。底面具有一大的漏极垫106。
图4是为底面框架110的上表面透视图。如同先前所述，底面框架110被分隔为源极部112与一栅极部114。一位于源极框架112上的向上台阶区113与一位于栅极框架114上的向上台阶区115是被配置以匹配位于晶粒上的源极垫102与栅极垫104，此，当晶粒105覆盖与依靠在底面框架时，晶粒源极垫102与源极向上台阶113深入接触并且晶粒栅极垫104与栅极向上台阶115深入接触。因此源极引线架直接接触芯片的源极主动区域并且栅极引线架直接接触芯片的栅极区域，经由施加超音波、局部热处理、传导环氧树脂/胶、焊锡或者碳型态连接点等，以将芯片与引线架间的接触区域最大化。顶面框架具有相同的台阶结构，因此，可由超音波、局部热处理、传导环氧树脂/胶、焊锡等手段直接与芯片的漏极区域直接接触。由这样直接接触，这样结构的芯片外部的源极与栅极相关电阻与电感将可以显著地减至最小。介于芯片与引线架间的接合区域可被最大化，以减少电阻并且同时使冷却效果最大化。
此封装是利用直接暴露于空气中的顶面与底面框架进行铸模，其提供热直接散逸的窗口。此铸模的封装提供作为封装强度与可靠度的有效机械支撑力，也提供在某些运作环境下对湿气与化学侵害的化学防护。如图5所示，其为具有接触区域125的封装顶面自覆盖有铸模防护壳130的剩余表面显露出的部分的剖视图。
如同上述所述的封装配件是使用较大的金属垫，以作为接触的层状板，使用较大金属垫的来作为接物层状板是较容易的且可靠的。金属导线架120、112、114直接附属于晶粒表面，就像是芯片与板的界面。芯片105与金属导线架120、112、114之间与板上没有凸块或者锡球。由无需要凸块或锡球的附着制程，因此显著的节省成本。如同图1～图5所示的封装结构配置，将使装配更为便利，以下将更进一步解释将此封装结构配置应用在基质装配上的情况。单位生产力与装配花费的改善被达成。此一先前所描述的封装结构配置因为取消传统接触界面需使用凸块或者锡球，而提供了较短的电传导距离，因此具有较低的电感。使用导线架作为附属于源极、栅极与漏极接脚的层状板将使在对相同高度的需求易于达成。封装结构具有最大效率的热消散区域，这样能有效改善封装的热效能。
如图6A～图6C所示，其是封装一利用先前所描述的封装结构配置来执行的列状MOSFET功率组件的第一方法。在图6A中，用来接触MOSFET芯片105的列状顶面导线架120朝上设置在一晶粒装设机械如晶粒放置机(于图中未示)的下方。导电环氧树脂/胶层或者焊锡垫(于图中未示)沈积于芯片垫顶面的上方，成为引线架120的部分。芯片随后放置在支撑垫上并且透过超音波局部加热环氧树脂/胶、焊锡、碳胶伴随底部应用方法装设于引线架上。在另一具体实施例中，无使用环氧树脂/胶、焊锡、碳胶，而是采透过超音波局部热处理，直接以金属熔融接合将晶粒装设于引线架上。在图6B中，包含有源极112与栅极114接触点的底部引线架110被设置于顶面，以与芯片105的源极与栅极接触。底面引线架110利用超音波进行局部加热或者环氧树脂/胶、焊锡或者碳胶等程序装设于芯片上。图6C为一列状功率芯片利用先前所述的步骤封装于引线架顶面与底面的底面视图，其伴随有显示出栅极接触点114、源极接触点112与漏极接触点120并且已可用于装设与设置各种应用回路。
如图7A～7C所示，其是封装一利用先前所描述的封装结构配置来执行的列状MOSFET功率组件的第二方法。在图7A中，用以接触MOSFET芯片105的栅极接触点114与源极接触点112的列状底面引线架110被设置于一晶粒装设机械如晶粒放置机(于图中未示)上。一层导电环氧树脂/胶、焊锡(于图中未示)沈积于芯片垫的上表面上方，作为引线架120之一部分。芯片随后被放置于支撑垫上方并且透过焊锡、碳胶超音波局部热处理伴随一底面应用方法，来装设于导线架上。在另一具体实施例中，无使用环氧树脂/胶、焊锡、碳胶，晶粒，而是采透过超音波局部热处理，直接以金属熔融接合将晶粒装设于引线架上。在图7B中，包含有漏极120接触点的顶面引线架120装设于上方，以与芯片105的漏极接触。顶面引线架120透过利用超音波进行局部加热或者使用环氧树脂/胶、焊锡或者碳胶步骤附着于芯片上。图7C与图6C相同，为一列状动能芯片利用先前所述的步骤封装于引线架顶面与底面的底面视图，其伴随有显示出栅极接触点114、源极接触点112与漏极接触点120并且已可用于装设与设置各种应用回路。
如图8A～8C所示，其是封装一利用先前所描述的封装结构配置来执行的列状MOSFET功率组件的第三方法。在图8A中，晶粒105被置放于UV薄膜顶端条109上，UV薄膜顶端条109是依据晶粒的设置而为不锈钢或者硬的塑料组成。在图7B中，具有源极接触点112与栅极接触点114的列状底面引线架110整体透过上方超音波的应用、局部热处理、导电环氧树脂/胶、焊锡、碳胶等设置于晶粒上。在图8C中，上述的源极与栅极引线架110自上述晶粒表面被正面覆盖UV薄膜顶端条109。依循于顶面框架120上的附加物的步骤(如同图7B所示)完成装配一列状动力组件的封装过程(如同图6C与图7C)。
上述描述制程方法的部分是概述封装装配的流程，以作为本发明的较佳具体实施例，其是与目前的芯片安装与打线接合过程不相同。由这些新的方法与结构配置，功率MOSFET封装可因为电性、机械与化学需求于制程中将成本有效降低，并提高配线的效益。
由应用上述的制程步骤，此封装结构也可用于具有结合上述晶包结构的数个芯片应用，举例来说，两芯片与数个芯片封装等，如同图9～13所示。伴随列状引线架的些许修饰，底面引线架与顶面引线架间夹角为90度将是可能的。顶面引线架与底面引线架材料的选用与封装的结果、芯片表面底面冶金、热膨胀、电气、机械与化学需求将息息相关。
相较于现今的覆晶封装技术，本发明的封装具有较佳的电性与机械性能，同时成本是较低的。这个技术解决了习知覆晶技术需使用材质为金的凸块、焊锡凸块作为连接点。源极、栅极与漏极的芯片表面整体被传导引线架接合并覆盖，以接收较低的电阻与电感，虽然最大的横截面面积与最短的接合区域，作为晶粒与引线架间的传导。特别的是在这个超音波接合引线架与芯片的范例中，引线架被直接接合至芯片的源极、栅极与漏极，无需其它组件。本发明不仅解决了习知覆晶技术需使用材质为金的凸块、焊锡凸块作为连接点的技术，也消弥了凸块相关的制程与材料需求，举例来说如底部充填剂。就封装与层状板两者的电阻与电感而论，本技术相较于现在存在的覆晶技术，如球栅数组封装(BGA)、金凸块或者芯片尺寸封装，与打线接合技术而言是较为优秀的。就可靠度的观点而论，相较于其它使用任何型态凸块的既存覆晶技术来说，本发明拥有较多较可靠的构成要素与层状板连接，因为本发明具有较大的可利用接合区域与机械及化学强度。
相较于目前的利用金、铝与铜等材质所进行的打线接合、金属带、磁带、片状接合技术，本发明也具有较佳的电性与机械特性，例如电阻、电感、机械强度与可靠度。更者，本发明也消除了这些复杂的制程步骤与需使用较为昂贵的线材或者金属带材料，因此本发明的封装在组成价格与层状板配件成本上较为优势。这简化的制程步骤相较于目前得覆晶技术与打线、金属带或者磁带或者片状接合技术而言，大幅度地增加整个装配线的单位生产力的装配产率。本发明可用来取代大部分现有的功率组件封装，包含打线接合、金属带或者磁带或者片状接合、BGA覆晶、CSP、片段接合等等，以减少制程花费、增加产品可靠度与改善组件效能。
以上所述，仅为本发明一较佳实施例而已，并非用来限定本发明实施的范围，故凡依本发明权利要求所述的形状、构造、特征及精神所为的均等变化与修饰，均应包括于本发明的权利要求的范围内。

Claims (24)

1.一种包含、保护与提供电性接点给一功率晶体管的功率组件封装，其特征在于，包括有：
一顶面与一底面引线架，以无凸块的形式直接装设于该功率晶体管上。
2.如权利要求1所述的功率组件封装，其特征在于，其中该功率晶体管附于该底面引线架上，如同一具有一源极接触点与一栅极接触点的覆晶无凸块直接附于该底面引线架上。
3.如权利要求1所述的功率组件封装，其特征在于，其中该功率晶体管具有一底面漏极接触点，其依附于该顶面引线架。
4.如权利要求1所述的功率组件封装，其特征在于，其中该功率组件具有一底面漏极接触点，其依附于该顶面引线架，其中该顶面引线架更具有一延伸部，以提供一与该底面引线架同侧的底面漏极电极。
5.如权利要求1所述的功率组件封装，其特征在于，其更包含有：
一金属接合层，以供无凸块直接附加该功率晶体管于一该顶面引线架与底面引线架。
6.如权利要求1所述的功率组件封装，其特征在于，其更包含有：
一导电胶环氧树脂层，其是以供无凸块直接附加该功率晶体管于一该顶面引线架与底面引线架。
7.如权利要求1所述的功率组件封装，其特征在于，其更包含有：
一导电胶层，其是以供无凸块直接附加该功率晶体管于一该顶面引线架与底面引线架。
8.如权利要求1所述的功率组件封装，其特征在于，其更包含有：
一焊锡附着物，其是以供无凸块直接附加该功率晶体管于一该顶面引线架与底面引线架。
9.如权利要求1所述的功率组件封装，其特征在于，其更包含有：
一碳胶层，其是以供无凸块直接附加该功率晶体管于一该顶面引线架与底面引线架。
10.一种包含、保护与提供电性接点给数个功率晶体管的功率组件封装，其特征在于，其包括有：
一顶面与一底面引线架条，其每一个包含有数个顶面与底面引线架，其中每一该顶面与该底面引线架备用来无凸块直接依附于该数个功率晶体管上。
11.如权利要求10所述的功率组件封装，其特征在于，其中该数个功率晶体管的每一个附于该底面引线架中之一，如同一具有一源极接触点与一栅极接触点的覆晶无凸块直接附于该底面引线架上。
12.如权利要求10所述的功率组件封装，其特征在于，其中每一该功率晶体管具有一底面漏极接触点，其依附于该顶面引线架其中之一。
13.如权利要求10所述的功率组件封装，其特征在于，其中每一该功率组件具有一底面漏极接触点，其依附于该顶面引线架的其中之一，其中该顶面引线架更具有一延伸部，以提供一与该底面引线架同侧的底面漏极电极。
14.如权利要求10所述的功率组件封装，其特征在于，其更包含有：
一导电胶环氧树脂层，其是用于供无凸块直接附加每一该功率晶体管于一该顶面引线架与底面引线架其中之一。
15.如权利要求10所述的功率组件封装，其特征在于，其更包含有：
一导电胶层，其是用于供无凸块直接附加每一该功率晶体管于一该顶面引线架与底面引线架其中之一。
16.如权利要求10所述的功率组件封装，其特征在于，其更包含有：
一焊锡附着物，其是用于供无凸块直接附加每一该功率晶体管于一该顶面引线架与底面引线架其中之一。
17.如权利要求10所述的功率组件封装，其特征在于，其更包含有：一碳胶层，其是用于供无凸块直接附加每一该功率晶体管于一该顶面引线架与底面引线架其中之一。
18.一种包含、保护与提供电性接点给数个功率晶体管的封装方法，其特征在于，其包括有下列步骤：
将一顶面与底面引线架条依附于该数个功率晶体管，其利用无凸块直接将该顶面与底面引线架条的数个顶面引线架与底面引线架依附于该数个功率晶体管。
19.如权利要求18所述的方法，其特征在于，其中：
该无凸块直接将该底面引线架依附于该功率晶体管上的步骤更包含有将每一该数个功率晶体管依附于该底面引线架上的步骤，如同具有一源极接触点与一栅极接触点的覆晶无凸块直接地依附于该底面引线架；
如权利要求17所述的方法，其特征在于，其中：
该以无凸块直接将该顶面引线架依附于该功率晶体管上的步骤更包含有将位在每一个该功率晶体管上的底面漏极接触点依附于该任一顶面引线架的步骤。
20.如权利要求18所述的方法，其特征在于，其中：
该以无凸块直接将该顶面引线架依附于该功率晶体管上的步骤更包含有将位在每一该功率晶体管上之一底面漏极接触点依附于该顶面引线架任一的步骤；以及
提供一作为一位于该顶面引线架的底面漏极电极的延伸电极，以供延伸该底面漏极电极与该底面引线架同侧。
21.如权利要求18所述的方法，其特征在于，其更包含：
由涂布一导电环氧树脂层，以进行一无凸块直接依附的方式，将每一该功率晶体管依附于该顶面与底面引线架其中之一上。
22.如权利要求18所述的方法，其特征在于，其更包含：
由涂布一导电胶层，以进行一无凸块直接依附的方式，将每一该功率晶体管依附于该顶面与底面引线架其中之一上。
23.如权利要求18所述的方法，其特征在于，其更包含：
由涂布一焊锡胶，以进行一无凸块直接依附的方式，将每一该功率晶体管依附于该顶面与底面引线架其中之一上。
24.如权利要求18所述的方法，其特征在于，其更包含：
由涂布一碳胶，以进行一无凸块直接依附的方式，将每一该功率晶体管依附于该顶面与底面引线架其中之一上。
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