CN108074886B - 半导体装置封装及其制造方法 - Google Patents
半导体装置封装及其制造方法 Download PDFInfo
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- CN108074886B CN108074886B CN201710998266.3A CN201710998266A CN108074886B CN 108074886 B CN108074886 B CN 108074886B CN 201710998266 A CN201710998266 A CN 201710998266A CN 108074886 B CN108074886 B CN 108074886B
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Abstract
本发明的各种实施例涉及一种半导体装置封装,所述半导体装置封装包含载体、电组件、天线、导电垫及导电线所述载体包含顶表面所述电组件安置在所述载体的所述顶表面上方所述天线安置在所述载体的所述顶表面上方且与所述电组件间隔开所述导电垫安置在所述载体的所述顶表面上方且在所述天线下方,其中所述导电垫包含共振结构所述导电线电连接到所述电组件且在所述载体内延伸所述导电线的部分在所述天线及所述导电垫的所述共振结构下方。
Description
技术领域
本发明涉及一种半导体装置封装及一种制造所述半导体装置封装的方法,且更特定来说,涉及一种具有天线及屏蔽盖的半导体装置封装及一种制造所述半导体装置的方法。
背景技术
无线通信装置(例如移动电话)通常包含用于发射及接收射频(RF)信号的天线常规地,无线通信装置包含天线及通信模块,天线及通信模块各自安置在电路板的不同部分上在常规方法下,天线及通信模块是单独制造且在经放置在电路板上之后电连接在一起因此,两个组件可产生单独的制造成本此外,可能难以减小无线通信装置的大小以获得适合紧凑的产品设计另外,天线与通信模块之间的RF信号发射路径可较长,借此降低在天线与通信模块之间发射的信号的质量。
发明内容
根据本发明的一些实施例,半导体装置封装包含载体、电组件、天线、导电垫及导电线所述载体包含顶表面所述电组件安置在所述载体的所述顶表面上方所述天线安置在所述载体的所述顶表面上方且与所述电组件间隔开所述导电垫安置在所述载体的所述顶表面上方且在所述天线下方,其中所述导电垫包含共振结构所述导电线电连接到所述电组件且在所述载体内延伸所述导电线的一部分位于所述天线及所述导电垫的所述共振结构下方。
根据本发明的一些实施例,半导体装置封装包含载体、电组件、导电垫、天线及导电线载体包含顶表面及导电线所述电组件安置在所述载体的所述顶表面上方导电垫形成在载体的顶表面上方且在天线下方,其中导电垫包含共振结构天线安置在载体的顶表面上方且与主动装置间隔开导电线电连接到电组件且经由导电垫的共振结构电磁耦合到天线。
附图说明
图1A说明根据本发明的一些实施例的半导体装置封装的横截面图。
图1B说明根据本发明的一些实施例的图1A中所展示的半导体装置封装的一部分的俯视图。
图2A说明根据本发明的一些实施例的半导体装置封装的横截面图。
图2B说明根据本发明的一些实施例的半导体装置封装的俯视图。
图3A说明根据本发明的一些实施例的半导体装置封装的横截面图。
图3B说明根据本发明的一些实施例的图3A中所展示的半导体装置封装的一部分的放大图。
图4A说明根据本发明的一些实施例的半导体装置封装的横截面图。
图4B说明根据本发明的一些实施例的半导体装置封装的横截面图。
图5说明根据本发明的一些实施例的天线的横截面图。
图6说明根据本发明的一些实施例的天线的横截面图。
图7说明根据本发明的一些实施例的天线的横截面图。
图8说明根据本发明的一些实施例的天线的横截面图。
贯穿图式及详细描述使用共用参考编号来指示相同或类似组件本发明从结合附图进行的以下详细描述将更显而易见。
具体实施方式
图1A说明根据本发明的一些实施例的半导体装置封装1的横截面图半导体装置封装1包含载体10、电组件11、天线12、导电线13及导电垫14。
载体10包含顶表面101。载体10可为例如印刷电路板,例如纸基铜箔层压板、复合铜箔层压板或聚合物浸渍玻璃纤维基铜箔层压板载体10可包含用于电组件11与安装在载体10上的其它电组件之间的电连接的互连结构,例如分布层(RDL)。在一些实施例中,载体10的相对电容率(例如,介电常数)在从约2到约4的范围内。
电组件11在载体10的顶表面101上。电组件11可包含有源电组件及/或无源电组件电组件11可经由一或多个电连接11b倒装芯片接合到载体10的顶表面101电连接11b可为例如焊料球或铜(Cu)柱在一些实施例中,每一电连接11b的直径或高度是在从约250微米(μm)到约400μm的范围内在一些实施例中,电组件11可经由一或多个接合线线接合到载体10的顶表面101电组件11可为例如集成电路(IC)芯片或裸片在一些实施例中,电组件11可包含一或多个被动元件,例如电容器、电阻器、电感器或其组合
在一些实施例中,天线12在载体10的顶表面101上。天线12与电组件11间隔开。天线12包含第一导电层12m1、第二导电层12m2及介电层12d第一导电层12m1附接(或耦合)到介电层12d的顶表面第二导电层12m2附接到介电层12d的底表面在一些实施例中,介电层的厚度为约80μm在一些实施例中,第一导电层12m1及第二导电层12m2包含镍(Ni)、铂(Pt)、金(Au)或其组合天线12可为(例如)贴片天线在一些实施例中,天线12经由一或多个电连接12b倒装芯片接合到载体10的顶表面101以使得在介电层12d的底表面与载体10的顶表面101之间形成距离d以用于微波或无线电波辐射电连接12b可为(例如)焊料球或Cu柱在一些实施例中,每一电连接12b的直径或高度d在从约250μm到约400μm的范围内
在一些实施例中,天线12经配置以发射或接收具有在从约56千兆赫(GHz)到约64GHz的范围内的频率的电磁波在一些实施例中,天线12包含大于约7GHz的带宽及大于10分贝(dB)的增益。
在一些实施例中,导电垫14位于载体10的顶表面101上且在天线12下方。例如,导电垫14位于载体10与天线12之间。导电垫14包含孔隙14h导电垫14包含共振结构在一些实施例中,导电垫14与天线间隔从约250μm到约400μm的距离
在一些实施例中,导电线13安置在载体10内。在一些实施例中,导电线13的部分或第一部分位于或安置在载体10的顶表面101上。导电线13可经由电连接11b中的一或多者电连接到电组件11导电线13的部分或第二部分在导电垫14及天线12下方延伸。例如,载体10的顶表面101与导电线13分离一距离导电线13可经由导电垫14的共振结构电磁耦合到天线12。在一些实施例中,导电线13为用以电磁耦合或接收由天线12接收的信号且将所耦合或接收信号发射到电组件11的馈线。替代地,导电线13可为用以电磁耦合或接收来自电组件11的信号并将所述信号发射到天线12的馈线,且于是信号可被天线12接收。
图1B说明根据一些实施例的半导体装置封装1的部分(在图1A中经标记为“A”的部分)的俯视图
如在图1B中所展示,导电垫14包含孔隙14h导电线13的部分在导电垫14的孔隙14h下方延伸。换句话说,孔隙14h可安置在导电线13的部分上方。在一些实施例中,安置在孔隙14h下方的导电线13的部分的延伸方向为基本上垂直于导电垫14的孔隙14h的长度尺寸的延伸方向。孔隙14h的宽度尺寸可小于第二导电层12m2的宽度尺寸。
在一些实施例中,贴片天线可嵌入于衬底内且电磁耦合到嵌入于所述衬底内的馈线由于衬底的高介电常数(例如,在从约2到约4的范围内),因此可降低贴片天线与馈线之间的耦合效率为了减小贴片天线与馈线之间的介电常数,可在贴片天线与馈线之间且在衬底内形成腔然而,腔的形成可增加衬底的总厚度且弱化衬底的结构,此可导致衬底崩陷
根据一些实施例(例如,如在图1A中所展示),天线12形成在介电层12d上,所述介电层可倒装芯片接合到载体10的顶表面101,且在介电层12d与载体10的顶表面101之间形成距离d。天线12与导电垫14之间的介质为空气,空气包含低介电常数(例如,约1)因此,天线12及导电垫14可包含经改进耦合效率另外,由于在介电层12d与载体10的顶表面101之间形成距离d,因此可不利用在载体10内部形成的腔与本发明的一些实施例(例如,其包含耦合到衬底的天线)比较,半导体装置封装1可为较厚的,此可继而减少半导体装置封装1的总容积及半导体装置封装1的制造成本。
图2A说明根据本发明的一些实施例的半导体装置封装2的横截面图半导体装置封装2包含底面载体20、第一电组件21、第一天线22、第一导电线23、导电垫24、顶面载体25、第二电组件26、第二天线27及第二导电线28。
顶面载体25包含顶表面或第一表面251及与顶表面或第一表面251相对的底表面或第二表面252载体25可为例如印刷电路板,例如纸基铜箔层压板、复合铜箔层压板或聚合物浸渍玻璃纤维基铜箔层压板。顶面载体25可包含用于第二电组件26与安装在顶面载体25上的其它电组件之间的电连接的互连结构25r,例如RDL。在一些实施例中,顶面载体25的介电常数在从约2到约4的范围内。
第二电组件26安置在顶面载体25的顶表面251上。第二电组件26可包含有源电组件及/或无源电组件第二电组件26可经由一或多个电连接26b倒装芯片接合到顶面载体25的顶表面251电连接26b可为例如接触垫、焊料球或Cu柱在一些实施例中,每一电连接26b的直径或高度在从约250μm到约400μm的范围内在一些实施例中,第二电组件26可经由一或多个接合线线接合到顶面载体25的顶表面251第二电组件26可为例如IC芯片(例如,互补金属氧化物半导体(CMOS)收发器)或裸片在一些实施例中,第二电组件26可包含被动元件,例如,电容器、电阻器、电感器或其组合
底面载体20包含顶表面或第一表面201及与顶表面或第一表面201相对的底表面或第二表面202底面载体20可为例如印刷电路板,例如纸基铜箔层压板、复合铜箔层压板或聚合物浸渍玻璃纤维基铜箔层压板。底面载体20可包含用于第一电组件21与安装在底面载体20上的其它电组件之间的电连接的互连结构,例如RDL。在一些实施例中,底面载体20的介电常数在从约2到约4的范围内。一或多个电连接20b附接到底面载体20的底表面202。电连接20b可为例如导电垫、焊料球或CU柱。
在一些实施例中,第一电组件21在底面载体20的顶表面201上。第一电组件21可包含有源电组件及/或无源电组件第一电组件21可经由一或多个电连接21b倒装芯片接合到底面载体20的顶表面201电连接21b可为例如接触垫、焊料球或Cu柱在一些实施例中,每一电连接21b的直径或高度在从约250μm到约400μm的范围内在一些实施例中,第一电组件可经由一或多个接合线线接合到底面载体20的顶表面201第一电组件21可为例如IC芯片(例如,CMOS收发器)或裸片在一些实施例中,第一电组件21可包含被动元件,例如,电容器、电阻器、电感器或其组合
顶面载体25经由一或多个电连接25b接合到底面载体20的顶表面201电连接25b可包含例如焊料球或Cu柱。
在一些实施例中,第一天线22安置在顶面载体25的底表面252上。第一天线22与第二电组件26间隔开。第一天线22包含第一导电层22m1及第二导电层22m2第一导电层22m1与第二导电层22m2分离或间隔在一些实施例中,第一导电层22m1及第二导电层22m2包含Ni、Pt、Au或其组合第一天线22可包含例如贴片天线
在一些实施例中,第一天线22经配置以在第一方向发射或接收包含在从约56GHz到约64GHz的范围内的频率的电磁波在一些实施例中,第一方向基本上垂直于顶面载体25的顶表面251。在一些实施例中,第一天线22包含大于约7GHz的带宽及大于约10dB的增益。
在一些实施例中,导电垫24安置在底面载体20的顶表面201上且与第一天线22相对(例如,与第一天线22对准)导电垫24包含对应于第一天线22(例如,与其对准)的孔隙24h。导电垫24可包含共振结构
第一导电线23在底面载体20内。在一些实施例中,第一导电线23的部分或第一部分形成在底面载体20的顶表面201上。第一导电线23可经由电连接21b中的一或多者电连接到第一电组件21第一导电线23的部分或第二部分在导电垫24下方延伸第一导电线23可经由导电垫24的共振结构电磁耦合到第一天线22。在一些实施例中,第一导电线23为用以电磁耦合或接收由第一天线22接收的信号且将所耦合或接收信号发射到第一电组件21的馈线。替代地,第一导电线23可为用以电磁耦合或接收来自第一电组件21的信号并将所接收信号发射到第一天线22的馈线,且于是信号可被第一天线22接收。
在一些实施例中,第二天线27安置在顶面载体25的底表面252上且与第一天线22间隔开。第二天线27可包含例如宇田-八木(Yagi-Uda)天线在一些实施例中,第二天线27的部分位于未接地的顶面载体25内的区域25a处
在一些实施例中,第二天线27经配置以在第二方向发射或接收具有在从约56GHz到约64GHz的范围内的频率的电磁波在一些实施例中,电磁波发射朝向第二天线27或由第二天线27接收电磁波的第二方向不同于电磁波发射朝向第一天线22或由第一天线接收的电磁波的第一方向。在一些实施例中,第二方向基本上垂直于第一方向在一些实施例中,第二天线27包含大于约7GHz的带宽及大于10dB的增益
在一些实施例中,第二导电线28安置在顶面载体25的底表面252上且与第二天线27间隔开。第二导电线28可经由电连接26b中的一或多者电连接到第二电组件26第二导电线28可电磁耦合的第二天线27。
在一些实施例中,贴片天线可嵌入于衬底内且电磁耦合的嵌入于所述衬底内的馈线由于衬底的高介电常数(例如,在从约2到约4的范围内),因此可降低贴片天线与馈线之间的耦合效率为了减小贴片天线与馈线之间的介电常数,可在贴片天线与馈线之间且在衬底内形成腔然而,腔的形成可增加衬底的总厚度且弱化衬底的结构,此可导致衬底崩陷
根据第二实施例(例如,如在图2B中所展示),第一天线22与导电垫24之间的介质为空气,空气包含低介电常数(比如,约1)因此,第一天线22及导电垫24可包含经改进耦合效率另外,可不利用形成在顶面载体25或底面载体20内部的腔此外,图2B中所展示的半导体装置封装2可包含层叠封装(PoP)结构,此可减少半导体装置封装2的总面积及半导体装置封装2的制造成本。
图2B说明根据本发明的一些实施例的顶面载体25的俯视图顶面载体25包含第二电组件26、第一天线22、第二天线27及第二导电线28。还说明底面载体20的第一导电线23。
在一些实施例中,第一天线22位于第二电组件26的第一侧处且与第二电组件26间隔开。第一天线22可为例如贴片天线天线22经配置以在第一方向发射或接收包含在从约56GHz到约64GHz的范围内的频率的电磁波在一些实施例中,第一天线22包含大于约7GHz的带宽及大于10dB的增益。
在一些实施例中,第二天线27在第二电组件26的第二侧处且与第二电组件26间隔开。在一些实施例中,第二电组件26的第一侧不同于第二电组件26的第二侧。替代地,第二电组件26的第一侧可与第二电组件26的第二侧相同。第二天线27可为例如宇田-八木天线第二天线27的部分位于未接地的顶面载体25内的区域25a处
在一些实施例中,第二天线27经配置以在第二方向发射或接收包含从约56GHz到约64GHz的频率的电磁波在一些实施例中,电磁波发射朝向第二天线27或由第二天线27接收电磁波的第二方向不同于电磁波发射朝向第一天线22或由第一天线接收的电磁波的第一方向。在一些实施例中,第二方向基本上垂直于第一方向。在一些实施例中,第二天线27包含大于约7GHz的带宽及大于10dB的增益。
在一些实施例中,第一导电线23在第一天线22下方延伸。在一些实施例中,第一导电线23为电磁耦合到第一天线22的馈线。第二导电线28为电磁耦合到第二天线27的馈线。电连接25b围绕第一天线22、第二电组件26及第二天线27。
图3A说明根据本发明的一些实施例的半导体装置封装3的横截面图半导体装置封装3包含第一介电层30、电组件31、第二介电层32、第三介电层33、第一保护层34、第二保护层35及天线37。
第一介电层30包含顶表面301及与顶表面301相对的底表面302。第一介电层30可包含(但不限于)模塑料或预浸渍复合纤维(例如,预浸材料)模塑料的实例可包含(但不限于)环氧树脂(包含分散其中的填料)预浸材料的实例可包含(但不限于)通过堆叠或层压多个预浸渍材料及/或片料所形成的多层结构。
在一些实施例中,电组件31嵌入或位于第一介电层30内。电组件31可包含有源电组件及/或无源电组件电组件31可为例如IC芯片或裸片在一些实施例中,电组件31可包含被动元件,例如,电容器、电阻器、电感器或其组合
在一些实施例中,第二介电层32在第一介电层30的顶表面301上。第二介电层32可包含(但不限于)模塑料或预浸渍复合纤维(例如,预浸材料)模塑料的实例可包含(但不限于)环氧树脂(包含分散其中的填料)预浸材料的实例可包含(但不限于)通过堆叠或层压多个预浸渍材料及/或片料所形成的多层结构在一些实施例中,第二介电层32由不同于第一介电层30的材料的材料形成。替代地,第二介电层32可由与第一介电层30的材料相同的材料形成。
在一些实施例中,天线37位于第二介电层32上。天线37可经由电连接37a(例如,探针馈电)电连接到电组件31天线37可为例如贴片天线在一些实施例中,天线37经配置以发射或接收包含在从约56GHz到约64GHz的范围内的频率的电磁波在一些实施例中,天线37包含大于约7GHz的带宽及大于10dB的增益。
在一些实施例中,第一保护层34安置在第二介电层32上且覆盖天线37及第二介电层32的一或多个部分。在一些实施例中,第一保护层34包含抗焊剂层或防焊掩模
在一些实施例中,第三介电层33附接或耦合到第一介电层30的底表面302上。第三介电层33可包含(但不限于)模塑料或预浸渍复合纤维(例如,预浸材料)模塑料的实例可包含(但不限于)环氧树脂(包含分散其中的填料)预浸材料的实例可包含(但不限于)通过堆叠或层压多个预浸渍材料及/或片料所形成的多层结构在一些实施例中,第三介电层33由不同于第一介电层30的材料的材料形成。替代地,第三介电层33可由与第一介电层30的材料相同的材料形成。
在一些实施例中,第二保护层35附接或耦合到第三层33。在一些实施例中,第二保护层35为抗焊剂层或防焊掩模
在一些实施例中,一或多个电连接38穿透第一介电层30、第二介电层32及第三介电层33且将电组件31电连接到第一介电层30内到其它电组件或连接到外部电路自第一保护层34或第二保护层35暴露电连接38的一部分或多个部分。自第二保护层35暴露的电连接38的所述部分或多个部分经电连接到一或多个焊料球36。
图3B说明根据本发明的一些实施例的半导体装置封装3的经放大部分,放大自图3A中经标记为“B”的虚线正方形区域进行在一些实施例中,自第一介电层30的顶表面301到天线37测量的电连接37a的长度L在从约112μm到约144μm范围内
与在贴片天线与裸片之间包含长电连接(例如,约500μm)的半导体装置封装相比较,半导体装置封装3包含较短电连接37a,此可继而减少天线37与电组件31之间的发射损失及半导体装置封装3的总容积。天线37可经由电连接37a电连接到电组件31。
图4A说明根据本发明的一些实施例的半导体装置封装4的横截面图半导体装置封装4包含第一介电层40、电组件41、第二介电层42、第三介电层43、第一保护层44、第二保护层45及天线47。
第一介电层40包含顶表面401及与顶表面401相对的底表面402。第一介电层40可包含(但不限于)模塑料或预浸渍复合纤维(例如,预浸材料)模塑料的实例可包含(但不限于)环氧树脂(包含分散其中的填料)预浸材料的实例可包含(但不限于)通过堆叠或层压多个预浸渍材料及/或片料所形成的多层结构。
在一些实施例中,电组件41嵌入或位于第一介电层40内。电组件41可包含有源电组件及/或无源电组件电组件41可为例如IC芯片或裸片在一些实施例中,电组件31可包含被动元件,例如,电容器、电阻器、电感器或其组合
在一些实施例中,第二介电层42安置在第一介电层40的顶表面401上。第二介电层42可包含(但不限于)模塑料或预浸渍复合纤维(例如,预浸材料)模塑料的实例可包含(但不限于)环氧树脂(包含分散其中的填料)预浸材料的实例可包含(但不限于)通过堆叠或层压多个预浸渍材料及/或片料所形成的多层结构在一些实施例中,第二介电层42由不同于第一介电层40的材料的材料形成。替代地,第二介电层42可由与第一介电层40的材料相同的材料形成。
在一些实施例中,天线47安置在第二介电层42上。天线47可为(例如)贴片天线在一些实施例中,天线47经配置以发射或接收包含在从约56GHz到约64GHz的范围内的频率的电磁波在一些实施例中,天线47包含大于约7GHz的带宽及大于10dB的增益。
在一些实施例中,导电垫49嵌入于第二介电层42内且由第二介电层42囊封。导电垫49在天线47下方。导电垫49包含孔隙49h导电垫49可包含共振结构
在一些实施例中,导电线411安置在第一介电层40上且由第二介电层42囊封。导电线411经由一或多个电连接而电连接到电组件41导电线411的部分在导电垫49及天线47下方延伸导电线411可经由导电垫49的共振结构电磁耦合到天线47。在一些实施例中,导电线411为用以电磁耦合或接收由天线47接收的信号且将所耦合或接收信号发射到电组件41的馈线。替代地,导电线411可为用以电磁耦合或接收来自电组件41的信号并将所述所接收信号发射到天线47的馈线,且于是信号可被天线47接收。
在一些实施例中,第一保护层44安置在第二介电层42上且覆盖天线47及第二介电层42的一部分或多个部分。在一些实施例中,第一保护层44为抗焊剂层或防焊掩模
在一些实施例中,多个电连接48穿透第一介电层40及第二介电层42或安置于其中且将电组件41电连接到第一介电层40内的其它电组件或连接到外部电路自第一保护层44或第二保护层45暴露电连接48的一部分或多个部分。自第二保护层45暴露的电连接48的所述部分或多个部分经电连接到一或多个焊料球46。
图4B说明根据本发明的一些实施例的半导体装置封装4的横截面图半导体装置封装4包含第一介电层40、电组件41、第二介电层42、第一保护层44、第二保护层45、天线47、导电垫49及导电线411。
第一介电层40包含顶表面401及与顶表面401相对的底表面402。第一介电层40可包含(但不限于)模塑料或预浸渍复合纤维(例如,预浸材料)模塑料的实例可包含(但不限于)环氧树脂(包含分散其中的填料)预浸材料的实例可包含(但不限于)通过堆叠或层压多个预浸渍材料及/或片料所形成的多层结构。
在一些实施例中,第二保护层45附接或耦合到第一介电层40的底表面402。在一些实施例中,第二保护层45为抗焊剂层或防焊掩模
电组件41嵌入或位于第一介电层40及第二保护层45内。电组件41可包含有源电组件及/或无源电组件电组件41可为例如IC芯片或裸片在一些实施例中,电组件41可包含被动元件,例如,电容器、电阻器、电感器或其组合。
在一些实施例中,第二介电层42安置在第一介电层40的顶表面401上。第二介电层42可包含(但不限于)模塑料或预浸渍复合纤维(例如,预浸材料)模塑料的实例可包含(但不限于)环氧树脂(包含分散其中的填料)预浸材料的实例可包含(但不限于)通过堆叠或层压多个预浸渍材料及/或片料所形成的多层结构在一些实施例中,第二介电层42由不同于第一介电层40的材料的材料形成。替代地,第二介电层42可由与第一介电层40的材料相同的材料形成。
在一些实施例中,天线47安置在第二介电层42上。天线47可为(例如)贴片天线在一些实施例中,天线47经配置以发射或接收包含在从约56GHz到约64GHz的范围内的频率的电磁波在一些实施例中,天线47包含大于约7GHz的带宽及大于10dB的增益。
在一些实施例中,导电垫49嵌入于第二介电层42内且由第二介电层42囊封。导电垫49在天线47下方。导电垫49包含孔隙49h导电垫49可包含共振结构
在一些实施例中,导电线411安置在第一介电层40上且由第二介电层42囊封。导电线411经由一或多个电连接而电连接到电组件41导电线411的部分在导电垫49及天线47下方延伸导电线411可经由导电垫49的共振结构电磁耦合到天线47。在一些实施例中,导电线411为用以电磁耦合或接收由天线47接收的信号且将所耦合或接收信号发射到电组件41的馈线。替代地,导电线411可为用以电磁耦合或接收来自电组件41的信号并将所述所接收信号发射到天线47的馈线,且于是信号可被天线47接收。
在一些实施例中,第一保护层44安置在第二介电层42上且覆盖天线47及第二介电层42的一部分或多个部分。在一些实施例中,第一保护层44为抗焊剂层或防焊掩模
在一些实施例中,多个电连接48穿透第一介电层40或安置于其中且将电组件41电连接到第一介电层40内的其它电组件或连接到外部电路
图5说明根据本发明的一些实施例的天线5天线5可为宇田-八木天线天线5包含第一驱动部分5A、第二驱动部分5B及馈线50。
第一驱动部分5A包含导向器51A及驱动器52A导向器51A与驱动器52A物理上分离或间隔,且与驱动器52A电磁耦合在一些实施例中,导向器51A的长度L1小于驱动器52A的长度L2。
第二驱动部分5B包含导向器51B及驱动器52B导向器51B与驱动器52B物理上分离或间隔,且与驱动器52B电磁耦合在一些实施例中,导向器51B的长度L3小于驱动器52B的长度L4第一驱动部分5A的驱动器52A的长度L2不同于第二驱动部分5B的驱动器52B的长度L4在一些实施例中,L3对L4的比率在从约1.1到约1.3的范围内
在比较的宇田-八木天线中,第一驱动部分的驱动器的长度与第二驱动部分的长度相同为了增加天线的增益或带宽,可使用多个天线阵列,此可增加芯片的总面积及制造成本与比较的宇田-八木天线相比较,图5中的天线5通过利用天线5的驱动器52A、52B的不同长度(例如,L2、L4)而不增加天线的数目而包含获得较高增益及带宽在一些实施例中,天线5可应用于图1A、2A、3A及4A中所展示的半导体装置封装1、2、3、4中的任一者,且天线5可有效地减少半导体装置封装的总面积及制造成本。
图6说明根据本发明的一些实施例的天线6天线6包含类似于图5中所展示的天线5的第一驱动部分5A的配置的配置。然而,在一些实施例中,天线6的驱动器62并不平行于天线6的导向器61。在一些实施例中,驱动器62及导向器61包含在从约10o到约25o的范围内的角度。
与其中导向器平行于驱动器的比较的宇田-八木天线相比较,图6中所展示的天线6可包含较高增益及带宽在一些实施例中,天线6可应用于图1A、2A、3A、4A及4B中所展示的半导体装置封装1、2、3、4中的任一者,且可有效地减少半导体装置封装的总面积及制造成本。
图7说明根据本发明的一些实施例的天线7在一些实施例中,天线7为贴片天线天线7包含馈线70、第一部分7A及第二部分7B。
在一些实施例中,第一部分7A包含贴片区71A及孔隙72A孔隙72A包含第一部分72A1及基本上垂直于第一部分72A1的第二部分72A2在一些实施例中,孔隙72A包含H形状。
在一些实施例中,第一部分7A包含贴片区71B及孔隙72B孔隙72B包含第一部分72B1及基本上垂直于第一部分72B1的第二部分72B2在一些实施例中,孔隙72B包含H形状贴片区71B的面积可与贴片区71A的面积基本上相同在其它实施例中,孔隙72B的面积不同于孔隙72A的面积举例来说,孔隙72B的第一部分72B1的长度可长于孔隙72A的第一部分72A1的长度,且孔隙72B的第二部分72B2的长度可长于孔隙72A的第二部分72A2的长度在一些实施例中,孔隙72B的面积为孔隙72A的面积的1.5倍大。
在比较贴片天线中,两个贴片区的大小可不同与比较的贴片天线相比较,图7中所展示的天线7可通过使用包含相同大小的两个贴片区及使用包含不同大小的两个孔隙而包含较高增益及带宽在一些实施例中,天线7的带宽为比较的贴片天线的带宽的约1.3倍大在一些实施例中,天线7可应用于图1A、2A、3A、4A及4B中所展示的半导体装置封装1、2、3、4中的任一者。
图8说明根据本发明的一些实施例的天线8天线8可类似于图7中所展示的天线7,除孔隙82A及82B进一步包含各别第三部分82A3、82B3以外
在一些实施例中,孔隙82A的第三部分82A3位于孔隙82A的第一部分82A1之间孔隙82A的第三部分82A3基本上垂直于孔隙82A的第二部分82A2。
在一些实施例中,孔隙82B的第三部分82B3位于孔隙82B的第一部分82B1之间孔隙82B的第三部分82B3基本上垂直于孔隙82B的第二部分82B2。
通过将第三部分82A3、82B3添加到各别孔隙82A、82B,天线8的带宽及增益与比较的贴片天线相比较可增加在一些实施例中,天线8的带宽为比较的贴片天线的带宽的约1.3倍大在一些实施例中,天线8可应用于图1A、2A、3A、4A及4B中所展示的半导体装置封装1、2、3、4中的任一者。
如本文中所使用,术语“基本上”、“基本”、“大约”及“约”被用于表示小变化举例来说,当结合数值使用时,所述术语可是指相对于所述数值小于或等于±10%的变化,例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%,或小于或等于±0.05%术语“基本上共面”可是指两个表面沿着同一平面放置在数微米内,例如沿着同一平面放置在100μm内、在80μm内、在60μm内、在40μm内、在30μm内、在20μm内、在10μm内、在1μm内如果两个表面或组件之间的角度为例如90°±10°,例如±5°、±4°、±3°、±2°、±1°、±0.5°、±0.1°或±0.05°,那么其可被认为“基本上垂直”在结合事件或情形使用时,术语“基本上”、“基本”、“大约”及“约”可是指其中确切地发生事件或情形的情况以及其中近似地发生事件或情形的情况。
另外,数量、比率及其它数值有时在本文中以范围格式呈现可理解,此些范围格式是出于便利及简洁起见而使用,且应灵活地理解为不仅包含明确规定为范围的限制的数值,而且还包含所述范围内囊括的所有个别数值或子范围,犹如每一数值及子范围是明确规定的
如本文中所使用,除非上下文另有明确指示,否则单数术语“一(a)”、“一(an)”和“所述”可包含复数对象。
在一些实施例的描述中,提供在另一组件“上”或“上方”的组件可囊括其中前一组件直接在后一组件上(例如,物理或直接接触)的状况,以及其中一或多个介入组件可位于前一组件与后一组件之间的状况在一些实施例的描述中,提供在另一组件“下方”或“之下”的组件可囊括其中前一组件直接在后一组件之下(例如,物理或直接接触)的状况,以及其中一或多个介入组件可位于前一组件与后一组件之间的状况。
如本文中所使用,术语“导电”、“导电”及“导电性”是指传输电流的能力导电材料通常指示几乎不展现对电流的流动的阻碍的那些材料导电性的一个度量为西门子/米(S/m)通常,导电材料为具有大于大约104S/m(例如至少105S/m或至少106S/m)的导电性的材料。材料的导电性可有时随温度变化除非另有规定,否则材料的导电性是在室温下进行测量。
虽然已参考本发明的特定实施例描述并说明本发明,但这些描述及说明并不限制本发明所属领域技术者可清楚地理解,在不脱离如随附权利要求书所界定的本发明的真实精神及范围的情况下,在实施例内可做出各种改变且可替代等效元件说明可不必按比例绘制由于制造程序中的变数等等,因此本发明中的精巧呈现与实际设备之间可存在差异可存在本发明的未具体说明的其它实施例说明书及图式应视为说明性而非限制性可进行修改以使特定情况、材料、物质组合物、方法或过程适应本发明的目的、精神及范围所有此些修改意欲属于随附权利要求书的范围内虽然已参考以特定次序执行的特定操作来描述本文中所揭示的方法,但可理解,可在不背离本发明的教示的情况下将这些操作组合、细分或重新排序以形成等效方法因此,除非本文中特别指明,否则操作的次序及分组并非对本发明的限制。
Claims (20)
1.一种半导体装置封装,其包括:
载体,其包括顶表面;
电组件,其安置在所述载体的所述顶表面上方;
天线,其安置在所述载体的所述顶表面上方且与所述电组件间隔开;
导电垫,其安置在所述载体的所述顶表面上方且在所述天线下方,其中所述导电垫包括共振结构;及
导电线,其电连接到所述电组件且在所述载体内延伸,
其中所述导电线的一部分位于所述天线及所述导电垫的所述共振结构下方且通过所述共振结构与所述天线电磁耦合。
2.根据权利要求1所述的半导体装置封装,其中所述天线包括第一导电层、第二导电层、安置在所述第一导电层与所述第二导电层之间的介电层及安置在所述介电层上且电连接到所述载体的所述顶表面的多个电连接件。
3.根据权利要求2所述的半导体装置封装,其中所述介电层的厚度为约80微米(μm)。
4.根据权利要求2所述的半导体装置封装,其中所述第一导电层及所述第二导电层包括镍Ni、铂Pt、金Au或其组合。
5.根据权利要求2所述的半导体装置封装,其中每一电连接件包含在从约250μm到约400μm的范围内的直径。
6.根据权利要求1所述的半导体装置封装,其中所述共振结构在所述导电垫中界定孔隙。
7.根据权利要求6所述的半导体装置封装,其中所述导电线延伸使得所述导电线的一部分在所述导电垫的所述孔隙下方。
8.根据权利要求2所述的半导体装置封装,其中所述天线与所述导电垫分离由所述电连接件界定的距离。
9.根据权利要求1所述的半导体装置封装,其中所述载体的所述顶表面与所述导电线分离一距离。
10.根据权利要求1所述的半导体装置封装,其中所述载体包括在从约2到约4的范围内的介电常数。
11.根据权利要求1所述的半导体装置封装,其中所述天线为路径天线。
12.一种半导体装置封装,其包括:
载体,其包括顶表面及导电线;
电组件,其安置在所述载体的所述顶表面上方;
天线,其安置在所述载体的所述顶表面上方且与所述电组件间隔开;
导电垫,其安置在所述载体的所述顶表面上方且在所述天线下方,其中所述导电垫包括共振结构;及
导电线,其电连接到所述电组件且经由所述导电垫的所述共振结构电磁耦合到所述天线。
13.根据权利要求12所述的半导体装置封装,其中所述天线包括第一导电层、第二导电层、安置在所述第一导电层与所述第二导电层之间的介电层及安置在所述介电层上且电连接到所述载体的所述顶表面的多个电连接件。
14.根据权利要求13所述的半导体装置封装,其中所述天线与所述导电垫间隔由所述电连接件界定的距离。
15.根据权利要求12所述的半导体装置封装,其中所述天线经配置以发射或接收电磁波,所述电磁波包括在从约56千兆赫(GHz)到约64GHz的范围内的频率。
16.根据权利要求12所述的半导体装置封装,其中所述天线的带宽大于约7GHz。
17.根据权利要求12所述的半导体装置封装,其中所述天线的增益大于约10分贝(dB)。
18.根据权利要求12所述的半导体装置封装,其中所述共振结构在所述导电垫中界定孔隙且所述导电线的一部分位于所述天线及所述导电垫的所述孔隙下方。
19.根据权利要求12所述的半导体装置封装,其中所述天线与所述导电垫之间的介质的介电常数为约1,其中所述介质为空气。
20.根据权利要求12所述的半导体装置封装,其中所述共振结构沿基本上垂直于所述导电线延伸的方向的方向延伸。
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KR102450576B1 (ko) * | 2016-01-22 | 2022-10-07 | 삼성전자주식회사 | 전자 부품 패키지 및 그 제조방법 |
US10276404B2 (en) * | 2017-08-30 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package |
US11380616B2 (en) * | 2018-05-16 | 2022-07-05 | Intel IP Corporation | Fan out package-on-package with adhesive die attach |
JP7064600B2 (ja) * | 2018-08-24 | 2022-05-10 | 京セラ株式会社 | 構造体、アンテナ、無線通信モジュール、および無線通信機器 |
CN114639945A (zh) | 2018-10-26 | 2022-06-17 | 华为技术有限公司 | 一种高带宽的封装天线装置 |
CN112038779B (zh) * | 2020-09-08 | 2023-05-16 | 日月光半导体制造股份有限公司 | 天线半导体封装装置及其制造方法 |
US11735830B2 (en) * | 2021-08-06 | 2023-08-22 | Advanced Semiconductor Engineering, Inc. | Antenna device and method for manufacturing the same |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6818985B1 (en) * | 2001-12-22 | 2004-11-16 | Skyworks Solutions, Inc. | Embedded antenna and semiconductor die on a substrate in a laminate package |
CN101431181A (zh) * | 2007-11-09 | 2009-05-13 | 富士康(昆山)电脑接插件有限公司 | 多频天线 |
CN103247581A (zh) * | 2012-02-14 | 2013-08-14 | 国际商业机器公司 | 芯片封装和装置 |
US8624381B2 (en) * | 2009-01-30 | 2014-01-07 | Infineon Technologies Ag | Integrated antennas in wafer level package |
US8718550B2 (en) * | 2011-09-28 | 2014-05-06 | Broadcom Corporation | Interposer package structure for wireless communication element, thermal enhancement, and EMI shielding |
CN104025126A (zh) * | 2011-09-30 | 2014-09-03 | 日立化成株式会社 | Rfid标签 |
CN105895626A (zh) * | 2015-02-18 | 2016-08-24 | 日月光半导体制造股份有限公司 | 半导体装置封装及其制作方法 |
CN106098658A (zh) * | 2015-04-29 | 2016-11-09 | 日月光半导体制造股份有限公司 | 半导体装置封装及其制造方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3472430B2 (ja) * | 1997-03-21 | 2003-12-02 | シャープ株式会社 | アンテナ一体化高周波回路 |
EP1126522A1 (en) | 2000-02-18 | 2001-08-22 | Alcatel | Packaged integrated circuit with radio frequency antenna |
JP2002299947A (ja) * | 2001-03-30 | 2002-10-11 | Fujitsu Quantum Devices Ltd | 高周波半導体装置 |
US7230316B2 (en) * | 2002-12-27 | 2007-06-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having transferred integrated circuit |
DE102006023123B4 (de) * | 2005-06-01 | 2011-01-13 | Infineon Technologies Ag | Abstandserfassungsradar für Fahrzeuge mit einem Halbleitermodul mit Komponenten für Höchstfrequenztechnik in Kunststoffgehäuse und Verfahren zur Herstellung eines Halbleitermoduls mit Komponenten für ein Abstandserfassungsradar für Fahrzeuge in einem Kunststoffgehäuse |
JP4725582B2 (ja) | 2005-10-27 | 2011-07-13 | 株式会社村田製作所 | 高周波モジュール |
CN104540317B (zh) * | 2007-07-17 | 2018-11-02 | 株式会社村田制作所 | 印制布线基板 |
US7830311B2 (en) * | 2007-07-18 | 2010-11-09 | Murata Manufacturing Co., Ltd. | Wireless IC device and electronic device |
EP2863480B1 (en) * | 2010-09-07 | 2018-11-07 | Murata Manufacturing Co., Ltd. | Communication terminal apparatus comprising an antenna device |
JP5545371B2 (ja) * | 2010-09-14 | 2014-07-09 | 株式会社村田製作所 | リーダライタ用アンテナモジュールおよびアンテナ装置 |
US9721920B2 (en) * | 2012-10-19 | 2017-08-01 | Infineon Technologies Ag | Embedded chip packages and methods for manufacturing an embedded chip package |
US8866292B2 (en) * | 2012-10-19 | 2014-10-21 | Infineon Technologies Ag | Semiconductor packages with integrated antenna and methods of forming thereof |
JP6027905B2 (ja) * | 2013-01-31 | 2016-11-16 | 新光電気工業株式会社 | 半導体装置 |
JP2015198197A (ja) * | 2014-04-02 | 2015-11-09 | パナソニックIpマネジメント株式会社 | 無線モジュール及び無線モジュールの製造方法 |
US9620464B2 (en) * | 2014-08-13 | 2017-04-11 | International Business Machines Corporation | Wireless communications package with integrated antennas and air cavity |
KR101643926B1 (ko) * | 2015-02-05 | 2016-07-29 | (주)파트론 | 안테나 구조물 |
CN110611160B (zh) * | 2016-01-30 | 2021-08-03 | 华为技术有限公司 | 一种贴片天线单元及天线 |
-
2016
- 2016-11-10 US US15/348,854 patent/US10186779B2/en active Active
-
2017
- 2017-10-18 CN CN201710998266.3A patent/CN108074886B/zh active Active
- 2017-10-18 CN CN202010456443.7A patent/CN111599771A/zh active Pending
- 2017-10-20 TW TW106136094A patent/TWI659516B/zh active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6818985B1 (en) * | 2001-12-22 | 2004-11-16 | Skyworks Solutions, Inc. | Embedded antenna and semiconductor die on a substrate in a laminate package |
CN101431181A (zh) * | 2007-11-09 | 2009-05-13 | 富士康(昆山)电脑接插件有限公司 | 多频天线 |
US8624381B2 (en) * | 2009-01-30 | 2014-01-07 | Infineon Technologies Ag | Integrated antennas in wafer level package |
US8718550B2 (en) * | 2011-09-28 | 2014-05-06 | Broadcom Corporation | Interposer package structure for wireless communication element, thermal enhancement, and EMI shielding |
CN104025126A (zh) * | 2011-09-30 | 2014-09-03 | 日立化成株式会社 | Rfid标签 |
CN103247581A (zh) * | 2012-02-14 | 2013-08-14 | 国际商业机器公司 | 芯片封装和装置 |
CN105895626A (zh) * | 2015-02-18 | 2016-08-24 | 日月光半导体制造股份有限公司 | 半导体装置封装及其制作方法 |
CN106098658A (zh) * | 2015-04-29 | 2016-11-09 | 日月光半导体制造股份有限公司 | 半导体装置封装及其制造方法 |
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CN108074886A (zh) | 2018-05-25 |
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