US20170053897A1 - Independent 3d stacking - Google Patents
Independent 3d stacking Download PDFInfo
- Publication number
- US20170053897A1 US20170053897A1 US14/935,310 US201514935310A US2017053897A1 US 20170053897 A1 US20170053897 A1 US 20170053897A1 US 201514935310 A US201514935310 A US 201514935310A US 2017053897 A1 US2017053897 A1 US 2017053897A1
- Authority
- US
- United States
- Prior art keywords
- level
- package
- die
- rdl
- level die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 150000001875 compounds Chemical class 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 19
- 235000012431 wafers Nutrition 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 239000011295 pitch Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000000638 solvent extraction Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/0805—Shape
- H01L2224/08057—Shape in side view
- H01L2224/08058—Shape in side view being non uniform along the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08147—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area disposed in a recess of the surface of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8034—Bonding interfaces of the bonding area
- H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/186—Material
Definitions
- a method of forming a package includes forming a first package level on a carrier substrate, the first package level including a first level die encapsulated in a gap fill oxide layer, and a plurality of though oxide vias (TOVs).
- the TOVs may have a height of about 20 microns or less.
- a second level die is hybrid bonded to the first package level with direct bonded oxide-oxide surfaces and metal-metal surfaces. The second level die is encapsulated on a back side of the first package level.
- the carrier substrate is removed, and a RDL is formed on a front side of the first package level.
- the method of forming the package additionally includes attaching the first level die to the carrier substrate, depositing the gap fill oxide layer over the first level die, planarizing the gap fill oxide layer, and forming the plurality of TOVs in the gap fill oxide layer.
- the first level die is ground to reduce a thickness of the first level die after attaching the first level die to the carrier substrate and prior to depositing the gap fill oxide layer over the first level die.
- a first level RDL is formed on the planarized gap fill oxide layer and first level die, and the first level RDL is planarized, and the second level die is hybrid bonded to the planarized first level RDL.
- FIG. 6 is a cross-sectional side view illustration of a planarized gap fill oxide layer including through oxide vias in accordance with an embodiment.
- FIG. 12 is a cross-sectional side view illustration of package including a thinned second package level in accordance with an embodiment.
- FIG. 17E is a cross-sectional side view illustration of a package with more than two package levels in accordance with an embodiment.
- TSVs and/or TOVs, and hybrid bonding allows for significant flexibility in heterogeneous die integration.
- this may allow for a greater degree of freedom in location of the active devices, as well as location and density of the TSVs to provide a shorter and more direct routing to the stacked second level die.
- the stacked second level die can have relatively straight routing to the bottom landing pad or conductive bump of the package, where the power plane is, for example on a circuit board.
- gap fill oxide layer 130 may then be formed over the thinned first level die 110 .
- gap fill oxide layer 130 is deposited using a suitable technique such as chemical vapor deposition (CVD), though other techniques may be used. Due to the reduced thickness of the first level die 110 , a quality gap fill oxide layer 130 can be deposited using CVD, which may aid in hybrid bonding.
- CVD chemical vapor deposition
- a first level RDL 160 may be optionally formed over the gap fill oxide layer 130 and thinned first level die 110 as illustrated in FIG. 7 .
- the first level RDL may be formed on an in electrical contact with the plurality of TOVs 134 and/or TSVs 120 .
- the first level RDL 160 may include one or more metal redistribution lines 162 (e.g. copper) and insulating layers 164 .
- one or more insulating layers 164 are formed of an oxide (e.g. SiO 2 ) for subsequent hybrid bonding.
- the gap fill oxide layer 130 , TOVs 134 , first level die 110 , and optional first level RDL 160 form the first package level 150 .
- a back side 165 of the first package level 150 (e.g. the first level RDL 160 ) may be planarized using a suitable technique such as CMP to form a planar surface for hybrid bonding.
- FIG. 13 is a schematic bottom view illustration of a package 100 in accordance with embodiments illustrating a variety of TOV 134 and optionally TSV 120 connections from the first package level 150 including the first level die 110 to the second package level 250 including the second level die 210 .
- FIG. 13 also illustrates freedom of die size (x, y dimensions) and location (x, y placement) within package levels that may be possible with embodiments.
- heterogeneous die may be integrated into multiple package levels without one package level having to be larger than another package level. Thus, specific die need not be packaged into a primary carrier package level. Furthermore, short communication paths between package levels are achievable.
- the second-first level die 110 B and the third-first level die 110 C are laterally adjacent to opposite sides of the first level die 110 A.
- the first level die 110 A is rectangular, though other shapes are possible in accordance with embodiments.
- the first and second rows 136 A, 136 B of TOVs 134 are laterally adjacent (and parallel) to a first pair of laterally opposite sides 105 A, 105 B of the first level die 110 A.
- the second-first level die 110 B and the third-first level die 110 C are laterally adjacent (and parallel to) to a second pair of laterally opposite sides 108 A, 108 B of the first level active die 110 A, respectively.
- a first row 136 A of TOVs 134 and a second row 136 B of TOVs 134 protrude from the back side 315 of the RDL 300 , and the first level die 110 A is located laterally between the first and second rows 136 A, 136 B of TOVs 134 .
- the RDL 300 may be formed on an in electrical contact with front sides 111 of the first level die 110 A, 110 B, 110 C and the first and second rows 136 A, 136 B of TOVs.
- a plurality of second level die 210 A, 210 B are hybrid bonded to a back side 165 of the first package level 150 with direct bonded oxide-oxide surfaces and direct bonded metal-metal surfaces.
- the first package level 150 may additionally include a first package level RDL 160 on a back side 115 of the first level die 110 A and the gap fill oxide layer 130 .
- first level die 110 A, second-first level die 110 B, and/or third-first level die 110 C may include TSVs 120 as previously described.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
- This application claims the benefit of priority from U.S. Provisional Application No. 62/208,544, filed on Aug. 21, 2015, which is herein incorporated by reference.
- Field
- Embodiments described herein relate to semiconductor packaging. More particularly, embodiments relate to packages including 3D stacked die.
- Background Information
- The current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces. Additionally, while the form factor (e.g. thickness) and footprint (e.g. area) for semiconductor die packaging is decreasing, the number of input/output (I/O) pads is increasing.
- Various multiple-die packaging solutions such as system in package (SiP) and package on package (PoP) have become more popular to meet the demand for higher die/component density devices. In an SiP a number of different die are enclosed within the package as a single module. Thus, the SiP may perform all or most of the functions of an electronic system.
- A 3D stacking implementation such as chip on wafer (CoW) includes mounting of die onto a support wafer, followed by singulation of stacked die SiPs. A 3D stacking implementation such as wafer to wafer (W2 W) includes mounting of a top wafer onto a bottom wafer, followed by singulation of stacked die SiPs. Both of the conventional 3D stacking implementations require that one of the package level tiers (e.g. mounted die, or die within wafer) to be bigger or equal to the other tier. For example, CoW may involve the singulated area of the support wafer being bigger than the die mounted on the support wafer, while W2 W may involve equal areas of the singulated wafers.
- Embodiments describe semiconductor die packages. In one embodiment, a package includes a first level redistribution layer (RDL), and a front side of a first package level on the RDL. The first package level includes one or more first level die encapsulated within a gap fill oxide layer on the RDL. A plurality of through oxide vias (TOVs) extend through the gap fill oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less. A second level die is included in a second package level, and the second level die is hybrid bonded to a back side of the first package level, with the hybrid bond including direct bonded oxide-oxide surfaces and direct bonded metal-metal surfaces. The second level die may be encapsulated in molding compound, for example, on the first package level. In an embodiment, the RDL is formed on an in electrical contact with a front side of the first level die and the plurality of TOVs.
- In an embodiment, the first package level includes a first package level RDL on a back side of the first level die and the gap fill oxide layer. The second level die may be hybrid bonded to a planarized back surface of the first package level RDL. For example, the first package level RDL may include an oxide dielectric layer and metal redistribution line, and the second level die is hybrid bonded to the oxide dielectric layer and the metal redistribution line. The first level die may include a plurality of through silicon vias (TSVs), with the first package level RDL formed on an in electrical contact with the plurality of TSVs.
- In accordance with some embodiments, the TOVs may be arranged in rows. For example, the plurality of TOVs may include a first row of TOVs and a second row of TOVs. In a particular arrangement, the first and second rows of TOVs are laterally adjacent to a first pair of laterally opposite sides of the first level die. A second-first level die and a third-first level die can be located laterally adjacent to a second pair of laterally opposite sides of the first level die. In such an arrangement, the RDL may be formed on an in electrical contact with a front side of the first level die, a front side of the second-first level die, a front side of the third-first level die, the first row of TOVs, and the second row of TOVs. The first level die may additionally include a plurality of TSVs, for example, with a maximum width of about 10 microns or less.
- In an embodiment, a package includes an RDL, and a front side of a first package level on a back side of the RDL. A first level die is encapsulated in a gap fill oxide layer on the back side of the RDL. A first row of TOVs and a second row of TOVs protrude from the back side of the RDL, and the first level die is located laterally between the first and second rows of TOVs. A plurality of second level die are hybrid bonded to a back side of the first package level with direct bonded oxide-oxide surfaces and direct bonded metal-metal surfaces.
- The first package level may additionally include a first package level RDL on a back side of the first level die and the gap fill oxide layer. For example, the first package level RDL may include an oxide dielectric layer and a metal redistribution line, and the second level die is hybrid bonded to the oxide dielectric layer and the metal redistribution line.
- The first package level may additionally include a second-first level die and a third-first level die laterally adjacent to opposite sides of the first level die. The first level die, second-first level die, and third-first level die may all be on an in electrical contact with the RDL. In an embodiment, the first level die is rectangular, the first and second rows of TOVs are laterally adjacent to a first pair of laterally opposite sides of the first level die, and the second-first level die and the third-first level die are laterally adjacent to a second pair of laterally opposite sides of the first level die. In accordance with embodiments, the first level die, the first row of TOVs, and the second row of TOVs may all have a height of 20 microns or less. In accordance with embodiments, a plurality of TSVs may be within the first level die, with each TSV having a maximum width of 10 microns or less.
- In an embodiment, a method of forming a package includes forming a first package level on a carrier substrate, the first package level including a first level die encapsulated in a gap fill oxide layer, and a plurality of though oxide vias (TOVs). The TOVs may have a height of about 20 microns or less. A second level die is hybrid bonded to the first package level with direct bonded oxide-oxide surfaces and metal-metal surfaces. The second level die is encapsulated on a back side of the first package level. The carrier substrate is removed, and a RDL is formed on a front side of the first package level.
- In an embodiment, the method of forming the package additionally includes attaching the first level die to the carrier substrate, depositing the gap fill oxide layer over the first level die, planarizing the gap fill oxide layer, and forming the plurality of TOVs in the gap fill oxide layer. In an embodiment, the first level die is ground to reduce a thickness of the first level die after attaching the first level die to the carrier substrate and prior to depositing the gap fill oxide layer over the first level die. In an embodiment, a first level RDL is formed on the planarized gap fill oxide layer and first level die, and the first level RDL is planarized, and the second level die is hybrid bonded to the planarized first level RDL.
-
FIG. 1 is a flow chart illustrating a method of forming a package in accordance with an embodiment. -
FIG. 2 is a schematic cross-sectional side view illustration of a first level die including blind vias in accordance with an embodiment. -
FIG. 3 is a cross-sectional side view illustration of first level die attached to a carrier substrate in accordance with an embodiment. -
FIG. 4 is a cross-sectional side view illustration of thinned first level die in accordance with an embodiment. -
FIG. 5 is a cross-sectional side view illustration of a gap fill oxide layer formed over thinned first level die in accordance with an embodiment. -
FIG. 6 is a cross-sectional side view illustration of a planarized gap fill oxide layer including through oxide vias in accordance with an embodiment. -
FIG. 7 is a cross-sectional side view illustration of a first level redistribution layer formed over a planarized gap fill oxide layer including through oxide vias in accordance with an embodiment. -
FIG. 8 is a cross-sectional side view illustration of a first package level including a planarized first level redistribution layer in accordance with an embodiment. -
FIG. 9 is a cross-sectional side view illustration including a close-up view of second level die hybrid bonded to a first package level in accordance with an embodiment. -
FIG. 10 is a cross-sectional side view illustration of encapsulated second level die on a first package level in accordance with an embodiment. -
FIG. 11 is a cross-sectional side view illustration of package including hybrid bonded second level die in accordance with an embodiment. -
FIG. 12 is a cross-sectional side view illustration of package including a thinned second package level in accordance with an embodiment. -
FIG. 13 is a schematic bottom view illustration of a package including stacked die, through oxide vias, and through silicon vias in accordance with an embodiment. -
FIG. 14 is a flow chart illustrating a method of forming a package in accordance with an embodiment. -
FIGS. 15A-15D are cross-sectional side view illustrations of a method of forming a package with more than two package levels in accordance with an embodiment. -
FIG. 16 is a flow chart illustrating a method of forming a package in accordance with an embodiment. -
FIGS. 17A-17D are cross-sectional side view illustrations of a method of forming a package in accordance with an embodiment. -
FIG. 17E is a cross-sectional side view illustration of a package with more than two package levels in accordance with an embodiment. -
FIG. 18 a schematic bottom view illustration of a die stack arrangement and a close-up perspective view of a row of through oxide vias in accordance with an embodiment. -
FIG. 19A is a cross-sectional side view illustration of a package taken along line A-A inFIG. 18 in accordance with an embodiment. -
FIG. 19B is a cross-sectional side view illustration of a package taken along line B-B inFIG. 18 in accordance with an embodiment. - Embodiments describe semiconductor packages and packaging processes of heterogeneous stacked die. In accordance with embodiments, flexibility in heterogeneous die integration may be achieved independent of die area or thickness, in any package level. In this aspect, system on chip (SoC) die partitioning within an SiP structure may be possible in which intellectual property (IP) cores are freely segregated throughout the package.
- In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the embodiments. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.
- The terms “top”, “bottom”, “front”, “back”, “over”, “to”, “between”, and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over”, or “on” another layer or bonded “to” or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
- In one embodiment, a package includes a first package level including one or more first level die encapsulated within a gap fill oxide layer and a first level RDL spanning across the one or more first level die and the gap fill oxide layer. A planarized front surface of a second level die is hybrid bonded to a planarized surface of the first level RDL, which may include coplanar metal and oxide surfaces. In accordance with embodiments, the hybrid bonds include oxide-oxide bonds and metal-metal bonds between the second level die and the first level RDL. In this aspect, significant package z-height savings may be realized by eliminating interface materials for bonding. Furthermore, hybrid bonding may allow for a high connection density.
- In accordance with embodiments, through silicon vias (TSVs) may optionally be formed through the one or more first level die and through oxide vias (TOVs) may be formed through the gap fill oxide layer encapsulating the one or more first level die within the first package level. In accordance with embodiments, a thickness of the first level die, gap fill oxide layer, and TOVs may be reduced to about 20 μm or less, such as 2 μm-20 μm, or 5 μm-10 μm. In this manner, not only is z-height savings realized, it is possible to form narrow TSVs and TOVs without height being a practical limiting factor to minimum width of the TSVs and TOVs. In this aspect, direct and short communication paths to the second level die within the second level package are possible, at virtually any place through the first package level. This may additionally allow for minimal routing penalties due to routing length lengths, and full access for die in any package level to power distribution. In accordance with embodiments, the combination of TSVs and/or TOVs, and hybrid bonding allows for significant flexibility in heterogeneous die integration.
- In one aspect, embodiments describe system on chip (SoC) die partitioning and/or die splitting within an SiP structure (e.g. 3D memory package) in which IP cores such as CPU, GPU, IO, DRAM, SRAM, cache, ESD, power management, and integrated passives may be freely segregated throughout the package, while also mitigating total z-height of the package. Different IP cores can be segregated into different die within the package. Additionally, die partitioning may allow the integration of different process nodes into separate die. Likewise different IP cores in different die can be processed at different process nodes. By way of example, central processing unit (CPU) and general processing unit (GPU) can be separate die processed at different process nodes. Flexibility in die partitioning may be facilitated by the ability to access the power supply line anywhere. Flexibility in die partitioning may also mitigate thermal constraints across the system.
- In an embodiment, the first level die is an active die that includes active IP cores that benefit from relieved routing densities and short routing paths, such as a central processing unit/general processing unit (CPU/GPU) die. In an embodiment, the package is a 3D memory package, such as a wide I/O DRAM package. In an embodiment, the one or more second level die are memory die, such as, but not limited to, DRAM. In an embodiment, the additional first level die, such as the second-first level die and the third-first level die are a partitioned IP core, such as, but not limited to, split I/O die.
- In accordance with embodiments, a thickness or height of the first level die and TOVs is about 20 μm or less, such as 5 to 10 μm. In this manner, not only is z-height savings realized, it is possible to form narrow TOVs. In an embodiment, an exemplary TOV is about 10 μm wide, though narrower or wider TOVs may be formed, for example, easily within a 10:1 (height:diameter) aspect ratio. In an embodiment, an exemplary TOV is about 2 μm wide. In this aspect, the reduced thickness of the first level die allows for the formation of TOVs with substantially less width (or diameter) compared to common TSVs such as those in a traditional interposer.
- In accordance with embodiments, TOVs and optionally TSVs may be used to provide short vertical communication paths between the package levels. In accordance with embodiments TOVs may also be arranged in rows to provide short routing paths from the second level die to edges (e.g. each edge) of a first level die (e.g. active die), which can also allow for high routing densities with mitigated routing jam. In an exemplary embodiment, the pitch between TOVs in a row of TOVs may have a gap ratio of TOV to oxide between TOVs of 1:1. By way of example, exemplary 10 μm wide TOVs have a pitch of 20 μm (in x and/or y dimensions). This may correspond to a density of 50×50 per mm2 (or 2,500 per mm2). Embodiments are not limited to these exemplary gap ratios, TOV pitches, and TOV densities. For example, the amount of oxide between TOVs can be increased above the 1:1 gap ratio. Larger pitches, such as 40 μm-70 μm may also be implemented. Additionally, narrower TOVs may be fabricated. In another exemplary embodiment, TOVs are 2 μm wide. Assuming a 1:1 gap ratio, this may correspond to a pitch of 4 μm, and a density of 250×250 per mm2 (or 62,500 per mm2).
- In one aspect, embodiments describe an embedded TSV first level die configuration that may have a comparatively low keep out zone (KOZ). It has been observed that TSVs, such as copper TSVs through a silicon die, can create stress in the surrounding die area. As a result, active devices are arranged outside of a lateral KOZ around a TSV to mitigate TSV-induced stress on the active devices, such as affecting carrier mobility in the active devices. In accordance with embodiments, the reduced thickness of the embedded first level (e.g. active) die can allow the formation of TSVs with a substantially less width (or diameter) compared to common TSVs such as those in a traditional interposer. In some embodiments, aspect ratios of at most 10:1 first level die thickness:TSV maximum width are well within processing parameters. For example, TSVs having a maximum width (or diameter) of 2-10 μm, or less are possible. An exemplary list of TSV dimensions and aspect ratios is provided in Table 1 for illustrative purposes.
-
TABLE 1 TSV dimensions and aspect ratios First level die thickness (μm) TSV width (μm) TSV aspect ratio 20 2 10:1 20 10 2:1 5 2 5:1 - A reduced TSV height may allow for reduced TSV maximum width (or diameter), as well as increased TSV density and a smaller KOZ. In some embodiments, a TSV density of 250×250 per mm2 (e.g. 62,500 per mm2) is possible, which may be greater than that achievable with traditional interposers at approximately 10×10 per mm2 (or 100 per mm2). In some embodiments, a KOZ of less than approximately 5 μm is possible. In an embodiment, a TSV through the first level die is within 5 μm of an active device (e.g. transistor) in the first level die. In one aspect, this may allow for a greater degree of freedom in location of the active devices, as well as location and density of the TSVs to provide a shorter and more direct routing to the stacked second level die. In accordance with embodiments the stacked second level die can have relatively straight routing to the bottom landing pad or conductive bump of the package, where the power plane is, for example on a circuit board.
- Referring now
FIG. 1 a flow chart is provided illustrating a method of forming a package in accordance with an embodiment. In interest of clarity, the following description ofFIG. 1 is made with regard to reference features found in other figures described herein. At operation a 1010 afirst package level 150 is formed on acarrier substrate first package level 150 may include a first level die 110 encapsulated in a gapfill oxide layer 130, and a plurality of though oxide vias (TOVs) 134. In an embodiment theTOVs 134 have a height of about 20 μm or less. A second level die 210 is then hybrid bonded to thefirst package level 150 atoperation 1012 to form direct bonded oxide-oxide surfaces (e.g. forlayers 164, 264) and metal-metal surfaces (e.g. forlayers 162, 262), (seeFIG. 9 ). Atoperation 1014 the second level die 210 is encapsulated on aback side 165 of thefirst package level 150, followed by removal of thecarrier substrate operation 1016. AnRDL 300 may then be formed on afront side 170 of thefirst package level 150 atoperation 1018. - In accordance with embodiments, the one or more first level die 110 may be active die, though this is not required. In other embodiments, the first level die 110 may be replaced with silicon interposers, or silicon integrated passive devices (IPDs). Referring now to
FIG. 2 a schematic cross-sectional side view is provided of a first level die 110 includingblind vias 119 in accordance with an embodiment. In accordance with embodiments, the first level die 110 may be an active die such as a logic die or SOC die including an active component(s) such as, but not limited to, a microprocessor, memory, RF transceiver, and mixed-signal component. In the particular embodiment illustrated, an active device 121 (e.g. transistor) of an active component is shown by way of example. As shown, theactive devices 121 may be formed on asubstrate 117 such as a silicon substrate or silicon on insulator (SOI) substrate. In an embodiment, theactive devices 121 are formed in a topepitaxial silicon layer 116, formed over abase silicon substrate 114. In an embodiment, the KOZ is less than 5 μm, and a blind via 119 is formed within 5 μm (laterally) of anactive device 121. One ormore interconnect layers 118 may be formed for routing purposes to connect theactive devices 121 andblind vias 119 to landing pads 128 (including both 128A, 128B on the front side 111) of the first level die 110. The interconnect layers 118 may include one ormore metal layers 126 and/ordielectric layers 124. In the embodiment illustrated, the blind vias 119 (which will become TSVs 120) are interspersed between theactive devices 121 in the first level die 110. - The metal layer(s) 126 may provide lateral interconnect paths, with
vias 127 providing vertical connections. In accordance with embodiments, thefront side 111 of the first level die 110 may include insulating layer 122 (e.g. oxide, or polymer)landing pads 128B connected toblind vias 119, and/orlanding pads 128A connected to theactive devices 121 of the first level die 110. In the embodiment illustrated, theblind vias 119 are formed in the active layer (e.g. top epitaxial layer 116) of theactive devices 121. Theblind vias 119 may extend completely through the active layer (e.g. epitaxial layer 116) and optionally into thebase substrate 114. The depth of theblind vias 119 may be at least the depth of thefinal TSVs 120 to be formed. In an embodiment, theblind vias 119 may optionally extend at least partially through the interconnect layer(s) 118. For example,blind vias 119 may extend through theinterconnect layer 118 tolanding pads 128A, or to ametal layer 126 in an embodiment. In an embodiment,blind vias 119 may not contact a landing pad (e.g. 128A, 128B) on thefront side 111 and instead connect with anactive device 121 through one ormore metal layers 126 and vias 127 in theinterconnect layer 118. In this manner, theTSVs 120 to be formed can connect directly to theactive devices 121 within the first level die 110. - Referring now to
FIG. 3 , one or more first level die 110 are mounted on acarrier substrate 101 such as a glass panel, silicon wafer, metal panel, etc. Thecarrier substrate 101 may include arelease layer 102 for mounting the first level die. In an embodiment, therelease layer 102 is an oxide layer and the first level die 110 are mounted on thecarrier substrate 101 with oxide-oxide bonds (e.g. bonding with oxide insulating layer 122). In an embodiment, therelease layer 102 is an adhesive (e.g. polymer) or tape layer for mounting the first level die 110. As shown, the first level die 110 are mounted onto thecarrier substrate 101 face down, such that thefront sides 111 including the insulatinglayer 122 and landing pads 128 (128A, 128B) is face down. As shown, the one or morefirst level 110 may be different die, including different components, with different thicknesses and areas. One or more of the first level die 110 may be active die.Blind vias 119 are optionally formed within one or more of the first level die 110, though this is not required. - The one or more first level die 110 may then be ground using a suitable technique such as chemical mechanical polishing (CMP) to reduce a thickness of the first level die 110, as shown in
FIG. 4 . In accordance with embodiments, the thinning of the first level die 110 may expose theblind vias 119, resulting in aback side 115 of the first level die 110 including exposedsurfaces 123 ofTSVs 120. In an embodiment, the first level die 110 are thinned to about 20 μm or less, such as 2 μm-20 μm, or 5 μm-10 μm. - Referring to the embodiment illustrated in
FIG. 5 , a gapfill oxide layer 130 may then be formed over the thinned first level die 110. In an embodiment, gapfill oxide layer 130 is deposited using a suitable technique such as chemical vapor deposition (CVD), though other techniques may be used. Due to the reduced thickness of the first level die 110, a quality gapfill oxide layer 130 can be deposited using CVD, which may aid in hybrid bonding. - Referring now to
FIG. 6 ,TOVs 134 may be formed through the gapfill oxide layer 130. For example, the gapfill oxide layer 130 may be planarized, patterned, andTOVs 134 formed within the planarized gapfill oxide layer 130.TSVs 120 may also be optionally formed. For example,TSVs 120 may be formed at this stage in embodiments in which blind vias 119 were not previously formed in the first level die 110. In an embodiment, the thinned first level die 110 do not includeTSVs 120. In the particular embodiment illustrated inFIG. 6 , theback surface 131 of the gapfill oxide layer 130 and backside 115 of the first level die 110 are planarized, exposingsurfaces 135 of theTOVs 134, and optionally surfaces 123 of theTSVs 120. - A
first level RDL 160 may be optionally formed over the gapfill oxide layer 130 and thinned first level die 110 as illustrated inFIG. 7 . The first level RDL may be formed on an in electrical contact with the plurality ofTOVs 134 and/orTSVs 120. As shown, thefirst level RDL 160 may include one or more metal redistribution lines 162 (e.g. copper) and insulatinglayers 164. In an embodiment, one or moreinsulating layers 164 are formed of an oxide (e.g. SiO2) for subsequent hybrid bonding. Together, the gapfill oxide layer 130,TOVs 134, first level die 110, and optionalfirst level RDL 160 form thefirst package level 150. As illustrated inFIG. 8 , aback side 165 of the first package level 150 (e.g. the first level RDL 160) may be planarized using a suitable technique such as CMP to form a planar surface for hybrid bonding. - One or more second level die 210 may then be hybrid bonded to the
first package level 150 as shown in the embodiment illustrated inFIG. 9 . In the particular embodiment illustrated, the second level die 210 are hybrid bonded face down, with the (e.g. planar)front sides 211 of the second level die 210 hybrid bonded to the back side 165 (e.g. planar back surface) of thefirst package level 150. More specifically, thefront surfaces 211 may be hybrid bonded to thefirst level RDL 160, when present. The close-up view of the hybrid bond inFIG. 9 shows direct bonded oxide-oxide surfaces of an insulating layer 164 (e.g. SiO2) of thefirst level RDL 160 with an insulating layer 264 (e.g. SiO2) of a build-upstructure 260 for the second level die 210, and direct bonded metal-metal surfaces of redistribution line 162 (e.g. copper) of thefirst level RDL 160 with a metal layer 262 (e.g. copper) of the build-upstructure 260 for the second level die 210. - The second level die 210 are then encapsulated in a second
level molding compound 240 on theback side 165 of thefirst package level 150. For example, the secondlevel molding compound 240 may include a thermosetting cross-linked resin (e.g. epoxy), though other materials may be used as known in electronic packaging. Encapsulation may be accomplished using a suitable technique such as, but not limited to, transfer molding, compression molding, and lamination. In the embodiment illustrated, the secondlevel molding compound 240 covers theback sides 215 of the second level die 210. A thicker secondlevel molding compound 240 may provide structural support during subsequent processing. - Referring now to
FIG. 11 , thecarrier substrate 101 is removed, and anRDL 300 may be formed on thefront side 170 of thefirst package level 150. Specifically,RDL 300 may be formed on the gapfill oxide layer 130 andfront sides 111 of the first level die 110. As shown,RDL 300 may also be formed on an in electrical contact with the plurality ofTOVs 134.RDL 300 may include asingle redistribution line 302 ormultiple redistribution lines 302 anddielectric layers 304.RDL 300 may be formed by a layer-by-layer process, and may be formed using thin film technology. In an embodiment, theRDL 300 has a total thickness of less than 50 μm, or more specifically less than 30 μm, such as approximately 20 μm. In an embodiment,RDL 300 includes embedded redistribution lines 302 (embedded traces). For example, theredistribution lines 302 may be created by first forming a seed layer, followed by forming a metal (e.g. copper) pattern. Alternatively,redistribution lines 302 may be formed by deposition (e.g. sputtering) and etching. The material ofredistribution lines 302 can include, but is not limited to, a metallic material such as copper, titanium, nickel, gold, and combinations or alloys thereof. The metal pattern of theredistribution lines 302 is then embedded in adielectric layer 304, which is optionally patterned. The dielectric layer(s) 304 may be any suitable material such as an oxide, or polymer (e.g. polyimide). Following formation of RDL 300 a plurality of conductive bumps 350 (e.g. solder bumps, or stud bumps) may be formed on afront side 311 of theRDL 300.Individual packages 100 may then be singulated from the reconstituted substrate. In some embodiments, a thickness of thesecond package level 250 including the secondlevel molding compound 240 and second level die 210 may be reduced using a suitable technique such as CMP prior to singulation. In the embodiment illustrated inFIG. 12 , the thickness of thesecond package level 250 may be reduced to expose theback side 215 of one or more second level die 210. -
FIG. 13 is a schematic bottom view illustration of apackage 100 in accordance with embodiments illustrating a variety ofTOV 134 and optionallyTSV 120 connections from thefirst package level 150 including the first level die 110 to thesecond package level 250 including the second level die 210.FIG. 13 also illustrates freedom of die size (x, y dimensions) and location (x, y placement) within package levels that may be possible with embodiments. In accordance with embodiments, heterogeneous die may be integrated into multiple package levels without one package level having to be larger than another package level. Thus, specific die need not be packaged into a primary carrier package level. Furthermore, short communication paths between package levels are achievable. In accordance with embodiments, vias (TOV or TSV) may be located at any location in the entire face of thefirst package level 150, which may allow for full access to power distribution for both the first level die 110 and second level die 210. In accordance with embodiments, short communication path lengths between first level die 110 and second level die 210 can additionally be provided where the die overlap. In one embodiment, a first level die 110 may be a bridging die, which includesTSVs 120 directly underneath and in communication with two separate second level die 210. -
FIG. 14 is a flow chart illustrating a method of forming a package in accordance with an embodiment, which may optionally include forming more than two package levels. In the following description ofFIG. 14 reference is made with regard to the features found in the cross-sectional side view illustrations provided inFIGS. 3-12 andFIGS. 15A-15D . Referring toFIG. 14 , at operation 1410 a first level die 110 is attached to acarrier substrate 101, similarly as previously described with regard toFIG. 3A . At operation 1412 a thickness of the first level die 110 is reduced, similarly as described with regard toFIG. 4 . At operation 1414, a gapfill oxide layer 130 is deposited over the thinned first level die 110, similarly as described with regard toFIG. 5 . Atoperation 1416, the gap fill oxide layer 130 (and optionally the first level die 110) is planarized, similarly as described with regard toFIG. 6 . Atoperation 1418,TOVs 134 are formed through the gapfill oxide layer 130, similarly as described with regard toFIG. 6 . Atoperation 1420, afirst level RDL 160 is formed over the gapfill oxide layer 130 and the first level die 110, similarly as described with regard toFIGS. 7-8 , resulting in the structure illustrated inFIG. 15B . - At operation 1422, a second level die 210, or optionally first level die 110, is hybrid bonded to the
first level RDL 160, similarly as described with regard toFIG. 9 , resulting in the structure illustrated inFIG. 15C . At this stage, operations 1412-1422 may be repeated one or more times to formadditional package levels operation 1424, the second level die 210 is encapsulated on a back side of the first package level, similarly as described with regard toFIG. 10 . Atoperation 1426, thecarrier substrate 101 is removed, and at operation 1428 an RDL is formed on a front side of the first package level, similarly as described with regard toFIG. 11 . A thickness of thesecond package level 250 may then be reduced similarly as described with regard toFIG. 12 . Referring toFIG. 15D a process flow is illustrated in which twopackage levels back side 165B of thefirst package level 150B, and theRDL 300 is formed on thefront side 170A of thefirst package level 150A. -
FIG. 16 is a flow chart illustrating a method of forming a package in accordance with an embodiment. In the following description ofFIG. 16 reference is made with regard to the features found in the cross-sectional side view illustrations provided inFIGS. 3-12 andFIGS. 17A-17E . Referring toFIG. 16 , at operation a 1610 a first level die 110 is attached to afirst carrier substrate 101 similarly as previously described with regard toFIG. 3 . At operation 1612 a thickness of the first level die 110 is reduced, similarly as described with regard toFIG. 4 . Atoperation 1614, a gapfill oxide layer 130 is deposited over the thinned first level die 110, similarly as described with regard toFIG. 5 . Atoperation 1618,TOVs 134 are formed through the gapfill oxide layer 130, similarly as described with regard toFIG. 6 , resulting in the structure illustrated inFIG. 17A . - At operation 1620 a
second carrier substrate 103 is attached to the thinned first level die 110 and gap filloxide layer 130. Thefirst carrier substrate 101 may then be removed atoperation 1622, and afirst level RDL 160 is formed over the gapfill oxide layer 130 and first level die 110 atoperation 1624, resulting in the structure illustrated inFIG. 17B . At this stage, thefront side 111 of the first level die 110 is facing up toward thefirst level RDL 160 in thefirst package level 150. - At operation 1626, a second level die 210 is hybrid bonded to the
first level RDL 160, similarly as described with regard toFIG. 9 , resulting in the structure illustrated inFIG. 17C . At this stage, operations 1412-1422 or 1612-1626 may be repeated one or more times to formadditional package levels operation 1628, the second level die 210 is encapsulated on a back side of the first package level, similarly as described with regard toFIG. 10 . Atoperation 1630, thesecond carrier substrate 103 is removed, and atoperation 1632 an RDL is formed on a front side of the first package level, similarly as described with regard toFIG. 11 . A thickness of thesecond package level 250 may then be reduced similarly as described with regard toFIG. 12 . Referring toFIG. 17D a process flow is illustrated in which onefirst package level 150 is formed, with thefront side 111 of the first level die 110 andfront side 211 of the second level die 210 facing toward one another. Referring toFIG. 17E a process flow is illustrated in which twofirst package levels back side 165B of thefirst package level 150B, and theRDL 300 is formed on thefront side 170A of thefirst package level 150A. In the embodiment illustrated inFIG. 17E ,front side 111 of the first level die 110A within thefirst package level 150A, andfront side 111 of the first level die 110B within thefirst package level 150B are facing toward one another. Alternatively, the orientation of either of the first level die 110A or 110B may be reversed. - Referring now to
FIG. 18 a schematic bottom view illustration of a die stack arrangement and close-up perspective view of a row of TOVs are provided in accordance with an embodiment.FIG. 19A is a cross-sectional side view illustration of a package taken along line A-A inFIG. 18 in accordance with an embodiment.FIG. 19B is a cross-sectional side view illustration of a package taken along line B-B inFIG. 18 in accordance with an embodiment. In the embodiments illustrated, apackage 100 includes a first level die 110A, a second-first level die 110B, and a third-first level die 110C, afirst row 136A ofTOVs 134, and asecond row 136B ofTOVs 134. The second-first level die 110B and the third-first level die 110C are laterally adjacent to opposite sides of thefirst level die 110A. Referring toFIG. 18 , the first level die 110A is rectangular, though other shapes are possible in accordance with embodiments. As shown, the first andsecond rows TOVs 134 are laterally adjacent (and parallel) to a first pair of laterallyopposite sides first level die 110A. As shown, the second-first level die 110B and the third-first level die 110C are laterally adjacent (and parallel to) to a second pair of laterallyopposite sides active die 110A, respectively. - Referring to
FIG. 18 andFIGS. 19A-19B , a first-second level die 210A and a second-second level die 210B are arranged side-by-side over the first level die. Thefirst row 136A ofTOVs 134 is located beneath the first-second level die 210A, and thesecond row 136B ofTOVs 134 is located beneath the second-second level die 210B. Therows TOVs 134 may be parallel to theadjacent edges 203 of the corresponding second level die 210A, 210B. In an embodiment, aback side 115 of the first level (e.g. active) die 210A is facing thefront sides 111 of the first-second level die 210A and the second-second level die 210B laterally between the first andsecond rows TOVs 134. In such a configuration, short electrical routing paths (illustrated by arrows inFIG. 18 ) to each different edge of the first levelactive die 110A can be achieved. For example, an RDL 300 (seeFIGS. 19A-19B , for example) may be formed on and in electrical contact with the first levelactive die 110A, the first andsecond rows TOVs 134, and the second-first level die 110B and the third-first level die 110C. - In an embodiment, a
package 100 includes anRDL 300, and afront side 170 of afirst package level 150 on aback side 315 of theRDL 300. A first level die 110A is encapsulated in a gapfill oxide layer 130 on theback side 315 of theRDL 300. Additionally, a second-first level die 110B and a third-first level die 110C may be located laterally adjacent to opposite sides of thefirst level die 110A. The first level die 110A, 110B, 110C may all be on an in electrical contact with theRDL 300. Afirst row 136A ofTOVs 134 and asecond row 136B ofTOVs 134 protrude from theback side 315 of theRDL 300, and the first level die 110A is located laterally between the first andsecond rows TOVs 134. In an embodiment, theRDL 300 may be formed on an in electrical contact withfront sides 111 of the first level die 110A, 110B, 110C and the first andsecond rows back side 165 of thefirst package level 150 with direct bonded oxide-oxide surfaces and direct bonded metal-metal surfaces. Thefirst package level 150 may additionally include a firstpackage level RDL 160 on aback side 115 of the first level die 110A and the gapfill oxide layer 130. - It is to be appreciated, that the particular arrangement of a pair of second level die 210A, 210B, and a pair of second-first level die 110B and third-
first level die 110C are exemplary. While the particular arrangement may be used to form short electrical routing paths to each side of the first level die 110A, other configurations are possible. Additionally, the first level die 110A, second-first level die 110B, and/or third-first level die 110C may include TSVs120 as previously described. - While several package variations are described and illustrated separately, many of the structural features and processing sequences may be combined in a single embodiment. In utilizing the various aspects of the embodiments, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming package including heterogeneous stacked die. Although the embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as embodiments of the claims useful for illustration.
Claims (20)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/935,310 US9559081B1 (en) | 2015-08-21 | 2015-11-06 | Independent 3D stacking |
CN201680043123.0A CN107851615B (en) | 2015-08-21 | 2016-06-15 | Independent 3D stacking |
KR1020187004420A KR102033865B1 (en) | 2015-08-21 | 2016-06-15 | Independent 3D Stacking |
PCT/US2016/037690 WO2017034654A1 (en) | 2015-08-21 | 2016-06-15 | Independent 3d stacking |
TW105121277A TWI621228B (en) | 2015-08-21 | 2016-07-05 | Semiconductor package and method for forming the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562208544P | 2015-08-21 | 2015-08-21 | |
US14/935,310 US9559081B1 (en) | 2015-08-21 | 2015-11-06 | Independent 3D stacking |
Publications (2)
Publication Number | Publication Date |
---|---|
US9559081B1 US9559081B1 (en) | 2017-01-31 |
US20170053897A1 true US20170053897A1 (en) | 2017-02-23 |
Family
ID=57867523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/935,310 Active US9559081B1 (en) | 2015-08-21 | 2015-11-06 | Independent 3D stacking |
Country Status (5)
Country | Link |
---|---|
US (1) | US9559081B1 (en) |
KR (1) | KR102033865B1 (en) |
CN (1) | CN107851615B (en) |
TW (1) | TWI621228B (en) |
WO (1) | WO2017034654A1 (en) |
Cited By (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180130745A1 (en) * | 2016-11-04 | 2018-05-10 | Phoenix Pioneer Technology Co., Ltd. | Package substrate and its fabrication method |
WO2019065668A1 (en) * | 2017-09-29 | 2019-04-04 | 株式会社村田製作所 | High frequency module and communication device |
WO2020046677A1 (en) * | 2018-08-31 | 2020-03-05 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
WO2020211272A1 (en) * | 2019-04-15 | 2020-10-22 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
KR20210012372A (en) * | 2019-07-25 | 2021-02-03 | 삼성전자주식회사 | Semiconductor package having stacked semiconductor chips |
DE102019129840A1 (en) * | 2019-10-18 | 2021-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | SEMICONDUCTOR COMPONENT AND METHOD FOR MANUFACTURING IT |
CN112701130A (en) * | 2019-10-22 | 2021-04-23 | 财团法人工业技术研究院 | Image sensor package and method of manufacturing the same |
TWI741837B (en) * | 2019-10-18 | 2021-10-01 | 台灣積體電路製造股份有限公司 | Integrated circuit package and method of forming the same |
US11158573B2 (en) | 2018-10-22 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Interconnect structures |
US11158604B2 (en) | 2019-04-15 | 2021-10-26 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
US11264314B2 (en) * | 2019-09-27 | 2022-03-01 | International Business Machines Corporation | Interconnection with side connection to substrate |
US11282761B2 (en) | 2018-11-29 | 2022-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of manufacturing the same |
TWI764852B (en) * | 2021-06-30 | 2022-05-11 | 聯發科技股份有限公司 | Semiconductor package structure |
US11367729B2 (en) | 2019-04-30 | 2022-06-21 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and NAND flash memory and methods for forming the same |
TWI770609B (en) * | 2020-05-22 | 2022-07-11 | 台灣積體電路製造股份有限公司 | Semiconductor structure and mthhod of forming the same |
US11393779B2 (en) | 2018-06-13 | 2022-07-19 | Invensas Bonding Technologies, Inc. | Large metal pads over TSV |
US11430766B2 (en) | 2019-04-15 | 2022-08-30 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same |
US11456269B2 (en) | 2019-09-27 | 2022-09-27 | International Business Machines Corporation | Prevention of bridging between solder joints |
US20220344287A1 (en) * | 2021-04-27 | 2022-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated Circuit Structure and Method |
US11532533B2 (en) | 2019-10-18 | 2022-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit package and method |
US11587905B2 (en) * | 2019-10-09 | 2023-02-21 | Industrial Technology Research Institute | Multi-chip package and manufacturing method thereof |
US11694993B2 (en) | 2019-04-15 | 2023-07-04 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
US11710688B2 (en) | 2020-07-07 | 2023-07-25 | Mediatek Inc. | Semiconductor package structure |
US11728313B2 (en) | 2018-06-13 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Offset pads over TSV |
US11735529B2 (en) | 2021-05-21 | 2023-08-22 | International Business Machines Corporation | Side pad anchored by next adjacent via |
US11804377B2 (en) | 2018-04-05 | 2023-10-31 | Adeia Semiconductor Bonding Technologies, Inc. | Method for preparing a surface for direct-bonding |
US11929347B2 (en) | 2020-10-20 | 2024-03-12 | Adeia Semiconductor Technologies Llc | Mixed exposure for large die |
Families Citing this family (97)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7109092B2 (en) | 2003-05-19 | 2006-09-19 | Ziptronix, Inc. | Method of room temperature covalent bonding |
US7485968B2 (en) | 2005-08-11 | 2009-02-03 | Ziptronix, Inc. | 3D IC method and device |
US8735219B2 (en) | 2012-08-30 | 2014-05-27 | Ziptronix, Inc. | Heterogeneous annealing method and device |
US20150262902A1 (en) | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
US11069734B2 (en) | 2014-12-11 | 2021-07-20 | Invensas Corporation | Image sensor device |
US9741620B2 (en) | 2015-06-24 | 2017-08-22 | Invensas Corporation | Structures and methods for reliable packages |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US9953941B2 (en) | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
US10078183B2 (en) * | 2015-12-11 | 2018-09-18 | Globalfoundries Inc. | Waveguide structures used in phonotics chip packaging |
US9852988B2 (en) | 2015-12-18 | 2017-12-26 | Invensas Bonding Technologies, Inc. | Increased contact alignment tolerance for direct bonding |
US10446532B2 (en) | 2016-01-13 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Systems and methods for efficient transfer of semiconductor elements |
US20170338204A1 (en) * | 2016-05-17 | 2017-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device and Method for UBM/RDL Routing |
US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
US10332841B2 (en) * | 2016-07-20 | 2019-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | System on integrated chips and methods of forming the same |
US10446487B2 (en) | 2016-09-30 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
US10580735B2 (en) | 2016-10-07 | 2020-03-03 | Xcelsis Corporation | Stacked IC structure with system level wiring on multiple sides of the IC die |
TWI822659B (en) | 2016-10-27 | 2023-11-21 | 美商艾德亞半導體科技有限責任公司 | Structures and methods for low temperature bonding |
US10002844B1 (en) | 2016-12-21 | 2018-06-19 | Invensas Bonding Technologies, Inc. | Bonded structures |
US10796936B2 (en) | 2016-12-22 | 2020-10-06 | Invensas Bonding Technologies, Inc. | Die tray with channels |
WO2018125673A2 (en) | 2016-12-28 | 2018-07-05 | Invensas Bonding Technologies, Inc | Processing stacked substrates |
US20180182665A1 (en) | 2016-12-28 | 2018-06-28 | Invensas Bonding Technologies, Inc. | Processed Substrate |
KR20190092584A (en) | 2016-12-29 | 2019-08-07 | 인벤사스 본딩 테크놀로지스 인코포레이티드 | Bonded structure with integrated passive components |
JP7030825B2 (en) | 2017-02-09 | 2022-03-07 | インヴェンサス ボンディング テクノロジーズ インコーポレイテッド | Joined structure |
WO2018169968A1 (en) | 2017-03-16 | 2018-09-20 | Invensas Corporation | Direct-bonded led arrays and applications |
US10515913B2 (en) | 2017-03-17 | 2019-12-24 | Invensas Bonding Technologies, Inc. | Multi-metal contact structure |
US10508030B2 (en) | 2017-03-21 | 2019-12-17 | Invensas Bonding Technologies, Inc. | Seal for microelectronic assembly |
US10784191B2 (en) | 2017-03-31 | 2020-09-22 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
US10008454B1 (en) * | 2017-04-20 | 2018-06-26 | Nxp B.V. | Wafer level package with EMI shielding |
US10269756B2 (en) | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
US10879212B2 (en) | 2017-05-11 | 2020-12-29 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
US10529634B2 (en) | 2017-05-11 | 2020-01-07 | Invensas Bonding Technologies, Inc. | Probe methodology for ultrafine pitch interconnects |
US10446441B2 (en) | 2017-06-05 | 2019-10-15 | Invensas Corporation | Flat metal features for microelectronics applications |
US10217720B2 (en) | 2017-06-15 | 2019-02-26 | Invensas Corporation | Multi-chip modules formed using wafer-level processing of a reconstitute wafer |
US10276551B2 (en) * | 2017-07-03 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device package and method of forming semiconductor device package |
CN107507816A (en) * | 2017-08-08 | 2017-12-22 | 中国电子科技集团公司第五十八研究所 | Fan-out-type wafer scale multilayer wiring encapsulating structure |
US11195748B2 (en) | 2017-09-27 | 2021-12-07 | Invensas Corporation | Interconnect structures and methods for forming same |
US11031285B2 (en) | 2017-10-06 | 2021-06-08 | Invensas Bonding Technologies, Inc. | Diffusion barrier collar for interconnects |
US10622342B2 (en) * | 2017-11-08 | 2020-04-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Stacked LED structure and associated manufacturing method |
US10658313B2 (en) | 2017-12-11 | 2020-05-19 | Invensas Bonding Technologies, Inc. | Selective recess |
US11011503B2 (en) | 2017-12-15 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Direct-bonded optoelectronic interconnect for high-density integrated photonics |
US10217708B1 (en) | 2017-12-18 | 2019-02-26 | Apple Inc. | High bandwidth routing for die to die interposer and on-chip applications |
US10923408B2 (en) | 2017-12-22 | 2021-02-16 | Invensas Bonding Technologies, Inc. | Cavity packages |
US11380597B2 (en) | 2017-12-22 | 2022-07-05 | Invensas Bonding Technologies, Inc. | Bonded structures |
US10727219B2 (en) | 2018-02-15 | 2020-07-28 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
US11169326B2 (en) | 2018-02-26 | 2021-11-09 | Invensas Bonding Technologies, Inc. | Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects |
US11256004B2 (en) | 2018-03-20 | 2022-02-22 | Invensas Bonding Technologies, Inc. | Direct-bonded lamination for improved image clarity in optical devices |
US11244916B2 (en) | 2018-04-11 | 2022-02-08 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
US10790262B2 (en) | 2018-04-11 | 2020-09-29 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
US10964664B2 (en) | 2018-04-20 | 2021-03-30 | Invensas Bonding Technologies, Inc. | DBI to Si bonding for simplified handle wafer |
TWI672791B (en) | 2018-05-07 | 2019-09-21 | 財團法人工業技術研究院 | Chip package structure and manufacturing method thereof |
US10727203B1 (en) * | 2018-05-08 | 2020-07-28 | Rockwell Collins, Inc. | Die-in-die-cavity packaging |
US11004757B2 (en) | 2018-05-14 | 2021-05-11 | Invensas Bonding Technologies, Inc. | Bonded structures |
US11276676B2 (en) * | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
CN112514059B (en) | 2018-06-12 | 2024-05-24 | 隔热半导体粘合技术公司 | Interlayer connection for stacked microelectronic components |
US10910344B2 (en) | 2018-06-22 | 2021-02-02 | Xcelsis Corporation | Systems and methods for releveled bump planes for chiplets |
WO2020010056A1 (en) | 2018-07-03 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Techniques for joining dissimilar materials in microelectronics |
WO2020010265A1 (en) * | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
WO2020010136A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
US11515291B2 (en) | 2018-08-28 | 2022-11-29 | Adeia Semiconductor Inc. | Integrated voltage regulator and passive components |
US11296044B2 (en) | 2018-08-29 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes |
US10861808B2 (en) | 2018-11-21 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding structure of dies with dangling bonds |
US11244920B2 (en) | 2018-12-18 | 2022-02-08 | Invensas Bonding Technologies, Inc. | Method and structures for low temperature device bonding |
CN113330557A (en) | 2019-01-14 | 2021-08-31 | 伊文萨思粘合技术公司 | Bonding structure |
KR20200092566A (en) | 2019-01-25 | 2020-08-04 | 에스케이하이닉스 주식회사 | Semiconductor package including bridge die |
US10770433B1 (en) | 2019-02-27 | 2020-09-08 | Apple Inc. | High bandwidth die to die interconnect with package area reduction |
US11901281B2 (en) | 2019-03-11 | 2024-02-13 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures with integrated passive component |
US10854578B2 (en) | 2019-03-29 | 2020-12-01 | Invensas Corporation | Diffused bitline replacement in stacked wafer memory |
US11205625B2 (en) | 2019-04-12 | 2021-12-21 | Invensas Bonding Technologies, Inc. | Wafer-level bonding of obstructive elements |
US11373963B2 (en) | 2019-04-12 | 2022-06-28 | Invensas Bonding Technologies, Inc. | Protective elements for bonded structures |
US11610846B2 (en) | 2019-04-12 | 2023-03-21 | Adeia Semiconductor Bonding Technologies Inc. | Protective elements for bonded structures including an obstructive element |
US11355404B2 (en) | 2019-04-22 | 2022-06-07 | Invensas Bonding Technologies, Inc. | Mitigating surface damage of probe pads in preparation for direct bonding of a substrate |
US11562982B2 (en) * | 2019-04-29 | 2023-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit packages and methods of forming the same |
CN113853670A (en) * | 2019-05-22 | 2021-12-28 | 华为技术有限公司 | Manufacturing method of 3DIC chip and 3DIC chip |
US11385278B2 (en) | 2019-05-23 | 2022-07-12 | Invensas Bonding Technologies, Inc. | Security circuitry for bonded structures |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
CN110739292A (en) * | 2019-09-02 | 2020-01-31 | 上海先方半导体有限公司 | 3D packaging structure and manufacturing method thereof |
US11856800B2 (en) | 2019-09-20 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices with system on chip devices |
DE102020106799A1 (en) * | 2019-09-20 | 2021-03-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | SEMICONDUCTOR COMPONENTS AND METHOD OF MANUFACTURING |
US11476201B2 (en) * | 2019-09-27 | 2022-10-18 | Taiwan Semiconductor Manufacturing Company. Ltd. | Package-on-package device |
DE102020108481B4 (en) | 2019-09-27 | 2023-07-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die package and manufacturing process |
US11862602B2 (en) | 2019-11-07 | 2024-01-02 | Adeia Semiconductor Technologies Llc | Scalable architecture for reduced cycles across SOC |
WO2021092779A1 (en) * | 2019-11-12 | 2021-05-20 | 华为技术有限公司 | Chip package on package structure and electronic device |
US11762200B2 (en) | 2019-12-17 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded optical devices |
US11876076B2 (en) | 2019-12-20 | 2024-01-16 | Adeia Semiconductor Technologies Llc | Apparatus for non-volatile random access memory stacks |
US11721653B2 (en) | 2019-12-23 | 2023-08-08 | Adeia Semiconductor Bonding Technologies Inc. | Circuitry for electrical redundancy in bonded structures |
KR20220120631A (en) | 2019-12-23 | 2022-08-30 | 인벤사스 본딩 테크놀로지스 인코포레이티드 | Electrical Redundancy for Bonded Structures |
KR20230003471A (en) | 2020-03-19 | 2023-01-06 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | Dimensional Compensation Control for Directly Coupled Structures |
US11742314B2 (en) | 2020-03-31 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Reliable hybrid bonded apparatus |
US11804469B2 (en) * | 2020-05-07 | 2023-10-31 | Invensas Llc | Active bridging apparatus |
WO2021236361A1 (en) | 2020-05-19 | 2021-11-25 | Invensas Bonding Technologies, Inc. | Laterally unconfined structure |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US20220148953A1 (en) * | 2020-11-09 | 2022-05-12 | Qualcomm Incorporated | Hybrid reconstituted substrate for electronic packaging |
CN113544827A (en) * | 2021-05-21 | 2021-10-22 | 广东省科学院半导体研究所 | Chip packaging method and chip packaging structure |
US12015003B2 (en) | 2021-09-29 | 2024-06-18 | International Business Machines Corporation | High density interconnection and wiring layers, package structures, and integration methods |
CN114937633B (en) * | 2022-07-25 | 2022-10-18 | 成都万应微电子有限公司 | Radio frequency chip system-in-package method and radio frequency chip system-in-package structure |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8263434B2 (en) | 2009-07-31 | 2012-09-11 | Stats Chippac, Ltd. | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP |
US8518746B2 (en) | 2010-09-02 | 2013-08-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die |
US9947609B2 (en) | 2012-03-09 | 2018-04-17 | Honeywell International Inc. | Integrated circuit stack |
US9385052B2 (en) * | 2012-09-14 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages |
US9818734B2 (en) * | 2012-09-14 | 2017-11-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming build-up interconnect structures over a temporary substrate |
KR101419597B1 (en) | 2012-11-06 | 2014-07-14 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
KR101419601B1 (en) | 2012-11-20 | 2014-07-16 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device using epoxy molding compound wafer support system and fabricating method thereof |
US8946784B2 (en) * | 2013-02-18 | 2015-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for image sensor packaging |
US9331032B2 (en) | 2013-03-06 | 2016-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding and apparatus for performing the same |
US9728453B2 (en) * | 2013-03-15 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for hybrid wafer bonding integrated with CMOS processing |
US9087821B2 (en) * | 2013-07-16 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
KR20150014214A (en) | 2013-07-29 | 2015-02-06 | 삼성전기주식회사 | Molding composition for semiconductor package and semiconductor package using the same |
US9379078B2 (en) | 2013-11-07 | 2016-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D die stacking structure with fine pitches |
US9293437B2 (en) * | 2014-02-20 | 2016-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Functional block stacked 3DIC and method of making same |
US9666520B2 (en) * | 2014-04-30 | 2017-05-30 | Taiwan Semiconductor Manufactuing Company, Ltd. | 3D stacked-chip package |
KR101729378B1 (en) * | 2014-05-30 | 2017-04-21 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor devices and methods of manufacture thereof |
-
2015
- 2015-11-06 US US14/935,310 patent/US9559081B1/en active Active
-
2016
- 2016-06-15 WO PCT/US2016/037690 patent/WO2017034654A1/en active Application Filing
- 2016-06-15 CN CN201680043123.0A patent/CN107851615B/en active Active
- 2016-06-15 KR KR1020187004420A patent/KR102033865B1/en active IP Right Grant
- 2016-07-05 TW TW105121277A patent/TWI621228B/en active
Cited By (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10580739B2 (en) * | 2016-11-04 | 2020-03-03 | Phoenix & Corporation | Package substrate and associated fabrication method with varying depths for circuit device terminals |
US20180130745A1 (en) * | 2016-11-04 | 2018-05-10 | Phoenix Pioneer Technology Co., Ltd. | Package substrate and its fabrication method |
US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
US11552041B2 (en) | 2017-09-24 | 2023-01-10 | Adeia Semiconductor Bonding Technologies Inc. | Chemical mechanical polishing for hybrid bonding |
US11127686B2 (en) | 2017-09-29 | 2021-09-21 | Murata Manufacturing Co., Ltd. | Radio-frequency module and communication device |
WO2019065668A1 (en) * | 2017-09-29 | 2019-04-04 | 株式会社村田製作所 | High frequency module and communication device |
US11804377B2 (en) | 2018-04-05 | 2023-10-31 | Adeia Semiconductor Bonding Technologies, Inc. | Method for preparing a surface for direct-bonding |
US11749645B2 (en) | 2018-06-13 | 2023-09-05 | Adeia Semiconductor Bonding Technologies Inc. | TSV as pad |
US11955445B2 (en) | 2018-06-13 | 2024-04-09 | Adeia Semiconductor Bonding Technologies Inc. | Metal pads over TSV |
US11728313B2 (en) | 2018-06-13 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Offset pads over TSV |
US11393779B2 (en) | 2018-06-13 | 2022-07-19 | Invensas Bonding Technologies, Inc. | Large metal pads over TSV |
US11011494B2 (en) | 2018-08-31 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
WO2020046677A1 (en) * | 2018-08-31 | 2020-03-05 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
US11756880B2 (en) | 2018-10-22 | 2023-09-12 | Adeia Semiconductor Bonding Technologies Inc. | Interconnect structures |
US11158573B2 (en) | 2018-10-22 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Interconnect structures |
US11282761B2 (en) | 2018-11-29 | 2022-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of manufacturing the same |
US11562985B2 (en) | 2019-04-15 | 2023-01-24 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same |
US11749641B2 (en) | 2019-04-15 | 2023-09-05 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
US12002788B2 (en) | 2019-04-15 | 2024-06-04 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same |
WO2020211272A1 (en) * | 2019-04-15 | 2020-10-22 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
US11430766B2 (en) | 2019-04-15 | 2022-08-30 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and dynamic random-access memory and methods for forming the same |
US11694993B2 (en) | 2019-04-15 | 2023-07-04 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
US11158604B2 (en) | 2019-04-15 | 2021-10-26 | Yangtze Memory Technologies Co., Ltd. | Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same |
US11367729B2 (en) | 2019-04-30 | 2022-06-21 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and NAND flash memory and methods for forming the same |
US11864367B2 (en) | 2019-04-30 | 2024-01-02 | Yangtze Memory Technologies Co., Ltd. | Bonded semiconductor devices having processor and NAND flash memory and methods for forming the same |
KR102661671B1 (en) * | 2019-07-25 | 2024-04-29 | 삼성전자주식회사 | Semiconductor package having stacked semiconductor chips |
KR20210012372A (en) * | 2019-07-25 | 2021-02-03 | 삼성전자주식회사 | Semiconductor package having stacked semiconductor chips |
US11456269B2 (en) | 2019-09-27 | 2022-09-27 | International Business Machines Corporation | Prevention of bridging between solder joints |
US11264314B2 (en) * | 2019-09-27 | 2022-03-01 | International Business Machines Corporation | Interconnection with side connection to substrate |
US11587905B2 (en) * | 2019-10-09 | 2023-02-21 | Industrial Technology Research Institute | Multi-chip package and manufacturing method thereof |
US11532533B2 (en) | 2019-10-18 | 2022-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit package and method |
TWI741837B (en) * | 2019-10-18 | 2021-10-01 | 台灣積體電路製造股份有限公司 | Integrated circuit package and method of forming the same |
DE102019129840B4 (en) | 2019-10-18 | 2021-08-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | SEMICONDUCTOR COMPONENT AND METHOD FOR MANUFACTURING IT |
DE102019129840A1 (en) * | 2019-10-18 | 2021-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | SEMICONDUCTOR COMPONENT AND METHOD FOR MANUFACTURING IT |
CN112701130A (en) * | 2019-10-22 | 2021-04-23 | 财团法人工业技术研究院 | Image sensor package and method of manufacturing the same |
US11728254B2 (en) | 2020-05-22 | 2023-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Giga interposer integration through chip-on-wafer-on-substrate |
US11967546B2 (en) | 2020-05-22 | 2024-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Giga interposer integration through Chip-On-Wafer-On-Substrate |
TWI770609B (en) * | 2020-05-22 | 2022-07-11 | 台灣積體電路製造股份有限公司 | Semiconductor structure and mthhod of forming the same |
US11710688B2 (en) | 2020-07-07 | 2023-07-25 | Mediatek Inc. | Semiconductor package structure |
US11929347B2 (en) | 2020-10-20 | 2024-03-12 | Adeia Semiconductor Technologies Llc | Mixed exposure for large die |
US11764171B2 (en) * | 2021-04-27 | 2023-09-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit structure and method |
US20230369254A1 (en) * | 2021-04-27 | 2023-11-16 | Taiwan Semiconductor Manufacturing Co., Ltd | Integrated Circuit Structure and Method |
US20220344287A1 (en) * | 2021-04-27 | 2022-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated Circuit Structure and Method |
US11735529B2 (en) | 2021-05-21 | 2023-08-22 | International Business Machines Corporation | Side pad anchored by next adjacent via |
TWI764852B (en) * | 2021-06-30 | 2022-05-11 | 聯發科技股份有限公司 | Semiconductor package structure |
Also Published As
Publication number | Publication date |
---|---|
CN107851615B (en) | 2021-01-05 |
WO2017034654A1 (en) | 2017-03-02 |
KR20180030147A (en) | 2018-03-21 |
CN107851615A (en) | 2018-03-27 |
TW201712824A (en) | 2017-04-01 |
TWI621228B (en) | 2018-04-11 |
US9559081B1 (en) | 2017-01-31 |
KR102033865B1 (en) | 2019-10-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9559081B1 (en) | Independent 3D stacking | |
US11239157B2 (en) | Package structure and package-on-package structure | |
US9679801B2 (en) | Dual molded stack TSV package | |
US9935087B2 (en) | Three layer stack structure | |
US11217563B2 (en) | Fully interconnected heterogeneous multi-layer reconstructed silicon device | |
TWI627716B (en) | System in package fan out stacking architecture and process flow | |
US10770433B1 (en) | High bandwidth die to die interconnect with package area reduction | |
US11195816B2 (en) | Integrated circuit packages comprising a plurality of redistribution structures and methods of forming the same | |
US8093711B2 (en) | Semiconductor device | |
US11056373B2 (en) | 3D fanout stacking | |
KR20180027679A (en) | Semiconductor package and method of fabricating the same | |
US20230170272A1 (en) | Semiconductor package and method of fabricating the same | |
TWI407540B (en) | Multi-chip stacked structure having through silicon via and fabrication method thereof | |
KR20130077627A (en) | Semicondcutor apparatus and method of manufacturing the same | |
US20220352077A1 (en) | Recessed semiconductor devices, and associated systems and methods | |
US20230031430A1 (en) | Package structure and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: APPLE INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LAI, KWAN-YU;ZHAI, JUN;HU, KUNZHONG;SIGNING DATES FROM 20151105 TO 20151106;REEL/FRAME:036983/0939 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
CC | Certificate of correction | ||
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |