CN113853670A

CN113853670A - Manufacturing method of 3DIC chip and 3DIC chip

Info

Publication number: CN113853670A
Application number: CN201980096667.7A
Authority: CN
Inventors: 顾识群; 尹学武; 王正波
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-05-22
Filing date: 2019-05-22
Publication date: 2021-12-28
Also published as: WO2020232678A1

Abstract

The embodiment of the application provides a 3DIC chip and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: detecting the first bare chip wafer, and screening out effective chips in the first bare chip wafer as first chips; preparing an interconnection layer on the surface of a first wafer; fixing a second wafer on the surface of the interconnection layer; the interconnection layer is provided with a signal line, and the signal line is coupled with the first wafer and/or the second wafer. The 3DIC chip manufactured by the method can improve the product yield of the 3DIC chip and reduce the process cost of the 3DIC chip.

Description

Manufacturing method of 3DIC chip and 3DIC chip

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a 3DIC chip and a method for manufacturing the same.

Background

As moore's law slows down, 3d ic (3 DIC) becomes one of the important research directions for continuing moore's law.

The 3DIC mainly refers to stacking small-sized dies by Hybrid Bonding (HB) technology in a thickness direction of a die wafer (die wafer). In general, 3DIC processes typically include the following steps: first, a plurality of individual IC traces are fabricated in a die wafer. Thereafter, one or more small chips are bonded above each IC die (in the thickness direction of the die wafer) by the HB technique. Finally, the die wafer is cut, and the area where one IC circuit is located in the die wafer and the small chips stacked above the IC circuit form one chip. The stacking of the multi-layer chips can be realized through the bonding technology in the thickness direction of the bare chip wafer, so that the integration level of the chips in unit area is improved.

However, the conventional 3DIC fabrication process has a low product yield and a high cost, and thus, the 3DIC technology is still under study.

Disclosure of Invention

The embodiment of the application provides a manufacturing method of a 3DIC chip and the 3DIC chip, and the effective wafer in the first bare chip wafer is screened to serve as the first wafer in the 3DIC chip, so that the product yield of the 3DIC chip is improved, and the process cost is reduced.

In a first aspect, an embodiment of the present application provides a method for manufacturing a 3DIC chip, including: detecting the first die wafer, and screening a first chip in the first die wafer, wherein the first chip is an effective chip in the first die wafer; preparing an interconnection layer on the surface of a first wafer; fixing a second wafer on the surface of the interconnection layer; the interconnection layer is provided with a signal line, and the signal line is coupled with the first wafer and/or the second wafer.

The 3DIC chip manufactured by the method has the advantages that the first wafer is an effective wafer obtained through screening, so that the first wafer has high yield, and the product yield of the 3DIC chip manufactured by the first wafer can be improved. Moreover, in the embodiment of the present application, the interconnection layer and the second chip are prepared only for the first chip, which is beneficial to reducing the waste of the invalid chips in the first die wafer to the process cost. In summary, the manufacturing method provided by the embodiment of the application can improve the product yield of the 3DIC chip and reduce the process cost of the 3DIC chip.

In a possible implementation manner, before the second chip is fixed on the surface of the interconnection layer, the second die wafer may be further inspected to screen out valid chips in the second die wafer as the second chips.

By adopting the method, the second wafer for manufacturing the 3DIC chip is also the screened second wafer, so that the yield of the second wafer can be improved, and the product yield of the 3DIC chip can be further improved.

For example, the interconnection layer may be prepared on the surface of the first wafer by bonding, that is, the interconnection layer may be generated on the surface of the carrier, and then the active surface of the first wafer may be fixed on the surface of the interconnection layer.

In one possible implementation, after the surface of the interconnect layer is fixed to the active surface of the first wafer, an insulating medium may be prepared on the surface of the interconnect layer in a region other than the first wafer to enhance the mechanical strength of the 3DIC chip.

In a possible implementation, the support layer may be prepared on the passive side of the first wafer, the carrier on the surface of the interconnect layer is removed, and then the second wafer is fixed on the surface of the interconnect layer.

Illustratively, holding a second wafer on a surface of the interconnect layer includes: the active surface of the second wafer is fixed on the surface of the interconnection layer.

In one possible implementation, after the active face of the second wafer is fixed on the surface of the interconnection layer, an insulating medium may be prepared on the surface of the interconnection layer in a region other than the second wafer to enhance the mechanical strength of the 3DIC chip.

In one possible implementation, the second wafer includes insulating layer vias TIV, and first metal lines passing through the TIVs, wherein the IC lines of the second wafer are coupled with the first metal lines. Illustratively, after the surface of the interconnect layer fixes the active surface of the second wafer, the method further comprises: etching the passive side of the second wafer to expose the first metal lines in the TIV of the second wafer; a wiring layer is prepared on the passive side of the second wafer, the wiring layer including second metal lines therein, and the second metal lines in the wiring layer being coupled with the first metal lines in the TIV of the second wafer.

In a possible implementation manner, a wiring layer may be prepared on the surface of the carrier, where the wiring layer includes a second metal line; fixing the active surface of the first wafer on the surface of the wiring layer, so that the second metal wire of the wiring layer is coupled with the IC circuit of the first wafer; the first wafer comprises an insulating layer through hole TIV and a third metal wire penetrating through the TIV, and the IC circuit of the first wafer is coupled with the third metal wire in the TIV of the first wafer; etching the passive side of the first wafer to expose a third metal line in the TIV of the first wafer; an interconnect layer is then fabricated on the passive side of the first wafer such that the third metal line in the TIV of the first wafer is coupled to the signal line in the interconnect layer.

In one possible implementation, the insulating medium may be prepared on the surface of the wiring layer in a region other than the first wafer, and then the interconnection layer may be prepared on the surface of the first wafer to enhance the mechanical strength of the 3DIC chip.

Illustratively, holding the second wafer at the surface of the interconnect layer includes: the active surface of the second wafer is fixed on the surface of the interconnection layer.

In one possible implementation, after the second wafer is fixed on the surface of the interconnection layer, an insulating medium may be prepared on the surface of the interconnection layer except for the second wafer to enhance the mechanical strength of the 3DIC chip.

In a possible implementation, after the second wafer is fixed on the surface of the interconnection layer, a support layer can be prepared on the passive surface of the second wafer, and the carrier on the surface of the wiring layer is removed.

In a second aspect, an embodiment of the present application further provides a 3DIC chip, where the 3DIC chip is suitable for the manufacturing method provided in the first aspect and any possible implementation manner of the first aspect. Specifically, the 3DIC chip includes: a first wafer, a second wafer, a support layer, and an interconnect layer; the first surface of the interconnection layer is provided with a first wafer, the second surface of the interconnection layer is provided with a second wafer, the interconnection layer comprises a signal line, and the signal line is coupled with the first wafer and/or the second wafer; the supporting layer is arranged on the surface of the first wafer or the second wafer and used for improving the mechanical strength of the chip.

In one possible implementation, the first die is an active die obtained by inspecting the first die wafer, and/or the second die is an active die obtained by inspecting the second die wafer.

In one possible implementation, the first surface of the interconnect layer holds the active face of the first wafer.

In one possible implementation, the region of the first surface other than the first wafer is provided with an insulating medium.

In one possible implementation, the support layer is disposed on the passive side of the first wafer.

In one possible implementation, the second surface of the interconnect layer holds the active face of the second wafer.

In a possible implementation, the second surface is provided with an insulating medium in regions other than the second wafer.

In one possible implementation, the second wafer includes an insulating layer via TIV, and a first metal line passing through the TIV, the IC line in the active face of the second wafer being coupled with the first metal line in the TIV; the chip further comprises a wiring layer, wherein the wiring layer is arranged on the passive surface of the second wafer; the routing layer includes a second metal line, the second metal line of the routing layer coupled to the first metal line in the TIV of the second wafer.

In one possible implementation, a chip includes a plurality of first wafers; the interconnect layer further includes lateral metal lines respectively coupled to at least two of the plurality of first dies.

In one possible implementation, the chip further includes a wiring layer disposed on the active surface of the first wafer, the wiring layer including a second metal line, the second metal line of the wiring layer being coupled to the IC line of the first wafer; the first wafer comprises an insulating layer through hole (TIV) and a third metal line penetrating through the TIV, and the IC circuit in the active surface of the first wafer is coupled with the third metal line in the TIV;

an interconnect layer is disposed on the passive side of the first wafer, and a third metal line is coupled to the signal line in the interconnect layer.

In one possible implementation, the surface of the wiring layer is provided with an insulating medium in a region other than the first wafer.

In one possible implementation, the active face of the second wafer is fixed at the second surface of the interconnect layer.

In one possible implementation, the support layer is disposed on the passive side of the second wafer.

In one possible implementation, a chip includes a plurality of first wafers; the wiring layer further includes fourth metal lines respectively coupled to at least two of the plurality of first wafers.

In a possible implementation manner, the silicon supporting layer is a silicon substrate, and the silicon supporting layer is bonded to the surface of the first wafer or the second wafer; or the silicon supporting layer is a silicon deposition layer, and the silicon supporting layer is deposited on the surface of the first wafer or the second wafer.

Drawings

FIG. 1 is a schematic diagram of a die wafer structure;

FIG. 2 is a schematic diagram of a 3DIC chip;

FIG. 3 is a schematic diagram of a 3DIC chip having the F2F structure;

FIG. 4 is a schematic diagram of a 3DIC chip having the F2B structure;

FIG. 5 is a schematic flow chart illustrating a method for fabricating a 3DIC chip according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram of a 3DIC chip having an F2F structure according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 15 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 16 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 17 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 18 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 19 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

FIG. 20 is a schematic diagram illustrating an intermediate structure of a 3DIC chip according to an embodiment of the present disclosure;

fig. 21 is a schematic structural diagram of a 3DIC chip having an F2B structure according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings. The particular methods of operation in the method embodiments may also be applied to apparatus embodiments or system embodiments. It is to be noted that "at least one" in the description of the present application means one or more, where a plurality means two or more. In view of this, the "plurality" may also be understood as "at least two" in the embodiments of the present invention. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" generally indicates that the preceding and following related objects are in an "or" relationship, unless otherwise specified. In addition, it is to be understood that the terms first, second, etc. in the description of the present application are used for distinguishing between the descriptions and not necessarily for describing a sequential or chronological order. In the description of the embodiments of the present application, "coupled" refers to a direct or indirect electrical connection relationship, for example, "a and B coupled" may mean that a and B are directly electrically connected, and may mean that a and B are electrically connected through C.

For convenience, specific spatially relative terminology is used in the following description and is not intended to be limiting. The words "upper" and "lower" designate directions in the drawings to which reference is made. The terminology includes the words above specifically mentioned, derivatives thereof and words of similar import. "over ….," over … …, "on … …," "above," and the like, are used to describe the spatial relationship of one device or feature to another device or feature as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

First, some concepts related to the embodiments of the present application will be explained:

(1) die wafer (wafer): generally, the integrated circuit comprises a semiconductor substrate and a circuit layer disposed on the semiconductor substrate, wherein semiconductor devices such as transistors are formed on the semiconductor substrate, a plurality of circuit layers are disposed in the circuit layer, and the circuit layer is generally provided with various functional circuits, which are coupled with the semiconductor devices on the semiconductor substrate, so as to form a complete chip circuit structure, i.e., an IC circuit. As shown in fig. 1, where 1 small square represents an individual IC circuit, a die wafer may include a plurality of IC circuits therein.

(2) Wafer: which may also be referred to as die (die), is an unpackaged die obtained by dicing a die wafer. Typically, each die is a functionally independent, unpackaged chip that may be comprised of one or more circuits. As shown in fig. 3, the die wafer is diced according to the dotted lines in fig. 1 to obtain a plurality of chips, each chip including an IC circuit. The surface of the wafer on the side where the IC circuit is located may be referred to as an active surface, and the surface of the wafer on the side where the semiconductor substrate is located may be referred to as a passive surface. After the bare chip wafer is cut, the obtained chip can be thinned, so that the thickness of the chip is reduced, the chip is lighter and thinner, and the heat dissipation capability is better.

(3) Bonding: cleaning and activating two sheets of homogeneous or heterogeneous semiconductor material with clean and atomically flat surfacesThe wafer is bonded into a whole by Van der Waals force, molecular force and even atomic force. In the integrated circuit packaging process, silicon dioxide (SiO) can be used₂) Molecular bond-SiO₂-SiO ₂Providing mechanical bonding between the two sheets and electrical bonding between the two sheets by copper (Cu) atomic bonds.

In the field of current integrated circuits, in order to meet the increasing demand of the market for high-integration chips, the industry has started to adopt a three-dimensional integrated circuit (3 DIC) packaging technology to prepare 3DIC chips. As shown in fig. 2, the 3DIC chip mainly includes a lower wafer 100, an upper wafer 200, and an interconnection layer 300 disposed between the lower wafer and the upper wafer.

Specifically, the lower wafer 100 may be a logic wafer, such as a processor or an Intellectual Property (IP) core (Cores), and the upper wafer 200 may be a memory (including a random access memory (SRAM) and a Dynamic Random Access Memory (DRAM)), a micro-electro-mechanical system (MEMS), a passive device (passive device), an interposer (interposer), or the like; alternatively, the lower wafer 100 may be a memory, MEMS, passive device or interposer, etc., and the upper wafer 200 may be a logic die, such as a processor or intellectual property core.

Since the lower wafer 100 and the upper wafer 200 are not of the same type in most cases, the lower wafer 100 and the upper wafer 200 tend to have different sizes therebetween. As shown in fig. 2, the lower wafer 100 has a size larger than that of the upper wafer 200. The interconnection layer 300 covers the surface of the lower wafer 100, and on the surface of the interconnection layer 300 contacting the upper wafer 200, an area other than the upper wafer 200 may be provided with an insulating medium 400 to fill the area of the surface of the interconnection layer 300 not covered by the upper wafer 200.

Signal lines are provided in the interconnect layer 300, and electrical signals can be transmitted inside the 3DIC chip. Some of the signal lines may be coupled to the lower wafer 100 and the upper wafer 200, respectively, so as to realize coupling between the lower wafer 100 and the upper wafer 200, so that electrical signals can be transmitted between the lower wafer 100 and the upper wafer 200.

Currently, 3DIC chips commonly used in the industry are mainly classified into a face-to-face (F2F) structure and a face-to-back (F2B) structure. Next, a 3DIC chip having an F2F structure and a 3DIC chip having an F2B structure will be described.

In the 3DIC chip of the F2F structure, the active surface of the lower wafer 100 and the active surface of the upper wafer 200 are both bonded to the interconnect layer 300. FIG. 3 schematically shows a 3DIC chip with an F2F structure. As shown in fig. 3, in the 3DIC chip, an IC circuit 102 is formed in an active surface 101 of a lower wafer 100, the active surface 101 is bonded to a surface 301 of an interconnect layer 300, an IC circuit 202 is formed in an active surface 201 of an upper wafer 200, and the active surface 201 is bonded to a surface 302 of the interconnect layer 300. The signal lines 303 in the interconnect layer 300 are coupled to the IC lines 102 at one end and the IC lines 202 at the other end, thereby achieving coupling between the lower wafer 100 and the upper wafer 200.

In the 3DIC chip of the F2B structure, the passive side of the lower wafer 100 is bonded to the interconnect layer 300 and the active side of the upper wafer 200 is bonded to the interconnect layer 300, or the active side of the lower wafer 100 is bonded to the interconnect layer 300 and the passive side of the upper wafer 200 is bonded to the interconnect layer 300. FIG. 4 illustrates a 3DIC chip schematic of one F2B configuration. As shown in fig. 4, the passive side 103 of the lower wafer 100 of the 3DIC chip is bonded to the surface 301 of the interconnect layer 300 and the active side 201 of the upper wafer 200 is bonded to the surface 302 of the interconnect layer 300. The lower wafer 100 further includes a Through Insulator Via (TIV) 104, the TIV104 includes a metal line therein, the metal line in the TIV104 passes through the TIV104, and one end of the metal line is coupled to the IC line 102 and the other end is coupled to the signal line 303, so that the lower wafer 100 can be coupled to the upper wafer 200.

Currently, 3DIC chips with either F2F or F2B structures can be realized by wafer to wafer (W2W) or wafer to wafer (D2W) processes. Specifically, the W2W process mainly comprises the following steps: step one, preparing an interconnection layer on the surface of a first die wafer on which a plurality of IC circuits 102 are fabricated. And step two, bonding the second die wafer with the plurality of IC circuits 202 with the interconnection layer. And step three, cutting the structure obtained after the two bare chip wafers are bonded, thereby obtaining a plurality of 3DIC chips. However, the W2W process requires high precision, and thus the yield of the product is still to be improved.

The product yield of the D2W process is higher than that of the W2W process. The D2W process mainly comprises the following steps: step one, preparing an interconnection layer on the surface of a first die wafer on which a plurality of IC circuits 102 are fabricated. Step two, the second die wafer is cut into a plurality of upper chips 200. And step three, bonding a plurality of upper wafers 200 with the interconnection layers respectively, wherein the position of one upper wafer 200 on the interconnection layer corresponds to the position of the IC circuit 102 bonded with the interconnection layer on the position.

However, even if the D2W process is used to fabricate chips, the current product yield is still not ideal. This is because, whether the W2W process or the D2W process is based on a first die wafer, an interconnect layer is superimposed over the first die wafer, and a second die wafer or an upper die is superimposed over the interconnect layer. However, in a batch production process, the first die wafer tends to have a large area. As the area of the first die wafer increases, the yield of the IC circuitry 102 gradually decreases.

In addition, the yield of the bottom wafer 100 generally conforms to the following formula:

Y＝Y ⁰*exp(-D ₀area) (formula one)

Wherein Y is the yield of the bottom wafer 100, Y⁰To a predetermined coefficient, D₀Which is a defect density factor, typically about 0.1, Area is the Area of the underlying wafer 100.

When the area of the bottom wafer 100 exceeds 600mm²In this case, the yield of the underlying wafer 100 may be as low as 10% or less.

Due to the yield of the bottom wafer 100, the yield of 3DIC chips is often not ideal. Moreover, the process cost of the W2W process and the D2W process is very high, and if the yield of the chip obtained by one production process is low, the process cost will be greatly wasted, which is not favorable for reducing the process cost of the 3DIC chip as a whole.

In view of this, embodiments of the present application provide a method for manufacturing a 3DIC chip, in the 3DIC chip manufactured by the method, a lower wafer is an effective wafer that has been screened, so that a yield of the lower wafer can be ensured, a product yield of the 3DIC chip can be improved, and a reduction in process cost of the 3DIC chip is facilitated.

Exemplarily, fig. 5 is a schematic flow chart illustrating a manufacturing method of a 3DIC chip according to an embodiment of the present disclosure. It is understood that in the embodiments described below, the first wafer may be the lower wafer 100 and the second wafer may be the upper wafer 200, or the first wafer may be the upper wafer 200 and the second wafer may be the lower wafer 100. For convenience of description, the first wafer 100 is taken as the lower wafer 100, and the second wafer 200 is taken as the upper wafer 200.

As shown in fig. 5, the method mainly comprises the following steps:

s501: and detecting the first die wafer, and screening a first chip in the first die wafer, wherein the first chip is an effective chip in the first die wafer.

For example, the first die wafer may be cut into a plurality of chips, and each chip may be tested by using a probe, so as to select a qualified chip, i.e., a valid chip, from the plurality of chips as the first chip. The first die may also be obtained by testing the IC circuits in the first die wafer with a probe, selecting the qualified IC circuits from the IC circuits, and cutting the areas where the qualified IC circuits are located.

S502: an interconnect layer is prepared on a surface of the first wafer. For example, the interconnection layer may be first formed on the carrier, and then bonded to the first wafer, or may be directly formed on the surface of the first wafer through deposition, etching, sputtering, or other processes.

S503: and fixing the second wafer on the surface of the interconnection layer, wherein a signal line is arranged in the interconnection layer and is coupled with the first wafer and/or the second wafer.

It is understood that the second wafer may also be a valid wafer from the screening. Specifically, the second die wafer may be inspected first, and the effective chips in the second die wafer are screened out as the second chips. In this case, the yield of the second wafer for fabricating the 3DIC chip can be improved, thereby further improving the yield of the 3DIC chip.

It should be noted that, in the embodiment of the present application, S503 has many possible implementations, for example, a second wafer may be bonded to the surface of the interconnect layer, or a second wafer may be fabricated on the surface of the interconnect layer.

In addition, depending on the 3DIC chip architecture, there are also various ways of coupling between the signal lines in the interconnect layer and the first and second wafers. For example, there is a portion of signal lines in the interconnect layer, one end coupled to the first die and the other end coupled to the second die, as shown by signal lines 303 in fig. 3. Also for example, there may be a portion of the signal lines in the interconnect layer that are coupled only to the first or second wafer.

Next, the manufacturing method provided in the embodiments of the present application will be further described with reference to the following two embodiments.

Example one

The manufacturing method of the 3DIC chip with the F2F structure mainly comprises the following steps:

in the first step, the first chip in the first die wafer is screened, which can refer to the specific implementation of S501 described above, and is not described again here.

And step two, generating an interconnection layer on the surface of the carrier. As with the intermediate structure shown in fig. 6, the interconnect layer 300 may be formed on the carrier 500 by a process such as deposition. In particular, SiO can be deposited₂As the main material of the interconnection layer 300, and in SiO₂ A signal line 303 made of metal is formed. The positions of the signal lines 303 in the interconnect layer 300 may be set according to the positions and structures of the IC lines 102 in the first wafer 100 and the positions and structures of the IC lines 202 in the second wafer 200, so that the IC lines 102 and the IC lines 202 may be accurately aligned in the subsequent bonding process.

Step three, preparing a bonding pad (pad) on the active surface 101 of the first wafer 100, and preparing a bonding pad on the surface 301 of the interconnect layer 300, thereby bonding the active surface 101 of the first wafer 100 on the surface 301 of the interconnect layer 300.

In one possible implementation, as shown in fig. 7, a plurality of first dies 100, such as a first die 100a and a first die 100b, may be included in the 3DIC chip. First die 100a and first die 100b are coupled for cooperatively performing the logic functions of first die 100. In this case, in the second step, as shown in fig. 6, it is also necessary to form a signal line 304 in the interconnect layer 300, and after the active surface 101a of the first wafer 100a is bonded to the interconnect layer 300, the IC line in the first wafer 100a is coupled to the signal line 303 on one side of the signal line 304, and after the active surface 101b of the first wafer 100b is bonded to the interconnect layer 300, the IC line in the first wafer 100b is coupled to the signal line 303 on the other side of the signal line 304. The signal lines 304 in the interconnect layer 300 are coupled at one end to the IC lines in the first die 100a and at the other end to the IC lines in the first die 100b such that the first die 100a and the first die 100b are coupled via the signal lines 304.

The 3DIC chip may have a plurality of first wafers 100 disposed therein, so that the area of a single first wafer 100 may be reduced. In the wafer fabrication process, the smaller the area of the wafer is, the higher the yield is, and therefore, reducing the area of the single first wafer 100 is beneficial to improving the yield of the first wafer 100, thereby further reducing the process cost.

In order to improve the mechanical strength of the 3DIC chip, in one possible implementation, after the third step, a fourth step may be performed, such as the intermediate structure shown in fig. 8, and a chemical vapor deposition, a physical vapor deposition, or the like may be used to prepare the insulating medium 400 on the surface of the interconnect layer 300 in the region except the first wafer (100a and 100 b). Specifically, the thickness of the insulating medium 400 is not less than that of the first wafers (100a and 100b) to sufficiently fill the regions not occupied by the first wafers (100a and 100b), thereby enhancing the mechanical strength of the 3DIC chip.

Step five, as shown in the intermediate structure of fig. 9, a support layer 600 is prepared on the passive side of the first wafer 100. Illustratively, a deposition process may be used to directly deposit a certain thickness of silicon (Si) on the passive surface of the first wafer 100 as the support layer 600, a bonding process may be used to bond a silicon substrate on the passive surface of the first wafer 100, and so on.

Before the support layer 600 is prepared by the bonding process, the insulating medium 400 and the plane where the passive surface of the first wafer 100 is located may be polished, and polishing processes such as Chemical Mechanical Polishing (CMP), Physical Mechanical Polishing (PMP), and the like may be applied. The passive side of the first wafer (100a and 100b) and the surface of the insulating medium 400 are made smoother by the polishing process, and can be more firmly bonded to the support layer 600.

In the embodiment of the present application, since the thicknesses of the first wafers (100a and 100b) and the insulating medium 400 are often small, the mechanical strength of the first wafers (100a and 100b) and the insulating medium 400 is not sufficient to support the subsequent processes. By bonding the supporting layer 600, the mechanical strength of the intermediate structure during the subsequent process can be increased, so that the intermediate structure can better support the subsequent process.

Sixth, after the passive side of the first wafer (100a and 100b) is bonded to the supporting layer 600, the carrier 500 may be removed to expose the other surface of the interconnection layer 300, and an intermediate structure as shown in fig. 10 may be obtained.

Thereafter, a second wafer may be bonded to the other surface of the interconnect layer 300. In a possible implementation manner, before bonding the second wafer, step seven may be performed to inspect the second die wafer, and the obtained valid wafer is used as the second wafer 200, so as to further improve the product yield of the 3DIC chip.

Step eight, preparing a bonding pad on the surface of the interconnection layer 300, preparing a bonding pad on the active surface of the second wafer 200, thereby bonding the active surface of the second wafer 200 on the surface of the interconnection layer 300, and coupling the IC circuit 202 in the second wafer 200 with the signal circuit 303 in the interconnection layer 300, so as to obtain the structure shown in fig. 11. In the structure shown in fig. 11, the 3DIC chip includes three second wafers (200a, 200b, and 200 c). Typically, the three second dies may be used to implement different logic functions, respectively. In the case where a plurality of first wafers and a plurality of second wafers exist in the 3DIC chip, there are many possibilities of the coupling manner between the second wafers and the first wafers. Such as the

second wafers

200a and 200c, may be coupled to only one first wafer 100, and, for example, the second wafer 200b may be coupled to both the first wafer 100a and the first wafer 100 b. The number of the second wafers 200 and the specific coupling manner between the second wafers 200 and the first wafer 100 are not limited in the embodiments of the present application.

Step nine, an insulating dielectric 400 is prepared on the surface of the interconnect layer 300 in the areas other than the

second wafers

200a, 200b and 200c, resulting in an intermediate structure as shown in fig. 12. For specific implementation, reference may be made to step four, which is not described in detail again.

As shown in fig. 12, in one possible implementation, after the insulating medium 400 is prepared, a TIV401 may be further fabricated in the insulating medium 400, and metal lines in the TIV401 are coupled to a part of the signal lines 303 in the interconnect layer 300.

Step ten, as shown in fig. 12, the

second wafers

200a, 200b and 200c also include a TIV, and metal lines in the TIV are coupled to IC lines in the second wafer where the TIV is located. In this case, the passive side of the

second wafers

200a, 200b, and 200c may be continuously etched on the basis of the structure shown in fig. 12, exposing the metal lines in the TIVs of the

second wafers

200a, 200b, and 200 c.

Step eleven, as shown in fig. 13, a wiring layer 700 is prepared on the inactive side of the

second wafers

200a, 200b and 200c, the wiring layer 700 including metal lines 701, and the metal lines 701 being coupled with the metal lines in the TIV of the second wafer. Specifically, while the passive side of the second wafer is etched in step ten, the insulating dielectric 400 adjacent to the second wafer may also be etched, exposing the metal lines in the TIV 401. The wiring layer 700 may cover the inactive side of the

second wafers

200a, 200b, and 200c, and the insulating medium 400 adjacent to the second wafers.

Illustratively, the wiring layer 700 has electrodes 702 and metal lines 701 formed therein, wherein a portion of the metal lines 701 is coupled to metal lines in the TIVs of the

second wafers

200a, 200b, and 200c, so that the

second wafers

200a, 200b, and 200c can input or output electrical signals through the electrodes 702 coupled thereto. In fig. 13, a part of the metal lines 701 is coupled to the signal lines 303 of the interconnect layer 300, which are coupled to the first wafer 100 only, through metal lines in the TIV401, so that the first wafer 100 is coupled to the electrodes 702 through the signal lines 303 and the metal lines 701, and the first wafer 100 can directly input or output electrical signals through the electrodes 702 coupled thereto.

Example two

The manufacturing method of the 3DIC chip with the F2B structure mainly comprises the following steps:

Step two, as shown in fig. 14, a wiring layer 700 is generated on the surface of the carrier 500. Illustratively, the wiring layer 700 includes a motor 702 and metal lines 701 therein, wherein a surface on which the electrodes 702 are disposed is disposed on a surface of the carrier 500.

And step three, bonding the active surface of the first wafer 100 on the surface of the wiring layer 700. In one possible implementation, the 3DIC chip includes a plurality of first dies, as shown in fig. 15, including a first die 100a and a first crystal 100 b. In this case, as shown in fig. 14, the wiring layer 700 generated in the second step further includes a metal line 703, and in the intermediate structure shown in fig. 15, one end of the metal line 703 is coupled to the first crystal 100a, and the other end is coupled to the first crystal 100b, thereby achieving coupling between the first crystal 100a and the first crystal 100 b.

In one possible implementation, step four may be performed before the interconnection layer is prepared, and the insulating medium 400 is prepared on the surface of the wiring layer 700 in a region except the first wafer 100a and the first wafer 100b to enhance the mechanical strength of the 3DIC chip.

In a 3DIC chip, there is a portion of signal lines 303 in the interconnect layer 300 that are coupled only to the die away from the wiring layer 700. For example, in the 3DIC chip of the F2F structure shown in fig. 13, the first wafer 100 is far from the wiring layer 700, and a part of the signal lines 303 existing in the interconnect layer 300 is coupled only to the first wafer 100 and is not coupled to the second wafer 200.

Similarly, in the intermediate structure shown in fig. 16, the first wafer 100 is disposed close to the wiring layer 700, and the second wafer 200 disposed next will be disposed away from the wiring layer 700. Therefore, a portion of the signal lines 303 in the interconnect layer 300 to be prepared next will be coupled only to the second wafer 200 and not to the first wafer 100. To provide a path for this portion of the signal lines to couple to the wiring layer 700, a TIV401 may also be fabricated in the insulating medium 400 after the insulating medium 400 is fabricated, as shown in fig. 16. The metal lines in the TIV401 are coupled to metal lines 701 in the wiring layer 700 that are not coupled to the first wafer 100a and the first wafer 100 b.

Step five, as shown in fig. 16, the TIV is also included in the first wafer 100a and the first wafer 100b, the metal lines in the TIV of the first wafer 100a are coupled to the IC lines of the first wafer 100a, and the metal lines in the TIV of the first wafer 100b are coupled to the IC lines of the first wafer 100 b. After the insulating dielectric 400 is prepared, the inactive side of the first wafer 100a, the inactive side of the first wafer 100b, and the insulating dielectric 400 may also be etched to expose the metal lines in the respective TIVs.

Step six, as shown in fig. 17, an interconnect layer 300 is prepared on the inactive side of the first wafer 100a and the first wafer 100 b. Illustratively, the interconnection layer 300 may be formed on another carrier, and then the interconnection layer 300 is bonded to the passive surfaces of the first wafer 100a and the first wafer 100b, or SiO may be deposited directly on the passive surfaces of the first wafer 100a and the first wafer 100b₂And based on the SiO obtained₂The signal lines are formed therein by deposition, etching, sputtering, or the like, thereby obtaining the interconnect layer 300.

As shown in fig. 17, a portion of the signal lines 303 in the interconnect layer 300 are coupled to metal lines in the TIVs of the first wafer 100a and the first wafer 100 b. In addition, a portion of the signal lines 303 in the interconnect layer 300 are coupled to metal lines in the TIV401 in the insulating medium 400.

Step seven, as shown in fig. 18, the active surfaces of the

second wafers

200a, 200b, and 200c are bonded on the interconnect layer 300, and the IC lines in the

second wafers

200a, 200b, and 200c may be coupled with the signal lines 303 in the interconnect layer 300. In particular, since the signal lines 303 in the interconnect layer 300 may be coupled to both metal lines in the TIV of the first wafer 100 and metal lines in the TIV of the insulating medium 400, after the second wafer is bonded on the interconnect layer 300, the second wafer may be coupled to both the first wafer 100 through the interconnect layer 300 and the wiring layer 700 through the interconnect layer 300. For example, the

second wafers

200a and 200c of fig. 18 may be coupled to the wiring layer 700 through metal lines in the TIV401 of the interconnect layer 300 and the insulating dielectric 400. As another example, the

second wafers

200a, 200b, and 200c of fig. 18 may all be coupled to metal lines in the TIV of the first wafer 100a and/or the second wafer 100b through the interconnect layer 300.

Step eight, as shown in fig. 19, an insulating dielectric 400 is prepared on the surface of the interconnect layer 300 in the region except the

second wafers

200a, 200b, and 200 c.

Step nine, the inactive surfaces of the

second wafers

200a, 200b, and 200c and the insulating dielectrics 400 adjacent to the

second wafers

200a, 200b, and 200c are polished, thereby preparing the supporting layer 600 on the smooth inactive surfaces of the

second wafers

200a, 200b, and 200c and the insulating dielectrics 400, resulting in the intermediate structure shown in fig. 20.

Step ten, the carrier 500 is removed to expose the electrodes 702 of the wiring layer 700, and the 3DIC chip with the F2B structure shown in fig. 21 is obtained.

In one possible implementation manner, in the mechanism shown in fig. 14, a certain thickness of insulating medium may be further spaced between the electrode 702 and the carrier 500, and in step ten, after the carrier 500 is removed, the insulating medium on the electrode 702 is etched to expose the electrode 702, so that damage to the electrode 702 due to processes such as carrier removal can be reduced.

It can be understood that the manufacturing methods provided in the first and second embodiments can be applied to the manufacturing of single 3DIC chips, and can also be applied to the batch generation of 3DIC chips. When the method is applied to batch production, insulating media can be filled between first wafers belonging to different 3DIC chips and/or between second wafers belonging to different 3DIC chips. Correspondingly, the carrier and the support layer may have larger areas to carry more first wafers and second wafers, and the specific implementation is similar to that of the first embodiment and the second embodiment, and thus, the description thereof is omitted.

Since the first wafer and the second wafer can both ensure a higher yield through screening, the yield of the 3DIC chip obtained in the embodiment of the present application is less affected by the areas of the carrier and the supporting layer, and the manufacturing method provided in the embodiment of the present application is more suitable for batch generation of the 3DIC chip than the W2W process and the D2W process.

Through the above first embodiment and the second embodiment, the specific implementation manner of the manufacturing method provided by the embodiment of the present application in the process of manufacturing the 3DIC chip with the F2F structure and the 3DIC chip with the F2B structure is respectively illustrated as an example. It should be noted that the manufacturing method provided in the embodiments of the present application is not only suitable for manufacturing 3DIC chips comprising two wafers (such as the first wafer and the second wafer) but also suitable for manufacturing 3DIC chips comprising more than two wafers.

For example, on the basis of the intermediate structure shown in fig. 12, it is also possible to continue to prepare an interconnect layer on the passive side of the

second wafers

200a, 200b, and 200c, and bond a third wafer on the surface of the prepared interconnect layer, and the specific process is similar to stacking the interconnect layer 300 and the second wafer 200 on the surface of the first wafer, and thus, the detailed description is omitted. The above process is repeated until a wafer of a target number of layers is obtained, and then the wiring layer 700 is prepared on the surface of the wafer which is finally fixed.

For another example, on the basis of the intermediate structure shown in fig. 19, an interconnect layer may be further prepared on the passive side of the

second wafers

200a, 200b, and 200c, and a third wafer may be bonded on the surface of the prepared interconnect layer, and the specific process is similar to stacking the interconnect layer 300 and the second wafer 200 on the surface of the first wafer, and thus, the detailed description thereof is omitted. The above processes are repeated until a wafer with a target number of layers is obtained, the support layer 600 is prepared on the surface of the wafer fixed at the end, and the carrier 500 is removed.

Based on the same technical concept, the embodiment of the present application further provides a 3DIC chip, and the 3DIC chip may be applied to the manufacturing method provided in any of the above embodiments. Illustratively, the 3DIC chip provided by the embodiments of the present application includes a first wafer, a second wafer, a silicon support layer, and an interconnect layer. Wherein the first surface of the interconnect layer is provided with a first wafer, the second surface of the interconnect layer is provided with a second wafer, the interconnect layer comprises signal lines, and the signal lines are coupled with the first wafer and/or the second wafer; the silicon supporting layer is arranged on the surface of the first wafer or the second wafer and used for improving the mechanical strength of the chip.

Specifically, reference may be made to the 3DIC chip structures shown in fig. 13 and 21. The material of the supporting layer 600 is silicon, that is, the silicon supporting layer 600. The silicon support layer 600 may be a silicon substrate or a silicon deposition layer having a certain thickness. Due to the existence of the silicon supporting layer 600, the mechanical strength of the 3DIC chip is increased, so that the 3DIC chip provided by the embodiment of the application can be suitable for the manufacturing method provided by the above embodiment.

For example, in step eight of the first embodiment, the active surface of the second wafer 200 needs to be bonded to the surface of the interconnect layer 300, so that the mechanical strength of the intermediate structure can support the bonding process due to the presence of the silicon support layer 600. For another example, in the tenth step of the second embodiment, the carrier 500 needs to be removed to expose the electrodes 702 in the wiring layer 700. Since the thicknesses of the first wafer 100, the second wafer 200, the wiring layer 700 and the interconnect layer 300 tend to be small, the thickness of the structure formed by these four layers is small, and the mechanical strength is not high. In this case, the process of removing the carrier 500 risks damaging the above four layers to some extent. In view of this, the addition of the silicon support layer 600 in the 3DIC chip increases the mechanical strength of the overall structure, thereby reducing the risk of damage to the first wafer 100, the second wafer 200, the wiring layer 700 and the interconnect layer 300 by the process of removing the carrier 500.

In one possible implementation, a silicon support layer is disposed on the passive side of the first wafer.

The chip comprises a plurality of first wafers, so that the area of a single first wafer can be reduced, the yield of the first wafer can be improved, and the process cost of the 3DIC chip can be further reduced.

In one possible implementation, the chip further includes a wiring layer disposed on the active surface of the first wafer, the wiring layer including a second metal line, the second metal line of the wiring layer being coupled to the IC line of the first wafer; the first wafer comprises an insulating layer through hole (TIV) and a third metal line penetrating through the TIV, and the IC circuit in the active surface of the first wafer is coupled with the third metal line in the TIV; an interconnect layer is disposed on the passive side of the first wafer, and a third metal line is coupled to the signal line in the interconnect layer.

In one possible implementation, a silicon support layer is disposed on the passive side of the second wafer.

Although the present application has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the application. Accordingly, the specification and figures are merely exemplary of the present application as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the present application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include such modifications and variations.

Claims

A method for manufacturing a 3DIC chip, comprising:

detecting a first die wafer, and screening a first chip in the first die wafer, wherein the first chip is an effective chip in the first die wafer;

preparing an interconnection layer on the surface of the first wafer;

fixing a second wafer on the surface of the interconnection layer; the interconnection layer is provided with a signal line, and the signal line is coupled with the first wafer and/or the second wafer.
The method of claim 1, further comprising, prior to securing a second wafer to the surface of the interconnect layer:

and detecting a second die wafer, and screening effective chips in the second die wafer as the second chips.
The method of claim 1, wherein preparing an interconnect layer on the surface of the first wafer comprises:

generating the interconnection layer on the surface of the carrier;

and fixing the active surface of the first wafer on the surface of the interconnection layer.
The method of claim 3, further comprising, after securing the surface of the interconnect layer to the active surface of the first wafer:

an insulating dielectric is prepared on the surface of the interconnect layer in areas other than the first wafer.
The method of claim 3, further comprising, prior to securing the second wafer to the surface of the interconnect layer:

preparing a support layer on the passive side of the first wafer;

removing the carrier.
The method of claim 3, wherein securing a second wafer to the surface of the interconnect layer comprises:

and fixing the active surface of the second wafer on the surface of the interconnection layer.
The method of claim 6, further comprising, after the surface of the interconnect layer secures the active face of the second wafer:

an insulating dielectric is prepared on the surface of the interconnect layer except for the second wafer.
The method of claim 6, wherein the second wafer comprises an insulating layer via (TIV) and a first metal line through the TIV, the IC circuitry of the second wafer being coupled to the first metal line;

after the surface of the interconnection layer fixes the active surface of the second wafer, the method further comprises the following steps:

etching the passive surface of the second wafer to expose a first metal wire in the TIV of the second wafer;

fabricating a wiring layer on a passive side of the second wafer, the wiring layer including a second metal line coupled to a first metal line in the TIV.
The method of claim 1, further comprising, prior to preparing an interconnect layer on the surface of the first wafer:

preparing a wiring layer on the surface of the carrier, wherein the wiring layer comprises a second metal wire;

fixing an active surface of the first wafer on the surface of the wiring layer, wherein the second metal wire of the wiring layer is coupled with the IC circuit of the first wafer;

the first wafer comprises an insulating layer via (TIV) and a third metal line passing through the TIV, and the IC circuit of the first wafer is coupled with the third metal line in the TIV;

etching the passive surface of the first wafer and exposing a third metal wire in the TIV of the first wafer;

preparing an interconnection layer on the surface of the first wafer, comprising:

the interconnection layer is prepared on the passive side of the first wafer, and the third metal line is coupled with a signal line in the interconnection layer.
The method of claim 9, further comprising, prior to preparing an interconnect layer on the surface of the first wafer: preparing an insulating medium on the surface of the wiring layer in a region other than the first wafer.
The method of claim 9, wherein securing a second wafer to the surface of the interconnect layer comprises:

and fixing the active surface of the second wafer on the surface of the interconnection layer.
The method of claim 11, further comprising, after securing a second wafer to a surface of the interconnect layer:

and preparing an insulating medium on the surface of the interconnection layer except for the second wafer.
The method of claim 9, further comprising, after securing a second wafer to the surface of the interconnect layer:

preparing a supporting layer on the passive surface of the second wafer;

removing the carrier.
A3 DIC chip, comprising: a first wafer, a second wafer, a silicon support layer and an interconnect layer;

a first surface of the interconnect layer is provided with the first wafer, a second surface of the interconnect layer is provided with the second wafer, the interconnect layer includes signal lines, and the signal lines are coupled with the first wafer and/or the second wafer;

the silicon supporting layer is arranged on the surface of the first wafer or the second wafer and used for improving the mechanical strength of the chip.
The chip of claim 14, wherein the first die is a valid die obtained by inspection of a first die wafer, and/or wherein the second die is a valid die obtained by inspection of a second die wafer.
The die of claim 14, wherein the first surface of the interconnect layer holds the active face of the first wafer.
The die of claim 16 wherein an area of the first surface other than the first wafer is provided with an insulating medium.
The die of claim 16, wherein the support layer is disposed on a passive side of the first wafer.
The die of claim 16 wherein the second surface of the interconnect layer holds the active face of the second wafer.
The chip of claim 19, wherein an area of the second surface other than the second wafer is provided with an insulating medium.
The chip of claim 19, in which the second wafer comprises an insulating layer via (TIV), and a first metal line that passes through the TIV, the IC circuitry in the active face of the second wafer being coupled with the first metal line in the TIV;

the chip further comprises a wiring layer arranged on the passive surface of the second wafer;

the routing layer includes second metal lines, the second metal lines of the routing layer coupled with the first metal lines in the TIV of the second wafer.
The die of claim 16, wherein the die comprises a plurality of first wafers; the interconnect layer further includes lateral metal lines respectively coupled with at least two of the plurality of first dies.
The chip of claim 14, further comprising a wiring layer disposed on the active surface of the first wafer, the wiring layer comprising second metal lines, the second metal lines of the wiring layer being coupled with the IC lines of the first wafer;

the first wafer comprises an insulating layer through-hole (TIV) and a third metal line penetrating through the TIV, and an IC circuit in an active surface of the first wafer is coupled with the third metal line in the TIV;

the interconnect layer is disposed on the passive side of the first wafer, and the third metal lines are coupled to signal lines in the interconnect layer.
The chip according to claim 23, wherein an insulating medium is provided on a surface of the wiring layer in a region other than the first wafer.
The die of claim 23 wherein the active face of the second wafer is secured to the second surface of the interconnect layer.
The die of claim 25 wherein an insulating medium is disposed on the second surface in areas other than the second wafer.
The die of claim 23, wherein the support layer is disposed on a passive side of the second wafer.
The chip of claim 23, wherein the chip comprises a plurality of first wafers; the routing layer further includes fourth metal lines respectively coupled to at least two of the plurality of first dies.
The chip of claim 14, wherein the silicon support layer is a silicon substrate bonded to a surface of the first or second wafer; or the silicon supporting layer is a silicon deposition layer, and the silicon supporting layer is deposited on the surface of the first wafer or the second wafer.