TWI621228B - Semiconductor package and method for forming the same - Google Patents

Semiconductor package and method for forming the same Download PDF

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Publication number
TWI621228B
TWI621228B TW105121277A TW105121277A TWI621228B TW I621228 B TWI621228 B TW I621228B TW 105121277 A TW105121277 A TW 105121277A TW 105121277 A TW105121277 A TW 105121277A TW I621228 B TWI621228 B TW I621228B
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Taiwan
Prior art keywords
level
die
rdl
package
oxide
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TW105121277A
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Chinese (zh)
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TW201712824A (en
Inventor
冠宇 賴
軍 翟
胡坤忠
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蘋果公司
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Priority to US201562208544P priority Critical
Priority to US62/208,544 priority
Priority to US14/935,310 priority patent/US9559081B1/en
Priority to US14/935,310 priority
Application filed by 蘋果公司 filed Critical 蘋果公司
Publication of TW201712824A publication Critical patent/TW201712824A/en
Application granted granted Critical
Publication of TWI621228B publication Critical patent/TWI621228B/en

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Abstract

本發明描述封裝及3D晶粒堆疊程序。在一實施例中,一種封裝包括:一第二層級晶粒,其混合結合至一第一封裝層級,該第一封裝層級包括囊封於一氧化物層中之一第一層級晶粒及延伸穿過該氧化物層之複數個氧化物穿孔(TOV)。在一實施例中,該等TOV及該第一層級晶粒具有約20微米或更小的高度。 The present invention describes packaging and 3D die stacking procedures. In one embodiment, a package includes a second-level die that is combined and combined with a first packaging level, the first packaging level including a first-level die encapsulated in an oxide layer and an extension A plurality of oxide vias (TOV) pass through the oxide layer. In one embodiment, the TOVs and the first-level grains have a height of about 20 microns or less.

Description

半導體封裝及用於形成該半導體封裝的方法Semiconductor package and method for forming the same 相關申請案的交叉參考Cross-reference to related applications

本申請案主張2015年8月21日申請的美國臨時申請案第62/208,544號之優先權,該申請案以引用的方式併入本文中。 This application claims priority from US Provisional Application No. 62 / 208,544, filed on August 21, 2015, which is incorporated herein by reference.

本文中所描述之實施例係關於半導體封裝。更特定而言,實施例係關於包括3D堆疊晶粒之封裝。 The embodiments described herein relate to semiconductor packages. More specifically, the embodiments relate to packages including 3D stacked dies.

對於諸如行動電話、個人數位助理(PDA)、數位攝影機、攜帶型播放器、遊戲以及其他行動器件之攜帶型及行動電子器件的當前市場需求要求將更多效能及特徵整合至愈來愈小之空間中。另外,雖然半導體晶粒封裝之外觀尺寸(例如,厚度)及佔據面積(例如,面積)減小,但輸入/輸出(I/O)襯墊的數目增大。 The current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, games, and other mobile devices requires more performance and features to be integrated into smaller and smaller In space. In addition, although the external dimensions (eg, thickness) and occupied area (eg, area) of the semiconductor die package are reduced, the number of input / output (I / O) pads is increased.

諸如系統級封裝(SiP)及堆疊式封裝(PoP)之各種多晶粒封裝解決方案已變得愈加風行以滿足對於較高晶粒/組件密度器件之需求。在SiP中,若干不同晶粒圍封於封裝內作為單一模組。因此,SiP可執行電子系統之所有或大部分功能。 Various multi-die packaging solutions such as system-in-package (SiP) and stacked-on-package (PoP) have become increasingly popular to meet the demand for higher die / component density devices. In SiP, several different dies are enclosed in a package as a single module. Therefore, SiP can perform all or most of the functions of an electronic system.

諸如晶圓上晶片(CoW)之3D堆疊實施包括將晶粒安裝至支撐晶圓上,後續接著單體化堆疊晶粒SiP。諸如晶圓至晶圓(W2W)之3D堆疊實施包括將頂部晶圓安裝至底部晶圓上,後續接著單體化堆疊晶粒SiP。該等習知3D堆疊實施兩者皆要求封裝層級層中之一者(例如,經 安裝晶粒或晶圓內的晶粒)較大或等於另一層。舉例而言,CoW可涉及支撐晶圓之單體化面積大於安裝於支撐晶圓上的晶粒,而W2W可涉及單體化晶圓之相等面積。 3D stacking implementations such as wafer-on-wafer (CoW) include mounting the die on a supporting wafer, followed by singulation of the stacked die SiP. 3D stacking implementations such as wafer-to-wafer (W2W) include mounting the top wafer on the bottom wafer, followed by singulation of the stacked die SiP. Both of these conventional 3D stack implementations require one of the packaging levels (e.g., The mounting die or die in the wafer) is larger or equal to another layer. For example, CoW may involve a singulated area of a support wafer larger than the die mounted on the support wafer, and W2W may involve an equal area of a singulated wafer.

實施例描述半導體晶粒封裝。在一項實施例中,一封裝包括一第一層級重佈層(RDL)及位於該RDL上之一第一封裝層級的一前側。該第一封裝層級包括囊封於該RDL上之一間隙填充氧化物層內的一或多個第一層級晶粒。複數個氧化物穿孔(TOV)延伸穿過該間隙填充氧化物層。在一實施例中,該等TOV及該第一層級晶粒具有約20微米或更小的高度。一第二層級晶粒包括於一第二封裝層級中,且該第二層級晶粒混合結合至該第一封裝層級之一背側,其中該混合結合包括經直接結合之氧化物對氧化物表面及經直接結合之金屬對金屬表面。該第二層級晶粒可囊封於(例如)該第一封裝層級上的模製化合物中。在一實施例中,該RDL形成於該第一層級晶粒之一前側及該複數個TOV上且與其等電接觸。 The embodiment describes a semiconductor die package. In one embodiment, a package includes a first-level redistribution layer (RDL) and a front side of a first packaging level on the RDL. The first encapsulation level includes one or more first-level grains encapsulated in a gap-filled oxide layer on the RDL. A plurality of oxide vias (TOV) extend through the gap-fill oxide layer. In one embodiment, the TOVs and the first-level grains have a height of about 20 microns or less. A second-level die is included in a second encapsulation level, and the second-level die is mixed and bonded to one back side of the first encapsulation level, wherein the mixed bonding includes a directly bonded oxide-to-oxide surface And directly bonded metal-to-metal surfaces. The second level die may be encapsulated in, for example, a molding compound on the first packaging level. In one embodiment, the RDL is formed on a front side of the first-level die and on the plurality of TOVs and is in electrical contact therewith.

在一實施例中,該第一封裝層級包括位於該第一層級晶粒及該間隙填充氧化物層之一背側上的一第一封裝層級RDL。該第二層級晶粒可混合結合至該第一封裝層級RDL之一平坦化後表面。舉例而言,該第一封裝層級RDL可包括一氧化物介電層及金屬重佈線,且該第二層級晶粒混合結合至該氧化物介電層及該金屬重佈線。該第一層級晶粒可包括複數個矽穿孔(TSV),其中該第一封裝層級RDL形成於該複數個TSV上且與其等電接觸。 In one embodiment, the first packaging level includes a first packaging level RDL on a backside of the first level die and the gap-fill oxide layer. The second-level die may be mixed and bonded to one of the first packaging-level RDL planarized surfaces. For example, the first package-level RDL may include an oxide dielectric layer and a metal redistribution, and the second-level die may be mixed and bonded to the oxide dielectric layer and the metal redistribution. The first-level die may include a plurality of TSVs, wherein the first package-level RDL is formed on the plurality of TSVs and is in electrical contact therewith.

根據一些實施例,該等TOV可配置成列。舉例而言,該複數個TOV可包括一第一列TOV及一第二列TOV。在一特定配置中,該第一列TOV及該第二列TOV側向地鄰近於該第一層級晶粒之一第一對側向對立側。一第二個第一層級晶粒及一第三個第一層級晶粒可經定位成 側向地鄰近於該第一層級晶粒之一第二對側向對立側。在此配置中,該RDL可形成於該第一層級晶粒之一前側、該第二個第一層級晶粒之一前側、該第三個第一層級晶粒之一前側、該第一列TOV及該第二列TOV上,且與其等電接觸。該第一層級晶粒可另外包括(例如)具有約10微米或更小之最大寬度的複數個TSV。 According to some embodiments, the TOVs may be configured in columns. For example, the plurality of TOVs may include a first column of TOVs and a second column of TOVs. In a specific configuration, the first row of TOVs and the second row of TOVs are laterally adjacent to a first pair of laterally opposite sides of one of the first-level grains. A second first-level grain and a third first-level grain can be positioned as A second pair of laterally opposite sides that are laterally adjacent to one of the first-level grains. In this configuration, the RDL may be formed on the front side of one of the first level grains, on the front side of the second first level grain, on the front side of one of the third first level grains, and on the first column. TOV and the second row of TOV are in electrical contact with it. The first-level grains may additionally include, for example, a plurality of TSVs having a maximum width of about 10 microns or less.

在一實施例中,一封裝包括一RDL及位於該RDL之一背側上的一第一封裝層級之一前側。一第一層級晶粒囊封於該RDL之該背側上的一間隙填充氧化物層中。一第一列TOV及一第二列TOV自該RDL之該背側凸起,且該第一層級晶粒經定位成側向地介於該第一列TOV及該第二列TOV之間。複數個第二層級晶粒混合結合至該第一封裝層級之一背側,具有直接結合氧化物對氧化物表面及直接結合金屬對金屬表面。 In one embodiment, a package includes an RDL and a front side of a first package level on a back side of the RDL. A first-level grain is encapsulated in a gap-filled oxide layer on the backside of the RDL. A first column of TOVs and a second column of TOVs protrude from the backside of the RDL, and the first-level grains are positioned laterally between the first column of TOVs and the second column of TOVs. A plurality of second-level crystal grains are mixed and bonded to one back side of the first packaging level, and have a direct-bonded oxide-to-oxide surface and a direct-bonded metal-to-metal surface.

該第一封裝層級可另外包括位於該第一層級晶粒及該間隙填充氧化物層之一背側上的一第一封裝層級RDL。舉例而言,該第一封裝層級RDL可包括一氧化物介電層及一金屬重佈線,且該第二層級晶粒混合結合至該氧化物介電層及該金屬重佈線。 The first packaging level may further include a first packaging level RDL on a backside of the first level die and the gap-fill oxide layer. For example, the first package-level RDL may include an oxide dielectric layer and a metal redistribution, and the second-level die may be mixed and bonded to the oxide dielectric layer and the metal redistribution.

該第一封裝層級可另外包括側向地鄰近於該第一層級晶粒之對立側的一第二個第一層級晶粒及一第三個第一層級晶粒。該第一層級晶粒、第二個第一層級晶粒及第三個第一層級晶粒可全部位於該RDL上,且與其電接觸。在一實施例中,該第一層級晶粒係矩形的,該第一列TOV及該第二列TOV側向地鄰近於該第一層級晶粒之一第一對側向對立側,且該第二個第一層級晶粒及該第三個第一層級晶粒側向地鄰近於該第一層級晶粒之一第二對側向對立側。根據實施例,該第一層級晶粒、該第一列TOV及該第二列TOV可全部具有20微米或更小之高度。根據實施例,複數個TSV可位於該第一層級晶粒內,其中每一TSV具有10微米或更小的最大寬度。 The first package level may further include a second first level die and a third first level die laterally adjacent to the opposite side of the first level die. The first-level crystal grain, the second first-level crystal grain, and the third first-level crystal grain may all be located on the RDL and be in electrical contact therewith. In an embodiment, the first-level grains are rectangular, the first row of TOVs and the second row of TOVs are laterally adjacent to a first pair of laterally opposite sides of the first-level grains, and the The second first-level grain and the third first-level grain are laterally adjacent to a second pair of laterally opposite sides of one of the first-level grains. According to an embodiment, the first-level die, the first-row TOV, and the second-row TOV may all have a height of 20 microns or less. According to an embodiment, a plurality of TSVs may be located within the first level die, where each TSV has a maximum width of 10 microns or less.

在一實施例中,一種形成一封裝之方法包括:將一第一封裝層級形成於一載體基板上,該第一封裝層級包括囊封於一間隙填充氧化物層中之一第一層級晶粒,及複數個氧化物穿孔(TOV)。該等TOV可具有約20微米或更小的高度。將一第二層級晶粒混合結合至該第一封裝層級,具有直接結合氧化物對氧化物表面及金屬對金屬表面。將該第二層級晶粒囊封於該第一封裝層級之一背側上。移除該載體基板,且將一RDL形成於該第一封裝層級之一前側上。 In one embodiment, a method for forming a package includes: forming a first package level on a carrier substrate, the first package level including a first level die encapsulated in a gap-filled oxide layer , And a plurality of oxide perforations (TOV). The TOVs may have a height of about 20 microns or less. A second-level die is mixed and bonded to the first packaging level, and has a direct-bonded oxide-to-oxide surface and a metal-to-metal surface. The second-level die is encapsulated on a backside of one of the first packaging levels. The carrier substrate is removed, and an RDL is formed on a front side of the first package level.

在一實施例中,形成該封裝之該方法另外包括:將該第一層級晶粒附接至該載體基板;將該間隙填充氧化物層沈積於該第一層級晶粒上方;將該間隙填充氧化物層平坦化;及將該複數個TOV形成於該間隙填充氧化物層中。在一實施例中,該第一層級晶粒被研磨以在將該第一層級晶粒附接至該載體基板之後且在將該間隙填充氧化物層沈積於該第一層級晶粒上方之前減小該第一層級晶粒之厚度。在一實施例中,將一第一層級RDL形成於該平坦化間隙填充氧化物層及第一層級晶粒上,且將該第一層級RDL平坦化,且將該第二層級晶粒混合結合至該平坦化第一層級RDL。 In one embodiment, the method of forming the package further includes: attaching the first-level die to the carrier substrate; depositing the gap-fill oxide layer over the first-level die; and filling the gap Planarizing the oxide layer; and forming the plurality of TOVs in the gap-fill oxide layer. In one embodiment, the first-level grains are ground to reduce the thickness of the first-level grains after attaching the first-level grains to the carrier substrate and before depositing the gap-fill oxide layer over the first-level grains. The thickness of the first-level crystal grains is small. In one embodiment, a first-level RDL is formed on the planarized gap-fill oxide layer and the first-level grains, and the first-level RDL is planarized, and the second-level grains are mixed and combined. Until this, the first-level RDL is planarized.

100‧‧‧封裝100‧‧‧ package

101‧‧‧第一載體基板101‧‧‧First carrier substrate

102‧‧‧脫模層102‧‧‧Release layer

105A‧‧‧側向對立側105A‧‧‧ side opposite

105B‧‧‧側向對立側105B‧‧‧ side opposite

108A‧‧‧側向對立側108A‧‧‧ side opposite

108B‧‧‧側向對立側108B‧‧‧ side opposite

110‧‧‧第一層級晶粒110‧‧‧ first-level grain

110A‧‧‧第一層級晶粒110A‧‧‧First-level grain

110B‧‧‧第二個第一層級晶粒110B‧‧‧Second first level grain

110C‧‧‧第三個第一層級晶粒110C‧‧‧Third first level grain

111‧‧‧前側111‧‧‧ front side

114‧‧‧基底矽基板114‧‧‧ base silicon substrate

115‧‧‧背側115‧‧‧ dorsal side

116‧‧‧頂部磊晶矽層116‧‧‧Top epitaxial silicon layer

117‧‧‧基板117‧‧‧ substrate

118‧‧‧互連層118‧‧‧Interconnection Layer

119‧‧‧盲介層孔119‧‧‧ blind via hole

120‧‧‧矽穿孔120‧‧‧ Silicon Via

121‧‧‧主動器件121‧‧‧active device

122‧‧‧氧化物絕緣層122‧‧‧oxide insulating layer

123‧‧‧曝露表面123‧‧‧ exposed surface

124‧‧‧介電層124‧‧‧ Dielectric layer

126‧‧‧金屬層126‧‧‧metal layer

127‧‧‧介層孔127‧‧‧Interstitial hole

128A‧‧‧焊盤128A‧‧‧pad

128B‧‧‧焊盤128B‧‧‧pad

130‧‧‧間隙填充氧化物層130‧‧‧ gap-fill oxide layer

131‧‧‧後表面131‧‧‧ rear surface

134‧‧‧氧化物穿孔(TOV) 134‧‧‧TOV

135‧‧‧表面135‧‧‧ surface

136A‧‧‧第一列TOV 136A‧‧‧TOV

136B‧‧‧第二列TOV 136B‧‧‧The second column TOV

150‧‧‧第一封裝層級150‧‧‧first package level

150A‧‧‧第一封裝層級150A‧‧‧first package level

150B‧‧‧第一封裝層級150B‧‧‧first package level

160‧‧‧第一層級RDL 160‧‧‧First level RDL

162‧‧‧金屬重佈線162‧‧‧metal heavy wiring

164‧‧‧絕緣層164‧‧‧Insulation

165‧‧‧背側165‧‧‧ dorsal side

165B‧‧‧背側165B‧‧‧Back side

170A‧‧‧前側170A‧‧‧Front

203‧‧‧鄰近邊緣203‧‧‧ near the edge

210‧‧‧第二層級晶粒210‧‧‧Second-level grain

210A‧‧‧第一個第二層級晶粒210A‧‧‧First second-level grain

210B‧‧‧第二個第二層級晶粒210B‧‧‧Second second-level grain

211‧‧‧前表面/前側211‧‧‧front / front

215‧‧‧背側215‧‧‧ dorsal side

240‧‧‧第二層級模製化合物240‧‧‧Second level molding compound

250‧‧‧第二封裝層級250‧‧‧Second package level

260‧‧‧堆積結構260‧‧‧ stacked structure

262‧‧‧金屬層262‧‧‧metal layer

264‧‧‧絕緣層264‧‧‧Insulation

300‧‧‧重佈層(RDL) 300‧‧‧ Heavy Distribution Layer (RDL)

302‧‧‧重佈線302‧‧‧Re-wiring

304‧‧‧介電層304‧‧‧ Dielectric layer

311‧‧‧前側311‧‧‧front

315‧‧‧背側315‧‧‧ dorsal side

350‧‧‧導電凸塊350‧‧‧Conductive bump

1010‧‧‧步驟1010‧‧‧step

1012‧‧‧步驟1012‧‧‧step

1014‧‧‧步驟1014‧‧‧step

1016‧‧‧步驟1016‧‧‧step

1018‧‧‧步驟1018‧‧‧step

圖1為說明根據一實施例的形成封裝之方法的流程圖。 FIG. 1 is a flowchart illustrating a method of forming a package according to an embodiment.

圖2為根據一實施例的包括盲介層孔之第一層級晶粒之示意性橫截面側視圖說明。 FIG. 2 is a schematic cross-sectional side view illustration of a first level die including a blind via hole according to an embodiment.

圖3為根據一實施例的附接至載體基板之第一層級晶粒之橫截面側視圖說明。 3 is a cross-sectional side view illustration of a first-level die attached to a carrier substrate according to an embodiment.

圖4為根據一實施例的薄化之第一層級晶粒之橫截面側視圖說明。 FIG. 4 is a cross-sectional side view of a thinned first-level grain according to an embodiment.

圖5為根據一實施例的形成於薄化之第一層級晶粒上方之間隙填充氧化物層的橫截面側視圖說明。 5 is a cross-sectional side view illustration of a gap-fill oxide layer formed over a thinned first-level die according to an embodiment.

圖6為根據一實施例的包括氧化物穿孔之平坦化間隙填充氧化物層的橫截面側視圖說明。 FIG. 6 is a cross-sectional side view illustration of a planarized gap-fill oxide layer including oxide perforations according to an embodiment.

圖7為根據一實施例的形成於包括氧化物穿孔之平坦化間隙填充氧化物層上方之第一層級重佈層的橫截面側視圖說明。 7 is a cross-sectional side view illustration of a first-level redistribution layer formed over a planarized gap-fill oxide layer including oxide perforations according to an embodiment.

圖8為根據一實施例的包括平坦化第一層級重佈層之第一封裝層級的橫截面側視圖說明。 8 is a cross-sectional side view illustration of a first package level including a planarized first-level redistribution layer according to an embodiment.

圖9為根據一實施例的包括混合結合至第一封裝層級之第二層級晶粒之近視圖的橫截面側視圖說明。 FIG. 9 is a cross-sectional side view illustrating a close-up view of a second level die including hybrid bonding to a first package level according to an embodiment.

圖10為根據一實施例的位於第一封裝層級上之經囊封第二層級晶粒的橫截面側視圖說明。 10 is a cross-sectional side view illustration of an encapsulated second-level die on a first packaging level according to an embodiment.

圖11為根據一實施例的包括混合結合之第二層級晶粒之封裝的橫截面側視圖說明。 FIG. 11 is a cross-sectional side view illustration of a package including a hybrid bonded second-level die according to an embodiment.

圖12為根據一實施例的包括薄化之第二封裝層級之封裝的橫截面側視圖說明。 12 is a cross-sectional side view illustration of a package including a thinned second package level according to an embodiment.

圖13為根據一實施例的包括堆疊晶粒、氧化物穿孔及矽穿孔之封裝的示意性仰視圖說明。 13 is a schematic bottom view illustration of a package including stacked dies, oxide vias, and through silicon vias according to an embodiment.

圖14為說明根據一實施例的形成封裝之方法的流程圖。 FIG. 14 is a flowchart illustrating a method of forming a package according to an embodiment.

圖15A至圖15D為根據一實施例的形成具有兩個以上封裝層級之封裝之方法的橫截面側視圖說明。 15A to 15D are cross-sectional side views illustrating a method of forming a package having more than two packaging levels according to an embodiment.

圖16為根據一實施例的說明形成封裝之方法的流程圖。 FIG. 16 is a flowchart illustrating a method of forming a package according to an embodiment.

圖17A至圖17D為根據一實施例的形成封裝之方法的橫截面側視圖說明。 17A to 17D are cross-sectional side views illustrating a method of forming a package according to an embodiment.

圖17E為根據一實施例的具有兩個以上封裝層級之封裝的橫截面側視圖說明。 17E is a cross-sectional side view illustration of a package having more than two packaging levels according to an embodiment.

圖18為根據一實施例的晶粒堆疊配置之示意性仰視圖說明及一列氧化物穿孔之近距透視圖。 18 is a schematic bottom view of a die stack configuration and a close-up perspective view of a row of oxide perforations according to an embodiment.

圖19A為根據一實施例的沿圖18中之線AA截得之封裝的橫截面側視圖說明。 FIG. 19A is a cross-sectional side view illustration of a package taken along line AA in FIG. 18 according to an embodiment.

圖19B為根據一實施例的沿圖18中之線BB截得之封裝的橫截面側視圖說明。 FIG. 19B is a cross-sectional side view illustration of the package taken along line BB in FIG. 18 according to an embodiment.

實施例描述半導體封裝及異質堆疊晶粒之封裝程序。根據實施例,可在任何封裝層級中獨立於晶粒面積或厚度達成異質晶粒整合之靈活性。在此態樣中,SiP結構內的系統單晶片(SoC)晶粒分割可為可能的,其中可在整個封裝中自由隔離智慧財產權(IP)核心。 The embodiment describes a packaging process for a semiconductor package and a hetero-stacked die. According to embodiments, the flexibility of heterogeneous die integration can be achieved independently of die area or thickness in any package level. In this aspect, system-on-chip (SoC) die segmentation within the SiP structure may be possible, where the intellectual property (IP) core can be freely isolated throughout the package.

在各種實施例中,參考諸圖進行描述。然而,某些實施例可在沒有此等特定細節中之一或多者的情況下或與其他已知方法及組態組合而實踐。在以下描述中,闡述諸多特定細節(諸如,特定組態、尺寸及程序等)以便提供對實施例之充分理解。在其他情況下,尚未以特定細節描述熟知之半導體製程及製造技術以免不必要地混淆實施例。貫穿本說明書參考「一項實施例」意謂結合實施例描述之特定特徵、結構、組態或特性包括於至少一項實施例中。因此,在貫穿本說明書之各種地方出現的片語「在一項實施例中」未必係指相同實施例。此外,可在一或多項實施例中以任何合適的方式組合特定特徵、結構、組態或特性。 In various embodiments, descriptions are made with reference to the drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions, procedures, etc., to provide a thorough understanding of the embodiments. In other cases, well-known semiconductor processes and manufacturing techniques have not been described in specific details to avoid unnecessarily obscuring the embodiments. Reference throughout this specification to "one embodiment" means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the appearance of the phrase "in one embodiment" in various places throughout this specification does not necessarily refer to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

如本文中所使用之術語「頂部」、「底部」、「前」、「後」、「在…之上」、「至」、「之間」及「在…上」可指一個層相對於其他層之相對位置。在另一層「之上」或「上」或結合「至」另一層或與另一層「接觸」之一個層可直接地與另一層接觸或可具有一或多個介入層。在若干層「之間」的一個層可與該等層直接接觸或可具有一或多個介入層。 The terms "top", "bottom", "front", "back", "above", "to", "between" and "on" as used herein may refer to a layer relative to Relative position of other layers. A layer that is "above" or "on" or in combination with "to" another layer or "contacting" another layer may be in direct contact with another layer or may have one or more intervening layers. A layer "between" several layers may be in direct contact with the layers or may have one or more intervening layers.

在一項實施例中,封裝包括第一封裝層級,其包括囊封於間隙 填充氧化物層內之一或多個第一層級晶粒及橫跨於該一或多個第一層級晶粒及該間隙填充氧化物層上的第一層級RDL。第二層級晶粒之平坦化前表面經混合結合至第一層級RDL之平坦化表面,該平坦化表面可包括共面的金屬與氧化物表面。根據實施例,混合結合包括位於第二層級晶粒與第一層級RDL之間的氧化物對氧化物結合及金屬對金屬結合。在此態樣中,可藉由排除用於結合之介面材料來實現顯著的封裝z高度節省。此外,混合結合可允許高連接密度。 In one embodiment, the package includes a first package level including an encapsulation in a gap One or more first-level grains in the filled oxide layer and a first-level RDL spanning the one or more first-level grains and the gap-fill oxide layer. The planarized front surface of the second-level grains is mixed and combined with the planarized surface of the first-level RDL, and the planarized surface may include coplanar metal and oxide surfaces. According to an embodiment, the hybrid bonding includes an oxide-to-oxide bonding and a metal-to-metal bonding located between the second-level grains and the first-level RDL. In this aspect, significant packaging z-height savings can be achieved by excluding interface materials for bonding. In addition, hybrid bonding can allow high connection densities.

根據實施例,可視情況穿過一或多個第一層級晶粒形成矽穿孔(TSV),且可穿過將該一或多個第一層級晶粒囊封於第一封裝層級內的間隙填充氧化物層形成氧化物穿孔(TOV)。根據實施例,第一層級晶粒、間隙填充氧化物層及TOV的厚度可減少至約20μm或更少,諸如2μm至20μm或5μm至10μm。以此方式,不僅實現z高度節省,還有可能形成窄的TSV及TOV而不使高度成為對TSV及TOV之最小寬度之實際限制因素。在此態樣中,在穿過第一封裝層級的幾乎任何位置處,至第二層級封裝內之第二層級晶粒的直接及短的通信路徑為可能的。此可另外允許歸因於佈線長度之最小佈線損失,及任何封裝層級中之晶粒對電力分配的完全存取。根據實施例,TSV及/或TOV之組合及混合結合允許異質晶粒整合中的顯著靈活性。 According to an embodiment, TSVs may be formed through one or more first-level dies as appropriate, and may be filled through a gap filling that encapsulates the one or more first-level dies in the first packaging level. The oxide layer forms an oxide via (TOV). According to an embodiment, the thickness of the first-level crystal grains, the gap-fill oxide layer, and the TOV may be reduced to about 20 μm or less, such as 2 μm to 20 μm or 5 μm to 10 μm. In this way, not only z-height savings are achieved, it is also possible to form narrow TSVs and TOVs without making height a practical limiting factor on the minimum widths of TSVs and TOVs. In this aspect, a direct and short communication path to the second-level die within the second-level package is possible at almost any position through the first-level package level. This may additionally allow minimal wiring loss due to wiring length, and full access to power distribution by the die in any package level. According to embodiments, the combination and hybrid combination of TSV and / or TOV allows significant flexibility in heterogeneous grain integration.

在一項態樣中,實施例描述SiP結構(例如,3D記憶體封裝)內的系統單晶片(SoC)晶粒分割及/或晶粒分裂,其中可遍及封裝自由隔離諸如CPU、GPU、IO、DRAM、SRAM、快取記憶體、ESD、功率管理及整合式被動元件之IP核心,同時亦減少封裝之總z高度。不同IP核心可經隔離至封裝內的不同晶粒中。另外,晶粒分割可允許不同程序節點整合至單獨晶粒中。同樣,可在不同程序節點處處理不同晶粒中之不同IP核心。借助於實例,中央處理單元(CPU)及一般處理單元(GPU)可為在不同程序節點處進行處理之單獨晶粒。可藉由在任何地 方存取電力供應線之能力促進晶粒分割之靈活性。晶粒分割的靈活性亦可減輕整個系統的熱約束。 In one aspect, the embodiments describe system-on-chip (SoC) die segmentation and / or die splitting within a SiP structure (e.g., a 3D memory package), where isolation such as CPU, GPU, IO, etc. is free throughout the package , DRAM, SRAM, cache memory, ESD, power management and integrated passive IP cores, while also reducing the total z-height of the package. Different IP cores can be isolated into different dies in the package. In addition, die segmentation allows different program nodes to be integrated into separate die. Similarly, different IP cores in different dies can be processed at different program nodes. By way of example, the central processing unit (CPU) and general processing unit (GPU) can be separate dies that process at different program nodes. Can be used anywhere The ability of the party to access the power supply line promotes the flexibility of the die division. The flexibility of the die segmentation can also ease the thermal constraints of the entire system.

在一實施例中,第一層級晶粒為包括得益於減少之佈線密度及短佈線路徑的主動IP核心之主動晶粒,諸如中央處理單元/一般處理單元(CPU/GPU)晶粒。在一實施例中,封裝為3D記憶體封裝,諸如寬的I/O DRAM封裝。在一實施例中,一或多個第二層級晶粒為記憶體晶粒,諸如(但不限於)DRAM。在一實施例中,諸如第二個第一層級晶粒及第三個第一層級晶粒的額外第一層級晶粒為經分割之IP核心,諸如(但不限於)經分裂I/O晶粒。 In one embodiment, the first-level die is an active die including an active IP core that benefits from reduced wiring density and short routing paths, such as a central processing unit / general processing unit (CPU / GPU) die. In one embodiment, the package is a 3D memory package, such as a wide I / O DRAM package. In one embodiment, the one or more second-level dies are memory dies, such as (but not limited to) DRAM. In one embodiment, the additional first-level dies such as the second first-level dies and the third first-level dies are the divided IP cores, such as (but not limited to) split I / O crystals grain.

根據實施例,第一層級晶粒及TOV之厚度或高度為約20μm或更小,諸如5至10μm。以此方式,不僅實現z高度節省,還有可能形成窄的TOV。在一實施例中,例示性TOV為約10μm寬,但可形成較窄或較寬TOV,例如,多半位於10:1(高度:直徑)縱橫比內。在一實施例中,例示性TOV為約2μm寬。在此態樣中,第一層級晶粒之厚度減少允許形成相比於諸如傳統內插件中之彼等TSV的共同TSV具有實質上較小寬度(或直徑)的TOV。 According to an embodiment, the thickness or height of the first-level crystal grains and the TOV is about 20 μm or less, such as 5 to 10 μm. In this way, not only z-height savings are achieved, but narrow TOVs are also possible. In an embodiment, the exemplary TOV is about 10 μm wide, but a narrower or wider TOV can be formed, for example, most likely within a 10: 1 (height: diameter) aspect ratio. In one embodiment, the exemplary TOV is about 2 μm wide. In this aspect, the reduction in the thickness of the first-level grains allows the formation of a TOV having a substantially smaller width (or diameter) than a common TSV such as those in a conventional interposer.

根據實施例,TOV及視需要存在之TSV可用以在封裝層級之間提供短的垂直通信路徑。根據實施例,TOV亦可配置成列,以提供自第二層級晶粒至第一層級晶粒(例如,主動晶粒)之邊緣(例如,每一邊緣)的短佈線路徑,其亦可允許高佈線密度,而佈線擁擠(routing jam)得以減輕。在例示性實施例中,一列TOV中的TOV間的間距可具有為1:1的TOV對TOV間氧化物的間隙比。借助於實例,例示性的10μm寬TOV具有20μm間距(在x及/或y維度上)。此可對應於50×50/mm2(或2500/mm2)的密度。實施例不限於此等例示性間隙比、TOV間距及TOV密度。舉例而言,TOV間氧化物的量可增大至超過1:1間隙比。亦可實施較大間距,諸如40μm至70μm。另外,可製造較窄TOV。 在另一例示性實施例中,TOV為2μm寬。假定1:1間隙比,此可對應於4μm之間距及250×250/mm2(或62500/mm2)之密度。 According to an embodiment, the TOV and, if necessary, the TSV can be used to provide a short vertical communication path between the packaging levels. According to an embodiment, the TOVs may also be configured in columns to provide short routing paths from the second-level die to the edges (eg, each edge) of the first-level die (e.g., active die), which may also allow High wiring density, and routing jams are alleviated. In an exemplary embodiment, a pitch between TOVs in a column of TOVs may have a gap ratio of TOV to inter-TOV oxide of 1: 1. By way of example, an exemplary 10 μm wide TOV has a 20 μm pitch (in the x and / or y dimensions). This may correspond to a density of 50 × 50 / mm 2 (or 2500 / mm 2 ). Embodiments are not limited to these exemplary gap ratios, TOV pitch, and TOV density. For example, the amount of inter-TOV oxide can be increased beyond a 1: 1 gap ratio. Larger pitches can also be implemented, such as 40 μm to 70 μm. In addition, narrower TOVs can be manufactured. In another exemplary embodiment, the TOV is 2 μm wide. Assuming a 1: 1 gap ratio, this may correspond to a pitch of 4 μm and a density of 250 × 250 / mm 2 (or 62500 / mm 2 ).

在一項態樣中,實施例描述可具有相對較低的禁入區域(KOZ)之嵌入型TSV第一層級晶粒組態。已觀察到,諸如穿過矽晶粒之銅TSV的TSV可在周圍晶粒區域中產生應力。因此,主動器件經配置於TSV周圍的側向KOZ外部,以減輕TSV誘發之應力對主動器件的作用,諸如影響主動器件中之載流子行動性。根據實施例,嵌入型第一層級(例如,主動)晶粒之厚度減少可允許形成相比於諸如傳統內插件中之彼等TSV的共同TSV具有實質上較小寬度(或直徑)的TSV。在一些實施例中,第一層級晶粒厚度:TSV最大寬度的至多為10:1的縱橫比完全在處理參數範圍內。舉例而言,具有2至10μm或較小之最大寬度(或直徑)的TSV係可能的。出於說明之目的,表1中提供TSV尺寸及縱橫比之例示性清單。 In one aspect, the embodiment describes an embedded TSV first-level die configuration that may have a relatively low no-entry zone (KOZ). It has been observed that TSVs, such as copper TSVs that pass through silicon grains, can cause stress in the surrounding grain regions. Therefore, the active device is configured outside the lateral KOZ around the TSV to reduce the effects of TSV-induced stress on the active device, such as affecting the mobility of carriers in the active device. According to an embodiment, the reduced thickness of the embedded first level (eg, active) die may allow for the formation of a TSV having a substantially smaller width (or diameter) than a common TSV such as those in a conventional interposer. In some embodiments, the aspect ratio of the first-level grain thickness: TSV maximum width of at most 10: 1 is completely within the processing parameter range. For example, TSVs with a maximum width (or diameter) of 2 to 10 μm or less are possible. For illustrative purposes, an exemplary list of TSV sizes and aspect ratios is provided in Table 1.

TSV高度減少可允許TSV最大寬度(或直徑)減少,以及TSV密度增大及KOZ較小。在一些實施例中,250×250/mm2(例如,62500/mm2)之TSV密度係可能的,其可大於可以用傳統插入件達成的約10×10/mm2(例如,100/mm2)的密度。在一些實施例中,小於約5μm之KOZ係可能的。在一實施例中,穿過第一層級晶粒之TSV與第一層級晶粒中之主動器件(例如,電晶體)相距不超過5μm。在一項態樣中,此可允許主動器件之定位以及TSV之定位及密度的較大自由度,以提供至堆疊第二層級晶粒的較短及較直接的佈線。根據實施例,堆疊第二層級晶粒可具有至封裝之底部焊盤或導電凸塊的相對筆直的佈 線,其中電源平面位於(例如)電路板上。 The reduction in TSV height allows for a reduction in the maximum TSV width (or diameter), as well as an increase in TSV density and a smaller KOZ. In some embodiments, a TSV density of 250 × 250 / mm 2 (eg, 62500 / mm 2 ) is possible, which may be greater than about 10 × 10 / mm 2 (eg, 100 / mm) that can be achieved with conventional inserts. 2 ) The density. In some embodiments, a KOZ of less than about 5 μm is possible. In one embodiment, the TSV passing through the first-level die is less than 5 μm from the active device (eg, transistor) in the first-level die. In one aspect, this allows greater freedom in the positioning of active devices and the positioning and density of TSVs to provide shorter and more direct wiring to stacked second-level dies. According to an embodiment, the stacked second-level die may have relatively straight wiring to the bottom pad or conductive bump of the package, where the power plane is on, for example, a circuit board.

現參考圖1,提供說明根據一實施例的形成封裝之方法的流程圖。為了明確,關於本文中所描述之其他圖式中所發現的參考特徵進行圖1之以下描述。在操作1010處,將第一封裝層級150形成於載體基板101、103上。第一封裝層級150可包括囊封於間隙填充氧化物層130中之第一層級晶粒110,及複數個氧化物穿孔(TOV)134。在一實施例中,TOV 134具有約20μm或較小的高度。隨後在操作1012處將第二層級晶粒210混合結合至第一封裝層級150,以形成經直接結合的氧化物對氧化物表面(例如,用於層164、264)及金屬對金屬表面(例如,用於層162、262)(參見圖9)。在操作1014處,將第二層級晶粒210囊封於第一封裝層級150之背側165上,後續接著在操作1016處移除載體基板101、103。可接著在操作1018處將RDL 300形成於第一封裝層級150之前側170上。 Referring now to FIG. 1, a flowchart illustrating a method of forming a package according to an embodiment is provided. For clarity, the following description of FIG. 1 is made with respect to reference features found in other drawings described herein. At operation 1010, a first package level 150 is formed on the carrier substrates 101, 103. The first encapsulation level 150 may include a first-level die 110 encapsulated in the gap-fill oxide layer 130 and a plurality of oxide vias (TOV) 134. In one embodiment, the TOV 134 has a height of about 20 μm or less. The second level die 210 is then mixed and bonded to the first encapsulation level 150 at operation 1012 to form a directly bonded oxide-to-oxide surface (e.g., for layers 164, 264) and a metal-to-metal surface (e.g., For layers 162, 262) (see Figure 9). At operation 1014, the second-level die 210 is encapsulated on the back side 165 of the first packaging level 150, and then the carrier substrates 101 and 103 are removed at operation 1016. The RDL 300 may then be formed on the front side 170 of the first package level 150 at operation 1018.

根據實施例,一或多個第一層級晶粒110可為主動晶粒,但此並非為所要求的。在其他實施例中,可用矽插入件或矽整合式被動器件(IPD)替換第一層級晶粒110。現參看圖2,提供根據一實施例的包括盲介層孔119之第一層級晶粒110之示意圖橫截面側視圖。根據實施例,第一層級晶粒110可為包括主動組件(諸如(但不限於)微處理器、記憶體、RF收發器及混合信號組件)之主動晶粒,諸如邏輯晶粒或SOC晶粒。在所說明之特定實施例中,借助於實例展示主動組件之主動器件121(例如,電晶體)。如所示,主動器件121可形成於基板117上,諸如矽基板或絕緣體上矽(SOI)基板。在一實施例中,主動器件121形成於頂部磊晶矽層116中,形成於基底矽基板114上方。在一實施例中,KOZ小於5μm,且盲介層孔119與主動器件121相距不超過5μm(側向地)。可出於佈線之目的形成一或多個互連層118,以將主動器件121及盲介層孔119連接至第一層級晶粒110之焊盤128(其包括前 側111上的128A、128B兩者)。互連層118可包括一或多個金屬層126及/或介電層124。在所說明之實施例中,盲介層孔119(其將變為TSV 120)穿插於第一層級晶粒110中之主動器件121之間。 According to an embodiment, one or more of the first-level dies 110 may be active dies, but this is not required. In other embodiments, the first-level die 110 may be replaced with a silicon interposer or a silicon integrated passive device (IPD). Referring now to FIG. 2, a schematic cross-sectional side view of a first level die 110 including a blind via 119 according to an embodiment is provided. According to an embodiment, the first-level die 110 may be an active die, such as a logic die or a SOC die, including active components such as (but not limited to) a microprocessor, a memory, an RF transceiver, and a mixed-signal component. . In the particular embodiment illustrated, an active device 121 (eg, a transistor) of an active component is shown by way of example. As shown, the active device 121 may be formed on a substrate 117, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. In one embodiment, the active device 121 is formed in the top epitaxial silicon layer 116 and is formed over the base silicon substrate 114. In one embodiment, the KOZ is less than 5 μm, and the distance between the blind via hole 119 and the active device 121 is not more than 5 μm (laterally). One or more interconnect layers 118 may be formed for wiring purposes to connect the active device 121 and the blind via 119 to the pads 128 (including the front Both 128A, 128B on side 111). The interconnect layer 118 may include one or more metal layers 126 and / or a dielectric layer 124. In the illustrated embodiment, a blind via hole 119 (which will become TSV 120) is interposed between the active devices 121 in the first-level die 110.

金屬層126可提供側向互連路徑,其中介層孔127提供垂直連接。根據實施例,第一層級晶粒110之前側111可包括絕緣層122(例如,氧化物或聚合物)、連接至盲介層孔119之焊盤128B,及/或連接至第一層級晶粒110之主動器件121的焊盤128A。在所說明之實施例中,盲介層孔119形成於主動器件121之作用層(例如,頂部磊晶層116)中。盲介層孔119可完全延伸穿過作用層(例如,磊晶層116),且視需要延伸至基底基板114中。盲介層孔119之深度可至少為有待形成之最終TSV 120的深度。在一實施例中,盲介層孔119可視情況至少部分延伸穿過互連層118。舉例而言,盲介層孔119可穿過互連層118延伸至焊盤128A,或在一實施例中延伸至金屬層126。在一實施例中,盲介層孔119可不接觸前側111上的焊盤(例如,128A、128B),且改為穿過互連層118中之一或多個金屬層126及介層孔127與主動器件121連接。以此方式,有待形成之TSV 120可直接連接至第一層級晶粒110內的主動器件121。 The metal layer 126 may provide a lateral interconnection path, with the vias 127 providing vertical connections. According to an embodiment, the front side 111 of the first-level die 110 may include an insulating layer 122 (eg, an oxide or a polymer), a pad 128B connected to the blind via hole 119, and / or a first-level die. The pad 128A of the active device 121 of 110. In the illustrated embodiment, the blind via hole 119 is formed in an active layer of the active device 121 (eg, the top epitaxial layer 116). The blind via hole 119 may completely extend through the active layer (for example, the epitaxial layer 116), and may extend into the base substrate 114 as needed. The depth of the blind via hole 119 may be at least the depth of the final TSV 120 to be formed. In an embodiment, the blind via hole 119 may optionally extend at least partially through the interconnect layer 118. For example, the blind via hole 119 may extend through the interconnect layer 118 to the pad 128A, or in one embodiment to the metal layer 126. In an embodiment, the blind vias 119 may not contact the pads (eg, 128A, 128B) on the front side 111 and pass through one or more metal layers 126 and vias 127 in the interconnect layer 118 instead It is connected to the active device 121. In this way, the TSV 120 to be formed can be directly connected to the active device 121 in the first-level die 110.

現參看圖3,一或多個第一層級晶粒110被安裝於諸如玻璃板、矽晶圓、金屬板等的載體基板101上。載體基板101可包括用於安裝第一層級晶粒之脫模層102。在一實施例中,脫模層102為氧化物層,且使用氧化物對氧化物結合(例如,與氧化物絕緣層122結合)將第一層級晶粒110安裝於載體基板101上。在一實施例中,脫模層102為用於安裝第一層級晶粒110之黏著劑(例如,聚合物)或膠帶層。如所示,第一層級晶粒110面朝下安裝至載體基板101上,使得包括絕緣層122及焊盤128(128A、128B)之前側111面朝下。如所示,一或多個第一層級110可為具有不同厚度及面積的不同晶粒,其包括不同組件。第一 層級晶粒110中之一或多者可為主動晶粒。盲介層孔119視需要形成於第一層級晶粒110中之一或多者內,但此並非為所要求的。 Referring now to FIG. 3, one or more first-level dies 110 are mounted on a carrier substrate 101 such as a glass plate, a silicon wafer, a metal plate, or the like. The carrier substrate 101 may include a release layer 102 for mounting a first-level die. In one embodiment, the release layer 102 is an oxide layer, and the first-level die 110 is mounted on the carrier substrate 101 using an oxide-to-oxide combination (eg, in combination with the oxide insulating layer 122). In one embodiment, the release layer 102 is an adhesive (eg, a polymer) or a tape layer for mounting the first-level die 110. As shown, the first-level die 110 is mounted face down on the carrier substrate 101 so that the front side 111 including the insulating layer 122 and the pads 128 (128A, 128B) faces down. As shown, the one or more first levels 110 may be different dies having different thicknesses and areas, which include different components. the first One or more of the hierarchical grains 110 may be active grains. Blind vias 119 are formed in one or more of the first-level dies 110 as needed, but this is not required.

一或多個第一層級晶粒110可接著使用諸如化學機械拋光(CMP)之合適技術研磨,以減小第一層級晶粒110之厚度,如圖4中所示。根據實施例,第一層級晶粒110之薄化可曝露盲介層孔119,導致第一層級晶粒110之背側115包括TSV 120之曝露表面123。在一實施例中,第一層級晶粒110薄化至約20μm或更小,諸如2μm至20μm,或5μm至10μm。 One or more first-level dies 110 may then be ground using a suitable technique such as chemical mechanical polishing (CMP) to reduce the thickness of the first-level dies 110 as shown in FIG. 4. According to an embodiment, the thinning of the first-level die 110 may expose the blind via hole 119, resulting in that the back side 115 of the first-level die 110 includes the exposed surface 123 of the TSV 120. In one embodiment, the first-level grains 110 are thinned to about 20 μm or less, such as 2 μm to 20 μm, or 5 μm to 10 μm.

參看圖5中所說明之實施例,可接著將間隙填充氧化物層130形成於薄化之第一層級晶粒110上方。在一實施例中,使用諸如化學氣相沈積(CVD)之合適技術沈積間隙填充氧化物層130,但可使用其他技術。歸因於第一層級晶粒110之厚度減少,可使用CVD沈積優質間隙填充氧化物層130,其可輔助混合結合。 Referring to the embodiment illustrated in FIG. 5, a gap-fill oxide layer 130 may then be formed over the thinned first-level grains 110. In one embodiment, the gap-fill oxide layer 130 is deposited using a suitable technique such as chemical vapor deposition (CVD), but other techniques may be used. Due to the reduced thickness of the first-level grains 110, a high-quality gap-fill oxide layer 130 can be deposited using CVD, which can assist in hybrid bonding.

現參看圖6,TOV 134可形成為穿過間隙填充氧化物層130。舉例而言,間隙填充氧化物層130可經平坦化、圖案化,且TOV 134形成於平坦化間隙填充氧化物層130內。亦可視需要形成TSV 120。舉例而言,可在此階段在盲介層孔119並非事先形成於第一層級晶粒110中的實施例中形成TSV 120。在一實施例中,薄化之第一層級晶粒110不包括TSV 120。在圖6中所說明之特定實施例中,間隙填充氧化物層130之後表面131及第一層級晶粒110之背側115經平坦化,從而曝露TOV 134之表面135,且視需要曝露TSV 120之表面123。 Referring now to FIG. 6, the TOV 134 may be formed through the gap-fill oxide layer 130. For example, the gap-fill oxide layer 130 may be planarized and patterned, and the TOV 134 is formed in the planarized gap-fill oxide layer 130. Optionally, TSV 120 can be formed. For example, the TSV 120 may be formed at this stage in an embodiment where the blind via hole 119 is not formed in the first-level die 110 in advance. In one embodiment, the thinned first-level die 110 does not include the TSV 120. In the specific embodiment illustrated in FIG. 6, the surface 131 after the gap-fill oxide layer 130 and the back side 115 of the first-level die 110 are planarized to expose the surface 135 of the TOV 134 and the TSV 120 as needed. Of the surface 123.

第一層級RDL 160可視需要如圖7中所說明的形成於間隙填充氧化物層130及薄化之第一層級晶粒110上方。第一層級RDL可形成於複數個TOV 134及/或TSV 120上,且與其等電接觸。如所示,第一層級RDL 160可包括一或多條金屬重佈線162(例如,銅)及絕緣層164。在一實施例中,一或多個絕緣層164由氧化物(例如,SiO2)形成,以供後 續混合結合。間隙填充氧化物層130、TOV 134、第一層級晶粒110,及可選第一層級RDL 160一起形成第一封裝層級150。如圖8中所說明,可使用諸如CMP之合適技術來平坦化第一封裝層級150(例如,第一層級RDL 160)之背側165,以形成用於混合結合之平坦表面。 The first-level RDL 160 may be formed over the gap-fill oxide layer 130 and the thinned first-level crystal grain 110 as illustrated in FIG. 7 as needed. The first-level RDL may be formed on a plurality of TOVs 134 and / or TSVs 120 and in electrical contact therewith. As shown, the first level RDL 160 may include one or more metal redistribution lines 162 (eg, copper) and an insulating layer 164. In one embodiment, one or more insulating layers 164 are formed of an oxide (eg, SiO 2 ) for subsequent mixing and bonding. The gap-fill oxide layer 130, the TOV 134, the first-level die 110, and the optional first-level RDL 160 together form a first package level 150. As illustrated in FIG. 8, the backside 165 of the first package level 150 (eg, the first level RDL 160) may be planarized using a suitable technique such as CMP to form a flat surface for hybrid bonding.

可接著將一或多個第二層級晶粒210混合結合至第一封裝層級150,如圖9中所說明之實施例中所示。在所說明之特定實施例中,第二層級晶粒210被面朝下混合結合,其中第二層級晶粒210之(例如,平坦的)前側211混合結合至第一封裝層級150之背側165(例如,平坦後表面)。更確切而言,前表面211可混合結合至第一層級RDL 160(若存在)。圖9中之混合結合之近視圖展示:第一層級RDL 160之絕緣層164(例如,SiO2)與用於第二層級晶粒210之堆積結構260的絕緣層264(例如,SiO2)之直接結合氧化物對氧化物表面;及第一層級RDL 160之重佈線162(例如,銅)與用於第二層級晶粒210之堆積結構260的金屬層262(例如,銅)之直接結合金屬對金屬表面。 One or more second-level dies 210 may then be mixed and bonded to the first packaging level 150, as shown in the embodiment illustrated in FIG. In the particular embodiment illustrated, the second-level die 210 is mixed-faced face down, wherein the (eg, flat) front side 211 of the second-level die 210 is mixed-bonded to the back side 165 of the first package level 150 (For example, a flat rear surface). More precisely, the front surface 211 may be hybrid bonded to the first level RDL 160 (if present). A close-up view of the hybrid combination in FIG. 9 shows that: an insulating layer 164 (eg, SiO 2 ) of the first-level RDL 160 and an insulating layer 264 (eg, SiO 2 ) of the stacked structure 260 of the second-level die 210 Direct bonding of oxide to the oxide surface; and direct bonding of redistribution 162 (eg, copper) of first level RDL 160 and metal layer 262 (eg, copper) of stacked structure 260 for second level die 210 On metal surface.

第二層級晶粒210隨後囊封於第一封裝層級150之背側165上的第二層級模製化合物240中。舉例而言,第二層級模製化合物240可包括熱固型交聯樹脂(例如,環氧樹脂),但可使用如電子封裝中所已知的其他材料。可使用合適技術來實現囊封,諸如但不限於轉注模製、壓縮模製及層壓。在所說明之實施例中,第二層級模製化合物240覆蓋第二層級晶粒210之背側215。較厚的第二層級模製化合物240可在後續處理期間提供結構支撐。 The second level die 210 is then encapsulated in a second level molding compound 240 on the back side 165 of the first packaging level 150. For example, the second-level molding compound 240 may include a thermosetting cross-linked resin (eg, epoxy resin), but other materials may be used as known in electronic packaging. Encapsulation may be achieved using suitable techniques, such as, but not limited to, injection molding, compression molding, and lamination. In the illustrated embodiment, the second-level molding compound 240 covers the backside 215 of the second-level die 210. The thicker second level molding compound 240 may provide structural support during subsequent processing.

現參看圖11,移除載體基板101,且可將RDL 300形成於第一封裝層級150之前側170上。具體而言,可將RDL 300形成於間隙填充氧化物層130及第一層級晶粒110之前側111上。如所示,亦可將RDL 300形成於複數個TOV 134上且與其等電接觸。RDL 300可包括單條重佈線302或多條重佈線302及介電層304。RDL 300可藉由逐層程序形 成,且可使用薄膜技術形成。在一實施例中,RDL 300具有小於50μm之總厚度,或更確切而言,小於30μm,諸如約20μm。在一實施例中,RDL 300包括嵌入型重佈線302(嵌入型跡線)。舉例而言,可藉由首先形成晶種層,隨後形成金屬(例如銅)圖案而產生重佈線302。替代地,可藉由沈積(例如,濺鍍)及蝕刻形成重佈線302。重佈線302之材料可包括(但不限於)金屬材料,諸如銅、鈦、鎳、金及其組合或合金。重佈線302之金屬圖案接著嵌入於視情況經圖案化之介電層304中。該(等)介電層304可為任何合適之材料,諸如氧化物或聚合物(例如聚醯亞胺)。在形成RDL 300之後,可將複數個導電凸塊350(例如,焊料凸塊或柱形凸塊)形成於RDL 300之前側311上。可接著自經重配基板單體化個別封裝100。在一些實施例中,可在單體化之前使用諸如CMP之合適技術來減小包括第二層級模製化合物240及第二層級晶粒210之第二封裝層級250的厚度。在圖12中所說明之實施例中,可減小第二封裝層級250之厚度以曝露一或多個第二層級晶粒210的背側215。 Referring now to FIG. 11, the carrier substrate 101 is removed, and the RDL 300 may be formed on the front side 170 of the first package level 150. Specifically, the RDL 300 may be formed on the front side 111 of the gap-fill oxide layer 130 and the first-level crystal grain 110. As shown, RDL 300 may also be formed on and in electrical contact with a plurality of TOVs 134. The RDL 300 may include a single redistribution 302 or a plurality of redistributions 302 and a dielectric layer 304. RDL 300 can be programmed by layer And can be formed using thin film technology. In one embodiment, the RDL 300 has a total thickness of less than 50 μm, or more specifically, less than 30 μm, such as about 20 μm. In one embodiment, the RDL 300 includes an embedded redistribution 302 (embedded trace). For example, the redistribution 302 may be generated by first forming a seed layer and then forming a metal (eg, copper) pattern. Alternatively, the redistribution 302 may be formed by deposition (eg, sputtering) and etching. The material of the redistribution 302 may include, but is not limited to, a metal material such as copper, titanium, nickel, gold, and combinations or alloys thereof. The metal pattern of the redistribution 302 is then embedded in the patterned dielectric layer 304 as appropriate. The (or other) dielectric layer 304 may be any suitable material, such as an oxide or a polymer (eg, polyimide). After forming the RDL 300, a plurality of conductive bumps 350 (for example, solder bumps or pillar bumps) may be formed on the front side 311 of the RDL 300. Individual packages 100 may then be singulated from the reconfigured substrate. In some embodiments, the thickness of the second packaging level 250 including the second level molding compound 240 and the second level die 210 may be reduced using a suitable technique such as CMP before singulation. In the embodiment illustrated in FIG. 12, the thickness of the second package level 250 may be reduced to expose the backside 215 of the one or more second level dies 210.

圖13為根據實施例的封裝100之示意性仰視圖說明,其說明自包括第一層級晶粒110之第一封裝層級150至包括第二層級晶粒210之第二封裝層級250的多種TOV 134及(視需要)TSV 120連接。圖13亦說明在實施例中可為可能的封裝層級內之晶粒大小(x、y維度)及定位(x、y位置)之自由度。根據實施例,異質晶粒可整合至多個封裝層級中,而無需一個封裝層級必須大於另一封裝層級。因此,特定晶粒無需封裝至主要載體封裝層級中。此外,可達成封裝層級之間的短通信路徑。根據實施例,介層孔(TOV或TSV)可位於第一封裝層級150之整個面中的任何位置處,其可允許第一層級晶粒110及第二層級晶粒210兩者對電力分配之完全存取。根據實施例,可另外在晶粒重疊處提供第一層級晶粒110與第二層級晶粒210之間的短通信路徑長度。在一項實 施例中,第一層級晶粒110可為橋接晶粒,其包括位於兩個單獨第二層級晶粒210正下方且與其通信的TSV 120。 13 is a schematic bottom view illustration of a package 100 according to an embodiment, illustrating a variety of TOVs 134 from a first package level 150 including a first level die 110 to a second package level 250 including a second level die 210 And (if required) TSV 120 connection. FIG. 13 also illustrates the degrees of freedom of the grain size (x, y dimensions) and positioning (x, y positions) within the possible packaging levels in an embodiment. According to an embodiment, heterogeneous dies can be integrated into multiple packaging levels without requiring one packaging level to be larger than another packaging level. Therefore, a specific die does not need to be packaged into the main carrier packaging level. In addition, short communication paths between packaging levels can be achieved. According to an embodiment, a via hole (TOV or TSV) may be located anywhere on the entire surface of the first package level 150, which may allow both the first-level die 110 and the second-level die 210 to distribute power. Full access. According to an embodiment, a short communication path length between the first-level die 110 and the second-level die 210 may be additionally provided at the die overlap. In a real In an embodiment, the first-level die 110 may be a bridge die, which includes a TSV 120 located directly under and in communication with two separate second-level die 210.

圖14為說明根據一實施例的形成封裝之方法的流程圖,該方法可視情況包括形成兩個以上封裝層級。在圖14之以下描述中,對在圖3至圖12及圖15A至圖15D中提供之橫截面側視圖說明中所發現的特徵進行參考。參看圖14,在操作1410處,將第一層級晶粒110附接至載體基板101,類似於先前關於圖3A所描述的。在操作1412處,減小第一層級晶粒110之厚度,類似於關於圖4所描述的。在操作1414處,將間隙填充氧化物層130沈積在薄化之第一層級晶粒110上,類似於關於圖5所描述的。在操作1416處,將間隙填充氧化物層130(及視需要第一層級晶粒110)平坦化,類似於關於圖6所描述的。在操作1418處,穿過間隙填充氧化物層130形成TOV 134,類似於關於圖6所描述的。在操作1420處,將第一層級RDL 160形成於間隙填充氧化物層130及第一層級晶粒110上方,類似於關於圖7至圖8所描述的,從而產生圖15B中所說明之結構。 14 is a flowchart illustrating a method of forming a package according to an embodiment. The method may optionally include forming two or more packaging levels. In the following description of FIG. 14, reference is made to features found in the cross-sectional side view descriptions provided in FIGS. 3 to 12 and 15A to 15D. Referring to FIG. 14, at operation 1410, a first level die 110 is attached to the carrier substrate 101, similar to that previously described with respect to FIG. 3A. At operation 1412, the thickness of the first-level die 110 is reduced, similar to that described with respect to FIG. At operation 1414, a gap-fill oxide layer 130 is deposited on the thinned first-level grains 110, similar to that described with respect to FIG. At operation 1416, the gap-fill oxide layer 130 (and the first-level grain 110 as needed) is planarized, similar to that described with respect to FIG. At operation 1418, a TOV 134 is formed through the gap-fill oxide layer 130, similar to that described with respect to FIG. At operation 1420, a first-level RDL 160 is formed over the gap-fill oxide layer 130 and the first-level grains 110, similar to that described with respect to FIGS. 7-8, thereby producing the structure illustrated in FIG. 15B.

在操作1422處,將第二層級晶粒210或視需要第一層級晶粒110混合結合至第一層級RDL 160,類似於關於圖9所描述的,從而產生圖15C中所說明之結構。在此階段,可一或多次地重複操作1412至1422以形成額外封裝層級150A、150B等。在操作1424處,將第二層級晶粒210囊封於第一封裝層級之背側上,類似於關於圖10所描述的。在操作1426處,移除載體基板101,且在操作1428處,將RDL形成於第一封裝層級之前側上,類似於關於圖11所描述的。可接著減小第二封裝層級250之厚度,類似於關於圖12所描述的。參考圖15D,說明一程序流程,其中,形成兩個封裝層級150A、150B,將第二層級晶粒210囊封於第一封裝層級150B之背側165B上,且將RDL 300形成於第一封裝層級150A之前側170A上。 At operation 1422, the second-level die 210 or, if necessary, the first-level die 110 is mixed and bonded to the first-level RDL 160, similar to that described with respect to FIG. 9, resulting in the structure illustrated in FIG. 15C. At this stage, operations 1412 to 1422 may be repeated one or more times to form additional packaging levels 150A, 150B, and the like. At operation 1424, the second level die 210 is encapsulated on the backside of the first packaging level, similar to that described with respect to FIG. At operation 1426, the carrier substrate 101 is removed, and at operation 1428, the RDL is formed on the front side of the first package level, similar to that described with respect to FIG. The thickness of the second package level 250 may then be reduced, similar to that described with respect to FIG. 12. Referring to FIG. 15D, a program flow is described in which two packaging levels 150A, 150B are formed, the second level die 210 is encapsulated on the back side 165B of the first packaging level 150B, and the RDL 300 is formed on the first package Level 150A is on the front side 170A.

圖16為說明根據一實施例的形成封裝之方法的流程圖。在圖16之以下描述中,對在圖3至圖12及圖17A至圖17E中提供之橫截面側視圖說明中所發現的特徵進行參考。參看圖16,在操作1610處,將第一層級晶粒110附接至第一載體基板101,類似於先前關於圖3所描述的。在操作1612處,減小第一層級晶粒110之厚度,類似於關於圖4所描述的。在操作1614處,將間隙填充氧化物層130沈積在薄化之第一層級晶粒110上,類似於關於圖5所描述的。在操作1618處,穿過間隙填充氧化物層130形成TOV 134,類似於關於圖6所描述的,從而產生圖17A中所說明之結構。 FIG. 16 is a flowchart illustrating a method of forming a package according to an embodiment. In the following description of FIG. 16, reference is made to features found in the cross-sectional side view descriptions provided in FIGS. 3 to 12 and 17A to 17E. Referring to FIG. 16, at operation 1610, a first-level die 110 is attached to a first carrier substrate 101 similar to that previously described with respect to FIG. 3. At operation 1612, the thickness of the first-level die 110 is reduced, similar to that described with respect to FIG. At operation 1614, a gap-fill oxide layer 130 is deposited on the thinned first-level grains 110, similar to that described with respect to FIG. At operation 1618, a TOV 134 is formed through the gap-fill oxide layer 130, similar to that described with respect to FIG. 6, resulting in the structure illustrated in FIG. 17A.

在操作1620處,將第二載體基板103附接至薄化之第一層級晶粒110及間隙填充氧化物層130。可接著在操作1622處移除第一載體基板101,且在操作1624處將第一層級RDL 160形成於間隙填充氧化物層130及第一層級晶粒110上方,從而產生圖17B中所說明之結構。在此階段,第一層級晶粒110之前側111面朝上向著第一封裝層級150中之第一層級RDL 160。 At operation 1620, the second carrier substrate 103 is attached to the thinned first-level grains 110 and the gap-fill oxide layer 130. The first carrier substrate 101 may then be removed at operation 1622, and a first-level RDL 160 is formed over the gap-fill oxide layer 130 and the first-level die 110 at operation 1624, thereby producing the one illustrated in FIG. 17B structure. At this stage, the front side 111 of the first-level die 110 faces upward toward the first-level RDL 160 in the first package level 150.

在操作1626處,將第二層級晶粒210混合結合至第一層級RDL 160,類似於關於圖9所描述的,從而產生圖17C中所說明之結構。在此階段,可一或多次地重複操作1412至1422或1612至1626以形成額外封裝層級150A、150B等。在操作1628處,將第二層級晶粒210囊封於第一封裝層級之背側上,類似於關於圖10所描述的。在操作1630處,移除第二載體基板103,且在操作1632處,將RDL形成於第一封裝層級之前側上,類似於關於圖11所描述的。可接著減小第二封裝層級250之厚度,類似於關於圖12所描述的。參看圖17D,說明一程序流程,其中形成一個第一封裝層級150,其中第一層級晶粒110之前側111及第二層級晶粒210之前側211面向彼此。參考圖17E,說明一程序流程,其中,形成兩個封裝層級150A、150B,將第二層級晶粒210囊 封於第一封裝層級150B之背側165B上,且將RDL 300形成於第一封裝層級150A之前側170A上。在圖17E中所說明之實施例中,第一封裝層級150A內的第一層級晶粒110A之前側111與第一封裝層級150B內的第一層級晶粒110B之前側111面向彼此。替代地,第一層級晶粒110A或110B中之任一者的定向可反轉。 At operation 1626, the second-level die 210 is mixed and bonded to the first-level RDL 160, similar to that described with respect to FIG. 9, resulting in the structure illustrated in FIG. 17C. At this stage, operations 1412 to 1422 or 1612 to 1626 may be repeated one or more times to form additional packaging levels 150A, 150B, and the like. At operation 1628, the second-level die 210 is encapsulated on the backside of the first packaging level, similar to that described with respect to FIG. At operation 1630, the second carrier substrate 103 is removed, and at operation 1632, the RDL is formed on the front side of the first package level, similar to that described with respect to FIG. 11. The thickness of the second package level 250 may then be reduced, similar to that described with respect to FIG. 12. Referring to FIG. 17D, a program flow is described in which a first package level 150 is formed, wherein the front side 111 of the first level die 110 and the front side 211 of the second level die 210 face each other. Referring to FIG. 17E, a program flow is described in which two packaging levels 150A and 150B are formed, and the second level die 210 is encapsulated. It is sealed on the back side 165B of the first package level 150B, and the RDL 300 is formed on the front side 170A of the first package level 150A. In the embodiment illustrated in FIG. 17E, the front side 111 of the first level die 110A in the first packaging level 150A and the front side 111 of the first level die 110B in the first packaging level 150B face each other. Alternatively, the orientation of any of the first-level dies 110A or 110B may be reversed.

現參看圖18,根據一實施例提供晶粒堆疊配置之示意性仰視圖說明及一列TOV之近距透視圖。圖19A為根據一實施例的沿圖18中之線A-A截得之封裝的橫截面側視圖說明。圖19B為根據一實施例的沿圖18中之線B-B截得之封裝的橫截面側視圖說明。在所說明之實施例中,封裝100包括第一層級晶粒110A、第二個第一層級晶粒110B、及第三個第一層級晶粒110C、TOV 134之第一列136A,及TOV 134之第二列136B。第二個第一層級晶粒110B及第三個第一層級晶粒110C側向地鄰近於第一層級晶粒110A之對立側。參看圖18,第一層級晶粒110A係矩形的,但根據實施例其他形狀係可能的。如所示,TOV 134之第一列136A及第二列136B側向地鄰近於(且平行於)第一層級晶粒110A之第一對側向對立側105A、105B。如所示,第二個第一層級晶粒110B及第三個第一層級晶粒110C分別側向地鄰近於(且平行於)第一層級主動晶粒110A之第二對側向對立側108A、108B。 Referring now to FIG. 18, a schematic bottom view description of a die stack configuration and a close-up perspective view of a column of TOVs are provided according to an embodiment. FIG. 19A is a cross-sectional side view illustration of a package taken along line A-A in FIG. 18 according to an embodiment. FIG. 19B is a cross-sectional side view illustration of the package taken along line B-B in FIG. 18 according to an embodiment. In the illustrated embodiment, the package 100 includes a first level die 110A, a second first level die 110B, and a third first level die 110C, a first column 136A of TOV 134, and TOV 134 The second column is 136B. The second first-level die 110B and the third first-level die 110C are laterally adjacent to opposite sides of the first-level die 110A. Referring to FIG. 18, the first-level die 110A is rectangular, but other shapes are possible according to the embodiment. As shown, the first row 136A and the second row 136B of the TOV 134 are laterally adjacent (and parallel to) the first pair of laterally opposing sides 105A, 105B of the first level die 110A. As shown, the second first-level die 110B and the third first-level die 110C are laterally adjacent (and parallel to) the second pair of laterally opposite sides of the first-level active die 110A, respectively. , 108B.

參看圖18及圖19A至圖19B,第一個第二層級晶粒210A及第二個第二層級晶粒210B並列配置在第一層級晶粒上。TOV 134之第一列136A位於第一個第二層級晶粒210A下方,且TOV 134之第二列136B位於第二個第二層級晶粒210B下方。TOV 134之列136A、136B可平行於對應第二層級晶粒210A、210B之鄰近邊緣203。在一實施例中,第一層級(例如,主動)晶粒210A之背側115面向側向地介於TOV 134之第一列136A及第二列136B之間的第一個第二層級晶粒210A及第二個第二層級晶粒210B之前側111。在此組態中,可達成至第一層級主動 晶粒110A之每一不同邊緣的短電佈線路徑(藉由圖18中之箭頭說明)。舉例而言,RDL 300(例如,參見圖19A至圖19B)可形成於第一層級主動晶粒110A、TOV 134之第一列136A及第二列136B,及第二個第一層級晶粒110B及第三個第一層級晶粒110C上且與其等電接觸。 Referring to FIG. 18 and FIGS. 19A to 19B, the first second-level die 210A and the second second-level die 210B are arranged side by side on the first-level die. The first column 136A of the TOV 134 is located below the first second-level die 210A, and the second column 136B of the TOV 134 is located below the second second-level die 210B. The rows 136A, 136B of the TOV 134 may be parallel to the adjacent edges 203 corresponding to the second-level dies 210A, 210B. In an embodiment, the back side 115 of the first level (eg, active) die 210A faces the first second level die between the first row 136A and the second row 136B of the TOV 134 laterally. 210A and the front side 111 of the second second-level die 210B. In this configuration, it is possible to reach the first level of initiative Short electrical wiring paths (illustrated by arrows in FIG. 18) for each different edge of the die 110A. For example, RDL 300 (e.g., see FIGS. 19A to 19B) may be formed in the first row 136A and the second row 136B of the first level active die 110A, TOV 134, and the second first level die 110B And a third first-level die 110C and is in electrical contact therewith.

在一實施例中,封裝100包括RDL 300及位於RDL 300之背側315上的第一封裝層級150之前側170。第一層級晶粒110A囊封於RDL 300之背側315上的間隙填充氧化物層130中。另外,第二個第一層級晶粒110B及第三個第一層級晶粒110C可定位為側向地鄰近於第一層級晶粒110A之對立側。第一層級晶粒110A、110B、110C可全部位於RDL 300上且與其電接觸。TOV 134之第一列136A及TOV 134之第二列136B自RDL 300之背側315凸起,且第一層級晶粒110A側向地定位於TOV 134之第一列136A及第二列136B之間。在一實施例中,RDL 300可形成於第一層級晶粒110A、110B、110C及TOV之第一列136A及第二列136B之前側111上,且與其等電接觸。複數個第二層級晶粒210A、210B混合結合至第一封裝層級150之背側165,具有直接結合氧化物對氧化物表面及直接結合金屬對金屬表面。第一封裝層級150可另外包括位於第一層級晶粒110A及間隙填充氧化物層130之背側115上的第一封裝層級RDL 160。 In one embodiment, the package 100 includes an RDL 300 and a front side 170 of a first package level 150 on a back side 315 of the RDL 300. The first-level die 110A is encapsulated in a gap-filled oxide layer 130 on the backside 315 of the RDL 300. In addition, the second first-level die 110B and the third first-level die 110C may be positioned laterally adjacent to opposite sides of the first-level die 110A. The first-level dies 110A, 110B, 110C may all be located on and in electrical contact with the RDL 300. The first column 136A of TOV 134 and the second column 136B of TOV 134 protrude from the back side 315 of RDL 300, and the first-level die 110A is positioned laterally in the first column 136A and the second column 136B of TOV 134 between. In one embodiment, the RDL 300 may be formed on the front side 111 of the first row 136A and the second row 136B of the first-level die 110A, 110B, 110C, and TOV, and is in electrical contact therewith. A plurality of second-level dies 210A, 210B are mixed and bonded to the back side 165 of the first package level 150, and have a direct-bonded oxide-to-oxide surface and a direct-bonded metal-to-metal surface. The first packaging level 150 may further include a first packaging level RDL 160 on the backside 115 of the first level die 110A and the gap-fill oxide layer 130.

應瞭解,一對第二層級晶粒210A、210B及一對第二個第一層級晶粒110B及第三個第一層級晶粒110C的特定配置係例示性的。雖然特定配置可用以形成至第一層級晶粒110A之每一側的短的電佈線路徑,但其他組態係可能的。另外,第一層級晶粒110A、第二個第一層級晶粒110B及/或第三個第一層級晶粒110C可包括如先前所描述的TSV 120。 It should be understood that the specific configuration of a pair of second-level grains 210A, 210B and a pair of second first-level grains 110B and third first-level grains 110C is exemplary. Although specific configurations may be used to form short electrical wiring paths to each side of the first level die 110A, other configurations are possible. In addition, the first-level die 110A, the second first-level die 110B, and / or the third first-level die 110C may include the TSV 120 as previously described.

雖然分別描述及說明若干封裝變化,但許多結構特徵及處理序列可組合於單一實施例中。在利用實施例之各種態樣中,對於熟習此 項技術者將變得顯而易見,以上實施例之組合或變化有可能用於形成包括異質堆疊晶粒之封裝。儘管已經用對於結構特徵及/或方法動作而言特定之語言描述實施例,但應理解,所附申請專利範圍不必受限於所描述之特定特徵或動作。所揭示之特定特徵及動作應替代地理解為申請專利範圍的對於說明有用之實施例。 Although several packaging variations are described and illustrated separately, many structural features and processing sequences can be combined in a single embodiment. In various aspects of using the embodiments, It will become apparent to those skilled in the art that combinations or variations of the above embodiments may be used to form packages that include heterogeneous stacked dies. Although embodiments have been described in language specific to structural features and / or methodological acts, it is to be understood that the scope of the appended patent application is not necessarily limited to the specific features or acts described. The specific features and actions disclosed should instead be construed as embodiments of the patentable scope useful for illustration.

Claims (19)

  1. 一種半導體封裝,其包含:一重佈層(RDL);位於該RDL上之一第一封裝層級的一前側,該第一封裝層級包括:囊封於該RDL上之一間隙填充氧化物層中的一第一層級晶粒,其中該第一層級晶粒的側向對立側係由間隙填充氧化物層側向圍繞;及側向地鄰近於該第一層級晶粒之該等側向對立側及延伸穿過該間隙填充氧化物層的複數個氧化物穿孔(TOV);其中該等TOV及該第一層級晶粒具有約20微米或更小的高度;及一第二封裝層級,其包括混合結合至該第一封裝層級之一背側的一第二層級晶粒,該混合結合包括直接結合氧化物對氧化物表面及直接結合金屬對金屬表面。 A semiconductor package includes: a redistribution layer (RDL); a front side of a first package level on the RDL, the first package level comprising: a gap-filled oxide layer encapsulated in the RDL A first-level grain, wherein laterally opposite sides of the first-level grain are laterally surrounded by a gap-fill oxide layer; and the laterally-opposite sides laterally adjacent to the first-level grain and A plurality of oxide vias (TOVs) extending through the gap-filled oxide layer; wherein the TOVs and the first-level grains have a height of about 20 microns or less; and a second encapsulation level including a hybrid A second-level die bonded to a back side of one of the first encapsulation levels. The hybrid bonding includes directly bonding an oxide to an oxide surface and directly bonding a metal to a metal surface.
  2. 如請求項1之半導體封裝,其中該第一封裝層級包括位於該第一層級晶粒及該間隙填充氧化物層之一背側上的一第一封裝層級RDL,且該複數個TOV在該RDL與該第一封裝層級RDL之間提供一電連接。 The semiconductor package of claim 1, wherein the first package level includes a first package level RDL on a backside of the first level die and the gap-fill oxide layer, and the plurality of TOVs are in the RDL An electrical connection is provided with the first package level RDL.
  3. 如請求項2之半導體封裝,其中該第二層級晶粒混合結合至該第一封裝層級RDL之一平坦化後表面。 The semiconductor package of claim 2, wherein the second-level die is mixed and bonded to one of the first package-level RDLs after planarizing.
  4. 如請求項3之半導體封裝,其中該第一封裝層級RDL包括一氧化物介電層及金屬重佈線,且該第二層級晶粒混合結合至該氧化物介電層及該金屬重佈線。 The semiconductor package as claimed in claim 3, wherein the first package level RDL includes an oxide dielectric layer and a metal redistribution, and the second level die is mixed and bonded to the oxide dielectric layer and the metal redistribution.
  5. 如請求項2之半導體封裝,其中該第一層級晶粒包括複數個矽穿孔(TSV),且該第一封裝層級RDL形成於該複數個TSV上且與其等電接觸。 The semiconductor package of claim 2, wherein the first-level die includes a plurality of silicon vias Holes (TSV), and the first package level RDL is formed on the plurality of TSVs and is in electrical contact therewith.
  6. 如請求項1之半導體封裝,其中該RDL形成於該第一層級晶粒之一前側及該複數個TOV上,且與其等電接觸。 The semiconductor package of claim 1, wherein the RDL is formed on a front side of the first-level die and on the plurality of TOVs, and is in electrical contact therewith.
  7. 一種半導體封裝,其包含:一重佈層(RDL);位於該RDL上之一第一封裝層級的一前側,該第一封裝層級包括:囊封於該RDL上之一間隙填充氧化物層中的一第一層級晶粒;及延伸穿過該間隙填充氧化物層的複數個氧化物穿孔(TOV);其中該等TOV及該第一層級晶粒具有約20微米或更小的高度;及一第二封裝層級,其包括混合結合至該第一封裝層級之一背側的一第二層級晶粒,該混合結合包括直接結合氧化物對氧化物表面及直接結合金屬對金屬表面,其中該第二層級晶粒囊封於該第一封裝層級上的一模製化合物中。 A semiconductor package includes: a redistribution layer (RDL); a front side of a first package level on the RDL, the first package level comprising: a gap-filled oxide layer encapsulated in the RDL A first-level grain; and a plurality of oxide vias (TOV) extending through the gap-fill oxide layer; wherein the TOV and the first-level grain have a height of about 20 microns or less; and The second packaging level includes a second level of grains bonded to a back side of one of the first packaging levels. The mixed bonding includes a direct bonding oxide-to-oxide surface and a direct bonding metal-to-metal surface. The two-level die is encapsulated in a molding compound on the first packaging level.
  8. 如請求項7之半導體封裝,其進一步包含:一第二列TOV;其中該複數個TOV包含一第一列TOV,且該第一列TOV及該第二列TOV側向地鄰近於該第一層級晶粒之一第一對側向對立側;一第二個第一層級晶粒及一第三個第一層級晶粒,其側向地鄰近於該第一層級晶粒之一第二對側向對立側;其中該RDL形成於該第一層級晶粒之一前側、該第二個第一層級晶粒之一前側、該第三個第一層級晶粒之一前側、該第一列TOV及該第二列TOV上,且與其等電接觸。 The semiconductor package of claim 7, further comprising: a second column of TOVs; wherein the plurality of TOVs include a first column of TOVs, and the first column of TOVs and the second column of TOVs are laterally adjacent to the first column of TOVs A first pair of side-level grains is opposite to the opposite side; a second first-level grain and a third first-level grain are laterally adjacent to a second pair of one of the first-level grains Laterally opposite sides; wherein the RDL is formed in front of one of the first-level grains, in front of one of the second first-level grains, in front of one of the third first-level grains, and in the first row TOV and the second row of TOV are in electrical contact with it.
  9. 如請求項8之半導體封裝,其進一步包含位於該第一層級晶粒內的複數個TSV,其中每一TSV具有約10μm或更小的最大寬度。 The semiconductor package of claim 8, further comprising a plurality of TSVs located in the first-level die, wherein each TSV has a maximum width of about 10 μm or less.
  10. 一種半導體封裝,其包含:一重佈層(RDL);位於該RDL之一背側上的一第一封裝層級之一前側,該第一封裝層級包括:一第一層級晶粒,其囊封於該RDL之該背側上的一間隙填充氧化物層中;一第一列氧化物穿孔(TOV),其自該RDL之該背側突出;一第二列氧化物穿孔(TOV),其自該RDL之該背側突出;其中該第一層級晶粒經定位成側向地介於該第一列TOV及該第二列TOV之間;及複數個第二層級晶粒,其混合結合至該第一封裝層級之一背側,該混合結合包括直接結合氧化物對氧化物表面及直接結合金屬對金屬表面。 A semiconductor package includes: a redistribution layer (RDL); a front side of a first package level on a back side of the RDL, the first package level including: a first-level die, encapsulated in A gap-fill oxide layer on the back side of the RDL; a first row of oxide vias (TOV) protruding from the back side of the RDL; a second row of oxide vias (TOV), The back side of the RDL protrudes; wherein the first-level grains are positioned laterally between the first row of TOVs and the second column of TOVs; and a plurality of second-level grains are mixed and combined to On the back side of one of the first encapsulation levels, the hybrid bonding includes a direct bonding oxide-to-oxide surface and a direct bonding metal-to-metal surface.
  11. 如請求項10之半導體封裝,其中該第一封裝層級包括位於該第一層級晶粒及該間隙填充氧化物層之一背側上的一第一封裝層級RDL,且該複數個TOV在該RDL與該第一封裝層級RDL之間提供一電連接。 The semiconductor package of claim 10, wherein the first package level includes a first package level RDL on a backside of the first level die and the gap-fill oxide layer, and the plurality of TOVs are in the RDL An electrical connection is provided with the first package level RDL.
  12. 如請求項11之半導體封裝,其中該第一封裝層級RDL包括一氧化物介電層及一金屬重佈線,且該第二層級晶粒混合結合至該氧化物介電層及該金屬重佈線。 According to the semiconductor package of claim 11, wherein the first package level RDL includes an oxide dielectric layer and a metal redistribution, and the second level die is mixed and bonded to the oxide dielectric layer and the metal redistribution.
  13. 如請求項10之半導體封裝,其進一步包含側向地鄰近於該第一層級晶粒之對立側的一第二個第一層級晶粒及一第三個第一層級晶粒,其中該第一層級晶粒、該第二個第一層級晶粒及該第三個第一層級晶粒位於該RDL上,且與其電接觸。 The semiconductor package of claim 10, further comprising a second first-level die and a third first-level die laterally adjacent to the opposite side of the first-level die, wherein the first The level grains, the second first level grains, and the third first level grains are located on the RDL and are in electrical contact therewith.
  14. 如請求項13之半導體封裝,其中該第一層級晶粒係矩形的,該第一列TOV及該第二列TOV側向地鄰近於該第一層級晶粒之一第一對側向對立側,且該第二個第一層級晶粒及該第三個第一層級晶粒側向地鄰近於該第一層級晶粒之一第二對側向對立側。 The semiconductor package of claim 13, wherein the first-level die is rectangular, the first-row TOV and the second-row TOV are laterally adjacent to a first pair of opposite sides of the first-level die. And the second first-level grain and the third first-level grain are laterally adjacent to a second pair of laterally opposite sides of one of the first-level grains.
  15. 如請求項14之半導體封裝,其中該第一層級晶粒、該第一列TOV,及該第二列TOV具有約20μm或更小的高度。 The semiconductor package of claim 14, wherein the first-level die, the first-row TOV, and the second-row TOV have a height of about 20 μm or less.
  16. 如請求項15之半導體封裝,其進一步包含位於該第一層級晶粒內的複數個TSV,其中每一TSV具有約10μm或更小的最大寬度。 The semiconductor package of claim 15, further comprising a plurality of TSVs located in the first-level die, wherein each TSV has a maximum width of about 10 μm or less.
  17. 一種形成一半導體封裝之方法,其包含:將一第一封裝層級形成於一載體基板上,該第一封裝層級包括囊封於一間隙填充氧化物層中之一第一層級晶粒,及複數個氧化物穿孔(TOV),其中該等TOV具有約20μm或更小的高度,其中將該第一封裝層級形成於該載體基板上的方法包含;將該第一層級晶粒附接至該載體基板;將該間隙填充氧化物層沈積於該第一層級晶粒上;將該間隙填充氧化物層平坦化;及將該複數個TOV形成於該間隙填充氧化物層中;將一第二層級晶粒混合結合至該第一封裝層級,其中該混合結合包括直接結合氧化物對氧化物表面及金屬對金屬表面;將該第二層級晶粒囊封於該第一封裝層級之一背側上;移除該載體基板;及將一重佈層(RDL)形成於該第一封裝層級之一前側上。 A method for forming a semiconductor package includes: forming a first package level on a carrier substrate, the first package level including a first-level crystal grain encapsulated in a gap-filled oxide layer, and a plurality of Oxide vias (TOVs), wherein the TOVs have a height of about 20 μm or less, wherein a method of forming the first package level on the carrier substrate includes attaching the first level die to the carrier A substrate; depositing the gap-fill oxide layer on the first-level crystal grains; planarizing the gap-fill oxide layer; and forming the plurality of TOVs in the gap-fill oxide layer; Die bonding to the first encapsulation level, wherein the hybrid bonding includes directly bonding an oxide-to-oxide surface and a metal-to-metal surface; encapsulating the second-level die on a back side of one of the first encapsulation levels Removing the carrier substrate; and forming a redistribution layer (RDL) on a front side of the first packaging layer.
  18. 如請求項17之方法,其進一步包含在將該第一層級晶粒附接至該載體基板之後及將該間隙填充氧化物層沈積於該第一層級晶粒上之前研磨該第一層級晶粒以減小該第一層級晶粒之厚度。 The method of claim 17, further comprising grinding the first-level die after attaching the first-level die to the carrier substrate and before depositing the gap-fill oxide layer on the first-level die. In order to reduce the thickness of the first-level crystal grains.
  19. 如請求項17之方法:其中將該第一封裝層級形成於該載體基板上包含:將一第一層級RDL形成於經平坦化之該間隙填充氧化物層及第一層級晶粒上;及將該第一層級RDL平坦化;及其中將該第二層級晶粒混合結合至該第一封裝層級包含:將該第二層級晶粒混合結合至經平坦化之該第一層級RDL。 The method of claim 17, wherein forming the first encapsulation level on the carrier substrate includes: forming a first level RDL on the gap-fill oxide layer and the first level grains after planarization; and The first-level RDL is planarized; and the second-level die is hybrid-bonded to the first package level including: the second-level die is hybrid-bonded to the first-level RDL that is planarized.
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