CN114651322A - 芯片堆叠封装结构、电子设备 - Google Patents

芯片堆叠封装结构、电子设备 Download PDF

Info

Publication number
CN114651322A
CN114651322A CN201980102104.4A CN201980102104A CN114651322A CN 114651322 A CN114651322 A CN 114651322A CN 201980102104 A CN201980102104 A CN 201980102104A CN 114651322 A CN114651322 A CN 114651322A
Authority
CN
China
Prior art keywords
dielectric layer
layer
main
chip
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201980102104.4A
Other languages
English (en)
Inventor
张宏英
朱靖华
王钿
顾识群
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of CN114651322A publication Critical patent/CN114651322A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种芯片堆叠封装结构(100)、电子设备(1)，涉及电子技术领域，用于解决如何在不简化芯片功能的情况下减小芯片的尺寸，并且保证芯片性能，降低芯片破裂的可能性的问题。芯片堆叠封装结构(100)，包括:主堆叠结构(10)，主堆叠结构(10)包括第一介电层(12)和暴露于第一介电层(12)的表面的第一凸点(13)；多个副堆叠结构(30)，副堆叠结构(30)包括第二介电层(32)和暴露于第二介电层(32)的表面的第二凸点(33)；第一介电层(12)与第二介电层(32)贴合，第一凸点(13)与第二凸点(33)电连接；第三介电层(40)，位于副堆叠结构(30)远离第一介电层(12)一侧，且与第一介电层(12)贴合。

Description

PCT国内申请，说明书已公开。

Claims (11)

  1. PCT国内申请，权利要求书已公开。
CN201980102104.4A 2019-11-12 2019-11-12 芯片堆叠封装结构、电子设备 Pending CN114651322A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/117720 WO2021092779A1 (zh) 2019-11-12 2019-11-12 芯片堆叠封装结构、电子设备

Publications (1)

Publication Number Publication Date
CN114651322A true CN114651322A (zh) 2022-06-21

Family

ID=75911795

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980102104.4A Pending CN114651322A (zh) 2019-11-12 2019-11-12 芯片堆叠封装结构、电子设备

Country Status (2)

Country Link
CN (1) CN114651322A (zh)
WO (1) WO2021092779A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023104094A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Fan-out packaging method and packaging structure of stacked chips thereof
TWI804094B (zh) * 2021-12-09 2023-06-01 南茂科技股份有限公司 晶片封裝結構及其製造方法
CN114980509B (zh) * 2022-06-14 2024-03-19 昆山国显光电有限公司 绑定连接结构、绑定连接结构的制备方法和显示模组
CN115579298A (zh) * 2022-09-28 2023-01-06 武汉新芯集成电路制造有限公司 芯片封装方法及封装芯片

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9559081B1 (en) * 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
US10290571B2 (en) * 2017-09-18 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with si-substrate-free interposer and method forming same
US10784247B2 (en) * 2017-11-15 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Process control for package formation
US10535636B2 (en) * 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
CN109950221A (zh) * 2019-04-15 2019-06-28 德淮半导体有限公司 半导体装置及其制造方法

Also Published As

Publication number Publication date
WO2021092779A1 (zh) 2021-05-20

Similar Documents

Publication Publication Date Title
EP2596689B1 (en) Microelectronic elements with post-assembly planarization
CN114651322A (zh) 芯片堆叠封装结构、电子设备
US9312239B2 (en) Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
JP4036764B2 (ja) チップ・オン・チップ・モジュール構造
KR102596758B1 (ko) 반도체 패키지
KR102147354B1 (ko) 반도체 패키지 및 그 제조 방법
KR101739939B1 (ko) 반도체 장치의 제조 방법
US11211363B2 (en) Semiconductor device having through silicon vias and manufacturing method thereof
KR20090100895A (ko) 반도체 패키지 제조 방법
JP2014512691A (ja) 積層された下向き接続ダイを有するマルチチップモジュール
CN113130464B (zh) 封装结构及其制造方法
KR20120088013A (ko) 디커플링 반도체 커패시터를 포함하는 반도체 패키지
US20220262751A1 (en) Chip Package on Package Structure, Packaging Method Thereof, and Electronic Device
KR20130007371A (ko) 반도체 패키지
US20240079288A1 (en) Semiconductor package structure and fabrication method thereof
CN115362549A (zh) 电子设备、半导体晶片、芯片封装结构及其制作方法
KR20210072181A (ko) 반도체 패키지 및 그의 제조 방법
JP2013219317A (ja) 半導体基板、これを有する半導体チップおよび積層半導体パッケージ
JP2001156248A (ja) 半導体装置
WO2023221540A1 (zh) 一种芯片组件、其制作方法、芯片及电子设备
CN220474621U (zh) 线路载板及电子封装体
WO2022251986A1 (zh) 芯片封装结构、其制备方法及终端设备
CN117320459A (zh) 堆叠式半导体封装
TW202107655A (zh) 電子封裝裝置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination