CN115362549A - 电子设备、半导体晶片、芯片封装结构及其制作方法 - Google Patents

电子设备、半导体晶片、芯片封装结构及其制作方法 Download PDF

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Publication number
CN115362549A
CN115362549A CN202080099617.7A CN202080099617A CN115362549A CN 115362549 A CN115362549 A CN 115362549A CN 202080099617 A CN202080099617 A CN 202080099617A CN 115362549 A CN115362549 A CN 115362549A
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China
Prior art keywords
layer
metal layer
semiconductor wafer
substrate
top metal
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Pending
Application number
CN202080099617.7A
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English (en)
Inventor
杨承瑜
崔江涛
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of CN115362549A publication Critical patent/CN115362549A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种电子设备、半导体晶片、芯片封装结构及其制作方法。该半导体晶片(100)包括晶片主体(110)、钝化层(120)和缓冲层(130)；晶片主体(110)包括至少一个顶层金属层(111)；钝化层(120)至少覆盖在顶层金属层(111)的外表面，缓冲层(130)至少覆盖在钝化层(120)背离顶层金属层(111)顶面的一侧，以使该半导体晶片(100)在封装过程中，封装层位于顶层金属层(111)上方的部分直接沉积在缓冲层(130)上，以缓解该封装层作用在顶层金属层(111)顶部的钝化层(120)上的封装应力，从而确保顶层金属层(111)顶部的钝化层(120)不会在封装过程中出现破裂的情况，从而保证芯片封装结构的防水性能，进而确保该芯片封装结构在HAST测试中的可靠性。

Description

PCT国内申请，说明书已公开。

Claims (28)

  1. PCT国内申请，权利要求书已公开。
CN202080099617.7A 2020-04-17 2020-04-17 电子设备、半导体晶片、芯片封装结构及其制作方法 Pending CN115362549A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/085308 WO2021208066A1 (zh) 2020-04-17 2020-04-17 电子设备、半导体晶片、芯片封装结构及其制作方法

Publications (1)

Publication Number Publication Date
CN115362549A true CN115362549A (zh) 2022-11-18

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CN202080099617.7A Pending CN115362549A (zh) 2020-04-17 2020-04-17 电子设备、半导体晶片、芯片封装结构及其制作方法

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Country Link
CN (1) CN115362549A (zh)
WO (1) WO2021208066A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117334584A (zh) * 2023-09-14 2024-01-02 中晶新源(上海)半导体有限公司 一种半导体器件的形成方法及半导体器件
CN117250067A (zh) * 2023-11-20 2023-12-19 南京泛铨电子科技有限公司 一种能填满与保护半导体试片材料分析的样本制备方法与系统

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KR100577308B1 (ko) * 2004-12-29 2006-05-10 동부일렉트로닉스 주식회사 반도체 소자 및 그의 제조 방법
US8664041B2 (en) * 2012-04-12 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method for designing a package and substrate layout
CN109755327A (zh) * 2019-01-14 2019-05-14 中国科学院上海技术物理研究所 原子尺度多层复合膜钝化的延伸波长铟镓砷探测器及方法

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