CN108122788A - 半导体封装结构的制造方法 - Google Patents

半导体封装结构的制造方法 Download PDF

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Publication number
CN108122788A
CN108122788A CN201710140203.4A CN201710140203A CN108122788A CN 108122788 A CN108122788 A CN 108122788A CN 201710140203 A CN201710140203 A CN 201710140203A CN 108122788 A CN108122788 A CN 108122788A
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China
Prior art keywords
semiconductor device
layer
electromagnetic interference
interference film
film
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CN201710140203.4A
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English (en)
Inventor
吴集锡
陈宪伟
黄立贤
杨天中
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN108122788A publication Critical patent/CN108122788A/zh
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Abstract

一种半导体封装结构的制造方法至少包括以下步骤。形成第一半导体装置。第一半导体装置包括顶表面及底表面。第一半导体装置包括金属层，且金属层具有暴露出的第一表面。在第一半导体装置的顶表面及侧壁上形成电磁干扰(Electromagnetic Interference，EMI)膜，且电磁干扰膜与金属层的暴露出的第一表面电接触。在电磁干扰膜上形成模制化合物。

Description

半导体封装结构的制造方法
技术领域
本发明实施例涉及一种半导体封装结构及其制造方法，且特别是涉及一种具有电磁干扰膜的半导体封装结构及其制造方法。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体行业经历了快速发展。在很大程度上，集成密度的这一提高是源自最小特征大小(minimum feature size)的连番减小(例如，朝子20nm节点(sub-20nm node)缩减半导体工艺节点)，而使更多的组件能够整合于所给定的区域中。随着近来对小型化、较高的速度、较大的频宽、较低的功率损耗及较少的延迟的需求的增加，对更小且更具创造性的半导体管芯封装技术的需要也随着增加。
随着半导体技术进一步发展，经堆叠的及经接合的半导体装置已成为用于进一步减小半导体装置的实体大小的有效替代形式。在经堆叠的半导体装置中，例如逻辑、存储器、处理器电路等有源电路至少部分地在分离的衬底上制造后，再实体地且电性地接合在一起以形成功能装置。此种接合工艺利用复杂的技术，故会期望对其进行改良。
发明内容
根据本发明的一些实施例，一种半导体封装结构的制造方法至少包括以下步骤。形成第一半导体装置。第一半导体装置包括顶表面及底表面。所述第一半导体装置包括金属层，且所述金属层具有暴露出的第一表面。在所述第一半导体装置的所述顶表面及所述侧壁上形成电磁干扰(Electromagnetic Interference，EMI)膜，且所述电磁干扰膜与所述金属层的所述暴露出的第一表面电接触。在所述电磁干扰膜上形成模制化合物。
附图说明
在结合附图阅读以下详细说明时，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A至图1C示出根据一些实施例的具有电磁干扰(ElectromagneticInterference，EMI)膜的半导体装置的形成。
图2A至图2C示出根据一些实施例的具有电磁干扰膜的半导体装置的形成。
图3至图9示出根据一些实施例的集成扇出型叠层式封装(Integrated Fan-OutPackage-on-Package，InFO-PoP)结构的形成。
图10至图14示出根据一些实施例的集成扇出型(Integrated Fan-Out，InFO)结构的形成。
图15至图16示出根据一些实施例的具有电磁干扰膜的集成扇出型叠层式封装结构的形成。
附图标号说明
101：第一半导体装置
103：第一衬底
105、205：切割区
107、107a、107b、207b：第一接触垫
109：第一钝化层
111：第一通孔层
111a、111b、407、411、1011、1013：第一通孔
113：第二钝化层
115：框架
117：第一粘合层
119、219、1509：侧壁
121、221、405、409、1101、1601：电磁干扰膜
123a：粘合层
123b、1603a：导电层
201：第二半导体装置
301：第一载体衬底
303：第二粘合层
305：第一聚合物层
307：第一晶种层
309：光刻胶
311：通孔
350、1500：集成扇出型叠层式封装结构
350’、1050’：区域
401：第三半导体装置
403：第四半导体装置
501：第一包封体
601a、601b、601c、1301a、1301b、1301c、1507：重布线层
603、1303：导电材料层
605：绝缘层
607、1307：钝化层
619、1319：凸块下金属
621、1321：外部连接件
701：环形结构
703：紫外线胶带
705：开口
801：背面球垫
803：背面保护层
805：第二衬底
807：第五半导体装置
809：第六半导体装置
811：第二接触垫
813、1201：第二包封体
815：第二外部连接件
817：衬底穿孔
819：打线接合
850：第一封装
901：底部填充物材料
1001：第二载体衬底
1003：第三粘合层
1005：第二聚合物层
1007：第七半导体装置
1009：第八半导体装置
1050：集成扇出型结构
1305：介电层
1503：第九半导体装置
1505：第十半导体装置
1511：表面
1513：表面准备工艺
1603b：保护层
具体实施方式
以下公开内容提供用于实作本发明的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成于第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中所述第一特征与所述第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复参考编号及/或字母。这种重复是出于简洁及清晰的目的，且不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能利用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在利用或操作中的不同取向。装置可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对性描述语可同样相应地进行解释。
图1A至图1C示出根据一些实施例的具有电磁干扰(EMI)膜121(在图1C中示出)的第一半导体装置101的形成。图2A至图2C示出根据一些实施例的具有电磁干扰(EMI)膜221的第二半导体装置201的形成。在一些实施例中，第一半导体装置101或第二半导体装置201可被并入至集成扇出型(InFO)结构、集成扇出型叠层式封装(InFO-PoP)结构、或其他类型的封装结构中。
参照图1A至图1C，图1A示出在单体化(singulation)之前的第一半导体装置101。在单体化之前，每一第一半导体装置101均被切割区(scribe region)105隔开。图1A示出两个第一半导体装置101作为说明性实例，但在其他实施例中，可一起形成多于两个第一半导体装置101，且每一第一半导体装置101分别被切割区105隔开。第一半导体装置101可为出于预期目的而设计的半导体装置，例如，存储器管芯(例如，动态随机存取存储器(dynamicrandom access memory，DRAM)管芯)、逻辑管芯、集成电路、中央处理器(centralprocessing unit，CPU)管芯、或其组合等。
在一些实施例中，第一半导体装置101包括第一衬底103、第一接触垫107、第一钝化层109、第一通孔层111以及第二钝化层113。第一衬底103可为晶片或其他衬底，且可为例如硅、锗、或砷化镓等半导体材料，可为经掺杂的或未经掺杂的、或可为绝缘体上硅(silicon-on-insulator，SOI)、氧化硅(SiO2)或其他绝缘材料、或其他材料。一般来说，绝缘体上硅衬底是例如硅、锗、硅锗、绝缘体上硅、绝缘体上硅锗(silicon germanium oninsulator，SGOI)、或其组合等半导体材料的层。第一衬底103也可为多层式衬底、梯度(gradient)衬底、混合取向(hybrid orientation)衬底或其他类型的衬底或晶片。
在一些实施例中，第一衬底103可包括有源装置(未示出)及可选的金属层(未示出)。第一半导体装置101的有源装置可包括例如晶体管、电容器、电阻器、电感器(inductor)等各种各样的有源装置及无源装置，且可用于产生第一半导体装置101的设计所期望的结构特征及功能特征。第一衬底103上或内的有源装置可利用任意合适的方法来形成。可选的金属层(未示出)可形成于有源装置上，且被设计成与各种有源装置连接以形成功能电路系统。在一些实施例中，金属层由介电质(dielectric)及导电材料的交替的层所形成，且可通过任意合适的工艺(例如，沉积、镶嵌、双重镶嵌等)形成。在一些实施例中，金属层包括一层或多层重布线层(redistribution layer，RDL)。
图1A也示出通过第一粘合层117而安装至框架115的第一半导体装置101。框架115可为例如硅系材料(例如，玻璃或氧化硅)或其他材料(例如，氧化铝、金属、陶瓷、聚合物、这些材料中的任意组合等)。第一粘合层117可为例如环氧树脂(epoxy resin)、酚树脂(phenol resin)、丙烯酸类橡胶(acrylic rubber)、硅填料、或其组合等管芯贴合膜(dieattach film，DAF)，且第一粘合层117可利用叠层(lamination)技术而被涂布。然而，可利用任意其他合适的替代材料及形成技术作为另外一种选择。在一些实施例中，第一衬底103在安装于框架115之前已被薄化。所述薄化可例如利用机械研磨(mechanical grinding)或化学机械抛光(chemical mechanical polishing，CMP)工艺来执行，由此利用化学蚀刻剂及研磨剂(abrasive)来反应掉及研磨掉第一衬底103。
第一接触垫107可形成于第一半导体装置101的金属层或第一半导体装置101的有源装置上，且与第一半导体装置101的金属层或第一半导体装置101的有源装置电接触。作为说明性实例，图1A至图1C示出总称为第一接触垫107的第一接触垫107a及第一接触垫107b。其他实施例可包括更多或更少的第一接触垫107。在一些实施例中，第一接触垫107为铝，但也可利用例如铜、铝铜(AlCu)、或其它材料等其他导电材料。在一些实施例中，首先利用例如溅镀等沉积工艺来形成导电材料层。接着通过合适的工艺(例如，光刻掩模及蚀刻)来移除部分导电材料层以形成第一接触垫107。在一些实施例中，第一接触垫107为凸块下金属(under bump metallization，UBM)。
第一钝化层109可在任意金属层及第一接触垫107上且形成于第一衬底103上。第一钝化层109可由例如氧化硅、氮化硅、低k介电质(例如，掺杂碳的氧化物)、极低k介电质(例如，掺杂多孔碳的二氧化硅)、其组合等一或多种合适的介电材料制成。在一些实施例中，第一钝化层109可为聚苯并恶唑(polybenzoxazole，PBO)，但也可利用例如聚酰亚胺(polyimide)或聚酰亚胺衍生物等任意合适的材料来形成。第一钝化层109可利用例如旋转涂布(spin-coating)工艺来形成。在其他实施例中，第一钝化层109可通过例如化学气相沉积(chemical vapor deposition，CVD)等工艺形成。可利用合适的光刻及蚀刻工艺而在第一接触垫107上形成第一钝化层109中的开口。
第一通孔层111形成于第一接触垫107上并与第一接触垫107电连接。作为说明性实例，图1A至图1C示出形成于第一接触垫107a上的第一通孔111a及形成于第一接触垫107b上的第一通孔111b。第一通孔层111的其他实施例可包括更多或更少的第一通孔。第一通孔层111可被形成为提供第一接触垫107与外部特征之间的电接触的导电区。举例来说，第一通孔层111的区域可连接至后续形成于第一半导体装置101上的重布线层。(参见例如图6至图9中所示的重布线层601a-c)。第一通孔层111可由例如铜等导电材料形成，但也可利用例如镍、金、焊料、金属合金、其组合等其他导电材料形成。第一通孔层111可通过任意合适的工艺(例如，沉积、镶嵌、双重镶嵌等)来形成。在一些实施例中，第一通孔层111可利用例如电镀等工艺来形成。在一些实施例中，第一通孔层111的一部分延伸至切割区105中，如同在图1A中示出的第一通孔111b。
第二钝化层113可形成于第一钝化层109及第一通孔层111上。第二钝化层113可由以上针对第一钝化层109所阐述的材料或工艺形成。第二钝化层113可为与第一钝化层109相同的材料或与第一钝化层109不同的材料。在一些实施例中，第一半导体装置101可具有更多的钝化层及/或金属层，且在一些实施例中，第一半导体装置101可具有更少的钝化层及/或金属层。
图1B示出在单体化工艺之后的第一半导体装置101。所述单体化工艺移除切割区105并使各第一半导体装置101隔开。在一些实施例中，所述单体化工艺可通过利用锯片(saw blade)切断第一衬底103、第一钝化层109及第二钝化层113来执行。所述单体化工艺也可切断第一粘合层117的一部分或全部。如图1A至图1B中所示，单体化工艺也切断第一通孔层111延伸至切割区105中的部分，从而暴露出第一通孔层111的侧壁。在图1B中示例性地示出第一通孔111b的暴露出的侧壁119，但其他实施例可包括多于一个暴露出的侧壁。在单体化之后，第一通孔层111的暴露出的侧壁可与第一衬底103的侧壁实质上共面。如所属领域的普通技术人员将认识到，利用锯片来进行单体化工艺仅为一个说明性实施例且并非旨在进行限制。可利用任意合适的技术来执行第一单体化工艺，例如利用一或多种蚀刻。可利用这些及任意其他合适的技术来使第一半导体装置101单体化。
图1C示出形成于单体化的第一半导体装置101上的电磁干扰(ElectromagneticInterference，EMI)膜121。在一些实施例中，电磁干扰膜121由单一材料的共形(conformal)层所形成，而在一些实施例中，电磁干扰膜121由多个材料的多层共形层所形成。电磁干扰膜121形成于第一半导体装置101上以屏蔽第一半导体装置101不受电磁干扰。
在一些实施例中，电磁干扰膜121由粘合层123a与导电层123b形成。粘合层123a共形地形成于第一半导体装置101的暴露出的表面上。粘合层123a可改善导电层123b对第一半导体装置101的粘合。在一些实施例中，粘合层123a可为例如不锈钢(stainless steel，SUS)、钛、或其他导电金属等导电金属。粘合层123a可利用合适的技术来形成，例如溅镀、物理气相沉积(physical vapor deposition，PVD)、化学气相沉积(CVD)、原子层沉积(atomiclayer deposition，ALD)等沉积工艺、喷射涂布(spray coating)、无电镀敷(electrolessplating)等。在一些实施例中，粘合层123a被形成为具有介于约0.05μm与约1μm之间的厚度，例如约0.1μm。
导电层123b共形地形成于粘合层123a上。在一些实施例中，导电层123b可为例如铜、银、钯/铜合金等材料。导电层123b可利用例如溅镀、物理气相沉积、化学气相沉积、原子层沉积、镀敷、或喷射等工艺来形成。在一些实施例中，导电层123b被形成为具有介于约1μm与约100μm之间的厚度，例如约10μm。
在一些实施例中，电磁干扰膜121包括形成于导电层123b上的附加保护层(例如，不锈钢层)，以保护导电层123b。在一些实施例中，电磁干扰膜121不包括形成于导电层123b上的附加保护层。举例来说，在一些实施例中，在导电层123b上直接地形成模制化合物、包封体或底部填充物(underfill)，以保护导电层123b。在例如这些实施例中，可能不需要在导电层123b上的附加保护层。参见图5至图9，会在以下更加详细地论述在电磁干扰膜121上直接形成模塑化合物。
由于第一通孔层111的第一通孔111b具有暴露出的侧壁119，因此电磁干扰膜121可经由暴露出的侧壁119而与第一通孔111b实体接触及电接触。如此一来，电磁干扰膜121可在第一通孔111b处电连接至第一半导体装置101的电压。举例来说，电磁干扰膜121可经由第一通孔111b而电连接至第一半导体装置101的参考电压(reference voltage)或接地电压(ground)。在其他实施例中，电磁干扰膜121可经由多个第一通孔的暴露出的侧壁或其他导电特征而连接至第一半导体装置101。通过将电磁干扰膜121电连接至装置，来自电磁干扰膜121的电磁屏蔽可得到改善。
在沉积电磁干扰膜121之后，可将每一第一半导体装置101从框架115移除且并入至例如集成扇出型(InFO)结构、集成扇出型叠层式封装(InFO-PoP)结构、或其他类型的封装结构等封装中。可通过例如拾取及放置(pick-and-place)工艺等合适的工艺来从框架115移除第一半导体装置101。在一些实施例中，拾取及放置工艺可将电磁干扰膜121贴合至第一半导体装置101的部分从电磁干扰膜121贴合至框架115的部分断开(sever)。
然而，如所属领域的普通技术人员将认识到，上述用于形成第一半导体装置101的工艺仅为一种说明，且并非意在将所述实施例限制至这一确切工艺。相反来说，所阐述的工艺旨在仅为说明性的，且可利用任意合适形成第一半导体装置101的工艺作为另外一种选择。所有合适的工艺皆包含于本实施例的范围内。
现转至图2A至图2C，第二半导体装置201与第一半导体装置101相似。第二半导体装置201可为出于预期目的而设计的半导体装置，例如，存储器管芯(例如，动态随机存取存储器管芯)、逻辑管芯、集成电路、中央处理器(CPU)管芯、或其组合等。然而，第二半导体装置201的第一通孔层211并未延伸至切割区205中。此外，将第一接触垫207形成为使得第一接触垫207延伸至切割区205中，如图2A的第一接触垫207b所示出。因此，如图2B中所示，在单体化之后，第一接触垫207b将具有暴露出的侧壁219。在单体化之后，第一接触垫207b的暴露出的侧壁可与第一衬底103的侧壁实质上共面。图2C示出在第二半导体装置201的表面上已形成共形的电磁干扰膜211之后的第二半导体装置201。电磁干扰膜221可与以上针对图1C所阐述的电磁干扰膜121相似。举例来说，电磁干扰膜221可由粘合层123a及导电层123b形成。
由于第一接触垫207b具有暴露出的侧壁219，因此电磁干扰膜221可经由暴露出的侧壁219而与第一接触垫207b实体接触及电接触。如此一来，电磁干扰膜221可在第一接触垫207b处电连接至第二半导体装置201的电压。在其他实施例中，电磁干扰膜221可经由多个第一接触垫207的暴露出的侧壁而连接至第二半导体装置201。在其他实施例中，电磁干扰膜221可经由一或多个第一接触垫207的暴露出的侧壁及经由一或多个第一通孔的暴露出的侧壁(如以上针对图1C所阐述)而连接至第二半导体装置201。通过将电磁干扰膜221电连接至装置，来自电磁干扰膜221的电磁屏蔽可得到改善。
图3至图9示出根据一些实施例的集成扇出型叠层式封装结构350的形成。集成扇出型叠层式封装结构350可包括如同以上针对图1A至图1C及图2A至图2C所阐述的一或多个半导体装置。现参照图3，图3示出第一载体衬底301及位于第一载体衬底301上的第二粘合层303、第一聚合物层305以及第一晶种层307。区域350’指示为将形成有单独的集成扇出型叠层式封装结构350的区域。第一载体衬底301可为例如玻璃或氧化硅等硅系材料、例如氧化铝等其他材料、这些材料的组合等。第一载体衬底301在工艺变异(process variation)内是平坦的，以适用于例如第一半导体装置101、第二半导体装置201、或一或多个其他半导体装置(未在图3中示出而在以下针对图4至图9进行示出及论述)等半导体装置的贴合。
第二粘合层303形成于第一载体衬底301上以帮助粘着上覆结构(例如，第一聚合物层305)。在一些实施例中，第二粘合层303可包括紫外线胶(ultraviolet glue)，所述紫外线胶在暴露至紫外光时会失去其粘合性质。然而，也可利用例如压敏粘合剂(pressuresensitive adhesive)、可辐射固化粘合剂(radiation curable adhesive)、环氧树脂(epoxy)、其组合等其他类型的粘合剂。第二粘合层303可以以在压力下易于发生变形的半液体形式(semi-liquid form)或胶体形式(gel form)而形成至第一载体衬底301上。
第一聚合物层305被放置于第二粘合层303上且可为贴合的半导体装置提供保护。在一些实施例中，第一聚合物层305可为聚苯并恶唑(PBO)，但也可利用例如聚酰亚胺或聚酰亚胺衍生物、阻焊剂(Solder Resistance，SR)或味之素构成膜(Ajinomoto build-upfilm，ABF)等任意合适的材料作为另外一种选择。可利用例如旋转涂布工艺等来将第一聚合物层305形成为介于约2μm与约15μm之间的厚度，例如约5μm，但也可利用任意合适的方法及厚度作为另外一种选择。
第一晶种层307形成于第一聚合物层305上。在一些实施例中，第一晶种层307是导电材料的薄层，且在后续处理步骤期间能帮助形成较厚的层。在一些实施例中，第一晶种层307是被约厚的铜层覆盖的约厚的钛层。可利用例如溅镀、蒸镀、等离子体增强型化学气相沉积(plasma enhanced chemical vapor deposition)工艺或其他工艺等工艺来形成第一晶种层307。在一些实施例中，第一晶种层307可具有介于约0.3μm与约1μm之间的厚度，例如约0.5μm。
图3也示出在第一晶种层307上的光刻胶309的形成及图案化。在一些实施例中，光刻胶309可利用旋转涂布技术或其他技术而形成于第一晶种层307上。在一些实施例中，光刻胶309被形成为介于约50μm与约250μm之间的厚度，例如约120μm。可通过一或多种合适的光刻技术来对光刻胶309进行图案化。
在一些实施例中，形成至光刻胶309中的图案是用于形成通孔311的图案。通孔311可位于如图4至图9中所示的随后贴合的半导体装置的不同侧上，但在其他实施例中，通孔311也可位于任意合适的排列位置。在一些实施例中，通孔311是由例如铜、钨、其他导电金属等一或多种导电材料而形成于光刻胶309内。举例来说，可通过电镀、无电镀敷等来形成通孔311。
在形成通孔311之后，可利用合适的移除工艺来移除光刻胶309(未在图3中示出，但示出于以下图4中)。可利用例如等离子体灰化(plasma ashing)、湿剥落(wet strip)或任意其他合适的工艺等合适的移除工艺来移除光刻胶。移除光刻胶309可暴露出第一晶种层307的下面的部分。
可移除第一晶种层307的暴露出的部分(未在图3中示出，但示出于以下图4中)。在一些实施例中，可通过湿式蚀刻工艺或干式蚀刻工艺或者其他合适的工艺来移除第一晶种层307的暴露出的部分(例如，未被通孔311覆盖的部分)。在移除第一晶种层307的暴露出的部分之后，第一聚合物层305的一部分被暴露于各通孔311之间。
图4示出放置至第一聚合物层305上的第三半导体装置401及第四半导体装置403。第三半导体装置401或第四半导体装置403可为出于预期目的而设计的半导体装置，例如存储器管芯(例如，动态随机存取存储器管芯)、逻辑管芯、集成电路、中央处理器(CPU)管芯、或其组合等。在一些实施例中，第三半导体装置401及第四半导体装置403与前面阐述的第一半导体装置101及/或第二半导体装置201相似。举例来说，第三半导体装置401可被连接至第一通孔407的电磁干扰膜405覆盖，且第四半导体装置403可被连接至第一通孔411的电磁干扰膜409覆盖。电磁干扰膜405或电磁干扰膜409可与以上阐述的电磁干扰膜121相似或不同。在一些实施例中，每一集成扇出型叠层式封装结构内放置有一个半导体装置或多于两个半导体装置。在一些实施例中，一或多个半导体装置可能不会被电磁干扰膜覆盖或可能不具有连接至电磁干扰膜的第一通孔或接触垫。第三半导体装置401或第四半导体装置403可通过粘合层(未示出)而贴合至第一聚合物层305。粘合层可形成于第三半导体装置401及/或第四半导体装置403上，且粘合层可与图1A至图2C中所示的第一粘合层117相似。在一些实施例中，可利用拾取及放置工艺而将半导体装置放置于第一聚合物层305上。然而，也可利用放置半导体装置的任意其他合适的方法。
图5示出通孔311、第三半导体装置401及第四半导体装置403的包封及平坦化。可利用任意合适的方法来将第一包封体501形成于通孔311、第三半导体装置401及第四半导体装置403上。第一包封体501例如为聚酰亚胺、聚苯硫醚(polyphenylene sulfide，PPS)、聚醚醚酮(polyetheretherketone，PEEK)、聚醚砜(polyethersulfone，PES)、耐热水晶树脂(heat resistant crystal resin)、或其组合等模制化合物树脂。在一些实施例中，第一包封体501在形成之后固化。
图5也示出第一包封体501的平坦化。可利用机械研磨工艺、化学机械抛光(CMP)工艺、或其他工艺来执行所述平坦化。在一些实施例中，所述平坦化可研磨掉第一包封体501、部分的通孔311、第三半导体装置401的电磁干扰膜405的顶表面及部分的第三半导体装置401、以及第四半导体装置403的电磁干扰膜409的顶表面及部分的第四半导体装置403。所述平坦化暴露出通孔311的顶表面、第三半导体装置401的第一通孔407、及第四半导体装置403的第一通孔411以进行进一步处理。由此，如图5中所示，通孔311、第三半导体装置401及第四半导体装置403可具有也与第一包封体501齐平的平坦的表面。如图5至图9中所示，在一些实施中，第一包封体501覆盖并保护覆盖半导体装置的电磁干扰膜。
图6示出在通孔311、第三半导体装置401、及第四半导体装置403上形成重布线层(RDL)601a-c以连接通孔311、第三半导体装置401、第四半导体装置403及外部连接件621。举例来说，重布线层601a-c可将通孔311连接至外部连接件621、将通孔311连接至第三半导体装置401及/或第四半导体装置403、将外部连接件621连接至第三半导体装置401及/或第四半导体装置403、及/或将第三半导体装置401连接至第四半导体装置403。图6是重布线层601a-c的说明性剖视图，且由于某些特征可能不存在于示例性横截面中，因此不示出重布线层601a-c的所有特征。举例来说，图6中所示的横截面可不示出重布线层601a-c的所有导电特征且可不示出导电特征之间的所有内连线。图6至图9中所示的重布线层601a-c包括3个重布线层601a、601b及601c，但在其他实施例中，重布线层601a-c可包括更多或更少的重布线层。在一些实施例中，重布线层601a-c是由绝缘材料及导电材料的交替的层所形成且可通过任意合适的工艺形成。在图6中示出示例性绝缘层605及示例性导电材料层603。
钝化层607可形成于重布线层601a-c中的最顶部重布线层601c上。在一些实施例中，钝化层607可为例如聚苯并恶唑、聚酰亚胺、聚酰亚胺衍生物、或其他介电材料等聚合物。可穿过钝化层607形成开口以暴露出部分的最顶部重布线层601c。钝化层607中的开口使得最顶部重布线层601c与凸块下金属(UBM)619之间能够接触。可利用合适的光刻掩模及蚀刻工艺来形成开口，但也可利用任意合适的工艺。
可通过在钝化层607上并沿穿过钝化层607的开口的内侧形成一或多个导电层来生成凸块下金属619。可利用例如电化学镀敷等镀敷工艺来执行每一导电层的形成，但也可利用例如溅镀、蒸镀、或等离子体增强型化学气相沉积工艺等其他形成工艺。一旦形成所期望的层，则可接着通过合适的光刻掩模及蚀刻工艺来移除层的部分以移除过量的材料。外部连接件621形成于凸块下金属619上且可向最顶部重布线层601c提供外部电连接点。外部连接件621可为例如接触凸块(contact bump)、焊料凸块、或其他类型的连接特征。
图7示出将第一载体衬底301从通孔311、第三半导体装置401及第四半导体装置403剥离(debonding)。在一些实施例中，外部连接件621可贴合至环形结构701。环形结构701可为金属环，用以在所述剥离工艺期间及在所述剥离工艺之后为结构提供支撑及稳定性。在一些实施例中，外部连接件621利用紫外线胶带(ultraviolet tape)703而贴合至环形结构701，但也可利用任意其他合适的粘合剂、胶带、框架、或贴合物(attachment)。一旦外部连接件621贴合至环形结构701，则第一载体衬底301可从第一聚合物层305剥离。图7也示出将第一聚合物层305图案化以形成开口705并暴露出通孔311的第一晶种层307。在一些实施例中，可利用激光钻孔(laser drilling)、光刻技术、或其他技术来将第一聚合物层305图案化。
图8示出放置于开口705内以保护暴露出的通孔311的背面球垫801。在一些实施例中，背面球垫801可包括例如焊料膏(solder on paste)或氧化保焊剂(oxygen solderprotection，OSP)等导电材料，但也可利用任意合适的材料。在一些实施例中，可利用模版喷刷(stencil)或其他技术来形成背面球垫801，且接着可对背面球垫801进行回焊以形成凸块形状。
图8也示出背面球垫801上的背面保护层803的形成及图案化。背面保护层803有效地密封背面球垫801与通孔311之间的接合处以防止受潮。在一些实施例中，背面保护层803可为例如聚苯并恶唑、阻焊剂(SR)、叠层化合物(lamination Compound，LC)胶带、味之素构成膜(ABF)、非导电膏(non-conductive paste，NCP)、非导电膜(non-conductive film，NCF)、图案化底部填充物(patterned underfill，PUF)、翘曲改善粘合剂(warpageimprovement adhesive，WIA)、液体模制化合物V9、或其组合等保护材料。然而，也可利用任意合适的材料。可利用例如丝网印刷(screen printing)、叠层、旋转涂布等工艺来形成背面保护层803。在形成之后，背面保护层803可被图案化以暴露出背面球垫801。可利用激光钻孔、光刻技术、或其他合适的技术来将背面保护层803图案化。
图8也示出背面球垫801接合至第一封装850。在一些实施例中，第一封装850可包括第二衬底805、第五半导体装置807、第六半导体装置809(接合至第五半导体装置807)、第二接触垫811、第二包封体813及第二外部连接件815。在一些实施例中，第二衬底805可为包括用于将第五半导体装置807及第六半导体装置809连接至背面球垫801的衬底穿孔(substrate via)817的封装衬底。在一些实施例中，第二衬底805可为插板(interposer)、经掺杂的或未经掺杂的硅衬底、或绝缘体上硅(SOI)衬底的有源层。第二衬底805也可为玻璃衬底、陶瓷衬底、聚合物衬底、或可提供合适的保护及/或内连线功能性的任意其他衬底。
第五半导体装置807可为出于预期目的而设计的半导体装置，例如存储器管芯(例如，动态随机存取存储器管芯)、逻辑管芯、中央处理器(CPU)管芯、或其组合等。在一些实施例中，第五半导体装置807包括例如晶体管、电容器、电感器、电阻器、第一金属层(未示出)等集成电路装置。在一些实施例中，第五半导体装置807被设计且被制造成与第三半导体装置401或第四半导体装置403共同或同时运转。
第六半导体装置809可与第五半导体装置807相似。举例来说，第六半导体装置809可为出于预期目的而设计的半导体装置(例如，动态随机存取存储器管芯)，且包括用于所需要的功能性的集成电路装置。在一些实施例中，第六半导体装置809被设计成与第三半导体装置401或第四半导体装置403共同或同时运转。
第六半导体装置809可接合至第五半导体装置807。在一些实施例中，第六半导体装置809例如通过利用粘合剂而仅与第五半导体装置807实体地接合。在此实施例中，第六半导体装置809及第五半导体装置807可利用打线接合(wire bond)819而电连接至第二衬底805，但也可利用任意合适的电接合作为另外一种选择。
作为另外一种选择，第六半导体装置809可在实体上及电性上均与第五半导体装置807接合。在此实施例中，第六半导体装置809可包括第六外部连接件(未在图8中分离地示出)，所述第六外部连接件与第五半导体装置807上的第七外部连接件(未在图8中分离地示出)连接以使第六半导体装置809与第五半导体装置807内连。
第二接触垫811可形成于第二衬底805上以在第五半导体装置807与第二外部连接件815之间形成电连接。在一些实施例中，第二接触垫811可形成于第二衬底805内的电布线(electrical routing)(例如，衬底穿孔817)上且与其电接触。
第二包封体813可用于包封并保护第五半导体装置807、第六半导体装置809及第二衬底805。在一些实施例中，第二包封体813可为例如聚酰亚胺、聚苯硫醚(PPS)、聚醚醚酮(PEEK)、聚醚砜(PES)、耐热水晶树脂、或其组合等模制化合物树脂。在一些实施例中，第二包封体813可在形成之后被固化。
在一些实施例中，第二外部连接件815可被形成以在第二衬底805与背面球垫801之间提供外部连接。第二外部连接件815可为例如微凸块或受控塌陷芯片连接(controlledcollapse chip connection，C4)凸块等接触凸块且可包含例如锡、银、铜、或其他合适的材料等材料。在形成第二外部连接件815之后，使第二外部连接件815与背面球垫801对齐并将第二外部连接件815放置成与背面球垫801实体接触，且执行接合工艺。举例来说，在第二外部连接件815为焊料凸块的一些实施例中，接合工艺可包括回焊工艺。
图9示出在从环形结构701剥离及单体化之后的集成扇出型叠层式封装结构350。在剥离及单体化之前，可将底部填充物材料901注射于或者形成于相邻的各第一封装850之间的空间中及第一封装850与背面保护层803之间的空间中。在一些实施例中，底部填充物材料901可为分配(dispense)于第一封装850与背面保护层803之间的液体环氧树脂，且接着被固化以变硬。在一些实施例中，第二电磁干扰膜(未示出)可形成于集成扇出型叠层式封装结构350上。
然而，如所属领域的普通技术人员将认识到，上述用于形成集成扇出型叠层式封装结构350的工艺仅为一种说明，且并非意在将所述实施例限制至这一确切工艺。相反来说，所阐述的工艺旨在仅为说明性的，且可利用用于形成及封装例如第一半导体装置101、第二半导体装置201、第三半导体装置401或第四半导体装置403等具有电磁干扰膜的半导体装置的任意合适的工艺作为另外一种选择。在一些实施例中，例如第一半导体装置101、第二半导体装置201、第三半导体装置401或第四半导体装置403等具有电磁干扰膜的半导体装置可并入至不具有通孔311的集成扇出型结构中。所有合适的工艺、封装、及结构皆包含于本实施例的范围内。
图10至图14示出根据一些实施例的集成扇出型结构1050的形成。集成扇出型结构1050可包括例如图10至图14中所示的示例性第七半导体装置1007及示例性第八半导体装置1009等一或多个半导体装置。在一些实施例中，在每一集成扇出型结构1050内放置有一个半导体装置或多于两个半导体装置。在一些实施例中，与图1B中所示的第一半导体装置101及/或图2B中所示的第二半导体装置201相似，所述一或多个半导体装置可具有第一通孔或接触垫，且所述第一通孔或接触垫具有暴露出的侧壁。举例来说，第七半导体装置1007包括具有暴露出的侧壁的第一通孔1011，且第八半导体装置1009包括具有暴露出的侧壁的第一通孔1013。在一些实施例中，半导体装置中的一个或多个在被放置于集成扇出型结构1050内之前不会被电磁干扰膜覆盖。举例来说，图10中所示的第七半导体装置1007及第八半导体装置1009未被电磁干扰膜覆盖。
现参照图10，图10示出具有第三粘合层1003及第二聚合物层1005的第二载体衬底1001。区域1050’指示为将形成有集成扇出型结构1050的区域。在一些实施例中，第二载体衬底1001可与图3至图6中所示的第一载体衬底301相似。举例来说，第二载体衬底1001可包括例如针对第一载体衬底301所阐述的材料。
第三粘合层1003形成于第二载体衬底1001上。在一些实施例中，第三粘合层1003可与前面阐述的第二粘合层303相似。第二聚合物层1005放置于第三粘合层1003上。在一些实施例中，第二聚合物层1005可与前面阐述的第一聚合物层305相似。在一些实施例中，第七半导体装置1007及第八半导体装置1009可利用拾取及放置工艺而放置至第二聚合物层1005上。然而，也可利用放置半导体装置的任意其他合适的方法。
图11示出形成于第七半导体装置1007的表面、第八半导体装置1009的表面及第二聚合物层1005的表面上的共形电磁干扰膜1101。电磁干扰膜1101可与前面阐述的电磁干扰膜121或电磁干扰膜221相似。举例来说，电磁干扰膜1101可由形成于粘合层上的导电层所形成。在一些实施例中，电磁干扰膜1101由形成于不锈钢粘合层上的铜导电层所形成。
由于第七半导体装置1007的第一通孔1011及第八半导体装置1009的第一通孔1013具有暴露出的侧壁，因此电磁干扰膜1101可与第七半导体装置1007及第八半导体装置1009实体接触及电接触。通过将电磁干扰膜1101电连接至第七半导体装置1007及第八半导体装置1009，来自电磁干扰膜1101的电磁屏蔽可得到改善。
图12示出第七半导体装置1007及第八半导体装置1009的包封及平坦化。可利用任意合适的方法来在第七半导体装置1007及第八半导体装置1009上形成第二包封体1201。第二包封体1201可为例如聚酰亚胺、聚苯硫醚(PPS)、聚醚醚酮(PEEK)、聚醚砜(PES)、耐热水晶树脂、或其组合等模制化合物树脂。在一些实施例中，第二包封体1201在形成之后被固化。
图12也示出第二包封体1201的平坦化。所述平坦化可利用机械研磨工艺、化学机械抛光(CMP)工艺、或其他工艺来执行。在一些实施例中，所述平坦化可研磨掉第二包封体1201、第七半导体装置1007及第八半导体装置1009上的电磁干扰膜1101的顶表面以及部分的第七半导体装置1007及部分的第八半导体装置1009。所述平坦化会暴露出第七半导体装置1007的第一通孔1011的顶表面及第八半导体装置1009的第一通孔1013的顶表面以进行进一步处理。如此一来，如图12中所示，第七半导体装置1007的第一通孔1011及第八半导体装置1009的第一通孔1013可具有也与第二包封体1201齐平的平坦的表面。如图12至图14中所示，在一些实施例中，第二包封体1201覆盖并保护电磁干扰膜1101。
图13示出在第七半导体装置1007及第八半导体装置1009上形成重布线层(RDL)1301a-c。图13至图14中所示的重布线层1301a-c包括3个重布线层1301a、1301b及1301c，但在其他实施例中，重布线层1301a-c可包括更多或更少的重布线层。在一些实施例中，重布线层1301a-c由介电质及导电材料的交替的层所形成且可通过任意合适的工艺(例如，沉积、镶嵌、双重镶嵌等)来形成。在图13中示出示例性介电层1305及示例性导电材料层1303。
钝化层1307可形成于重布线层1301a-c中的最顶部重布线层1301c上。在一些实施例中，钝化层1307可为例如聚苯并恶唑、聚酰亚胺、聚酰亚胺衍生物、或其他介电材料等聚合物。可穿过钝化层1307形成开口以暴露出部分的最顶部重布线层1301c。钝化层1307中的开口使得最顶部重布线层1301c与凸块下金属(UBM)1319之间能够接触。可利用合适的光刻掩模及蚀刻工艺来形成所述开口，但也可利用任意合适的工艺。可通过在钝化层1307上并沿穿过钝化层1307的开口的内侧形成一或多个导电层来生成凸块下金属1319。外部连接件1321形成于凸块下金属1319上且可向最顶部重布线层1301c提供外部电连接点。外部连接件1321可为例如接触凸块、焊料凸块、或其他类型的连接特征。
图14示出在单体化之后的集成扇出型结构1050。与图7中所示的实施例相似，在一些实施例中，在单体化之前，第二载体衬底1001可从第二聚合物层1005剥离，且外部连接件1321可贴合至环形结构。在一些实施例中，也可移除第二聚合物层1005(未示出)。在一些实施例中，可将模制化合物、包封体、介电膜、半导体装置或封装安置于集成扇出型结构1050上(未示出)。在一些实施例中，可对电磁干扰膜1101的部分进行附加电连接。
然而，如所属领域的普通技术人员将认识到，上述用于形成集成扇出型结构1050的工艺仅为一种说明，且并非意在将所述实施例限制至这一确切工艺。相反来说，所阐述的工艺旨在仅为说明性的，且可利用任意合适形成及封装例如第七半导体装置1007及第八半导体装置1009的半导体装置的工艺作为另外一种选择。所有合适的工艺、封装、及结构皆包含于本实施例的范围内。
图15至图16示出根据一些实施例的集成扇出型叠层式封装结构1500的形成。在一些实施例中，集成扇出型叠层式封装结构1500可与图9中所示的集成扇出型叠层式封装结构350相似，且通过相似的工艺来形成。举例来说，集成扇出型叠层式封装结构1500可包括放置于集成扇出型叠层式封装结构1500内的一或多个半导体装置。所述一或多个半导体装置可与图1A至图1C中所示的第一半导体装置101、图2A至图2C中所示的第二半导体装置201、图10至图14中所示的第七半导体装置1007、或图10至图14中所示的第八半导体装置1009相似，但也可在其他实施例中利用其他半导体装置。半导体装置可被电磁干扰膜覆盖或可不被电磁干扰膜覆盖。图15至图16示出放置于集成扇出型叠层式封装结构1500内的示例性第九半导体装置1503及示例性第十半导体装置1505。在一些实施例中，在集成扇出型叠层式封装结构1500内放置有一个半导体装置或多于两个半导体装置。
集成扇出型叠层式封装结构1500包括重布线层1507。在一些实施例中，重布线层1507的一或多个导电材料层可暴露于集成扇出型叠层式封装结构1500的侧壁处。在图15至图16中示出重布线层1507的导电材料层的示例性暴露出的侧壁1509。在图15至图16中也示出包括暴露出的侧壁1509的集成扇出型叠层式封装结构1500的暴露出的表面1511。暴露出的表面1511可包括模制化合物、包封体、介电层、导电层、或者其他材料或层的暴露出的表面。
图15也示出被施加至集成扇出型叠层式封装结构1500的暴露出的表面1511的表面准备工艺1513。表面准备工艺1513包括可改善后续形成于部分的暴露出的表面1511上的导电层的粘合的一或多个工艺。导电层可为电磁干扰膜的一部分，且以下针对图16更详细地阐述实施例。
在一些实施例中，表面准备工艺1513包括富氧处理(oxygen enrichmenttreatment)及/或表面粗糙度处理(surface roughness treatment)。在一些实施例中，所述富氧处理可包括将暴露出的表面1511暴露至氧等离子体工艺(oxygen plasmaprocess)。在一些实施例中，富氧处理可包括将暴露出的表面1511暴露至含有过氧化氢(H2O2)的溶液。在一些实施例中，表面粗糙度处理可包括将暴露出的表面1511暴露至氩等离子体工艺(argon plasma process)。在一些实施例中，表面粗糙度处理可包括将暴露出的表面1511暴露至蚀刻剂。表面准备工艺1513可包括这些处理或其他处理中的一或多者或其组合等。
图16示出形成于集成扇出型叠层式封装结构1500的暴露出的表面1511上的电磁干扰膜1601。在一些实施例中，电磁干扰膜1601是由单一材料的共形层所形成，而在一些实施例中，电磁干扰膜1601是由多个材料的多层共形层形成。电磁干扰膜1601形成于集成扇出型叠层式封装结构1500上以屏蔽集成扇出型叠层式封装结构1500不受电磁干扰。
在一些实施例中，电磁干扰膜1601由导电层1603a及保护层1603b形成。导电层1603a共形地形成于集成扇出型叠层式封装结构1500的暴露出的表面1511上。可利用例如以下合适的技术来形成导电层1603a，例如溅镀、物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)等沉积工艺、喷射涂布、无电镀敷(electroless plating)等。在一些实施例中，导电层1603a例如是铜、银、钯/铜合金等材料。在一些实施例中，利用表面准备工艺1513可使得导电层1603a无需通过暴露出的表面1511与导电层1603之间的粘合层(例如，不锈钢层或其他类型的粘合层)而贴合至暴露出的表面1511。在一些实施例中，导电层1603a被形成为具有介于约1μm与约10μm之间的厚度，例如约1μm。
保护层1603b共形地形成于导电层1603a上。保护层1603b可为例如不锈钢(SUS)等保护材料，但也可利用例如镍等任意其他合适的材料。可通过例如溅镀、物理气相沉积、化学气相沉积、原子层沉积、镀敷(plating)等工艺来将保护层1603b沉积成介于约0.1μm与约100μm之间的厚度，例如约10μm。
由于重布线层1507具有暴露出的侧壁1509，因此电磁干扰膜1601可经由暴露出的侧壁1509与集成扇出型叠层式封装结构1500实体接触及电接触。如此一来，电磁干扰膜1601可电连接至集成扇出型叠层式封装结构1500内的电压(例如，参考电压或接地电压)。在其他实施例中，电磁干扰膜1601可经由重布线层1507的多个暴露出的侧壁而连接至集成扇出型叠层式封装结构1500。通过将电磁干扰膜1601电连接至集成扇出型叠层式封装结构1500，来自电磁干扰膜1601的电磁屏蔽可得到改善。此外，通过形成直接位于暴露出的侧壁1509上的导电层1603a，集成扇出型叠层式封装结构1500与电磁干扰膜1601之间的电连接可具有降低的接触电阻(contact resistance)。举例来说，相比于暴露出的侧壁1509与电磁干扰膜的导电层下的粘合不锈钢层之间的连接，图16中所示的暴露出的侧壁1509与导电层1603a之间的连接可具有降低的接触电阻。
然而，如所属领域的普通技术人员将认识到，上述用于在集成扇出型叠层式封装结构1500上形成电磁干扰膜1601的工艺仅为一种说明，且并非意在将所述实施例限制至这一确切工艺。相反来说，所阐述的工艺旨在仅为说明性的，且可利用任意合适形成及封装例如集成扇出型叠层式封装结构1500等半导体装置的工艺作为另外一种选择。所有合适的工艺、封装、及结构皆包含于本实施例的范围内。
本发明的实施例包括被电磁干扰(EMI)膜覆盖的半导体装置，以屏蔽装置免受到电磁干扰。所述半导体装置可具有直接连接至电磁干扰膜的内导电层。如此一来，电磁干扰膜可电耦接至半导体装置，从而改善电磁干扰膜的屏蔽效果。此外，所述半导体装置可并入至例如集成扇出型结构、集成扇出型叠层式封装结构或其他结构等封装结构中。在一些实施例中，在半导体装置上覆盖电磁干扰膜能够消除对整个封装结构覆盖电磁干扰膜的需要，故可减少所需要的电磁干扰材料的量，进而降低成本并简化工艺。另外，半导体装置可被封装结构内的模制化合物或包封体覆盖。在这种情形中，覆盖半导体装置的电磁干扰膜可不需要保护层。如此一来，形成不具有保护层的电磁干扰膜也可降低所需要的电磁干扰材料的量，进而降低成本并简化工艺。
在一些实施例中，电磁干扰膜可形成于封装结构上。通过在形成电磁干扰膜之前执行表面准备工艺，可不需要电磁干扰膜的粘合层。形成不具有粘合层的电磁干扰膜也可减少所需要的电磁干扰材料的量，进而降低成本并简化工艺。此外，当不具电磁干扰膜的粘合层时，封装结构可电连接至电磁干扰膜的导电层，而可降低封装结构与电磁干扰膜之间的接触电阻。
根据本发明的一些实施例，一种半导体封装结构的制造方法至少包括以下步骤。形成第一半导体装置，其中所述第一半导体装置包括顶表面及底表面。所述第一半导体装置包括金属层，且所述金属层具有暴露出的第一表面。在所述第一半导体装置的所述顶表面及侧壁上形成电磁干扰(Electromagnetic Interference，EMI)膜，且所述电磁干扰膜与所述金属层的所述暴露出的第一表面电接触。在所述电磁干扰膜上形成模制化合物。
根据本发明的一些实施例，形成所述电磁干扰膜至少包括以下步骤。在所述第一半导体装置上形成粘合层。在所述粘合层上形成导电层。
根据本发明的一些实施例，所述粘合层包括不锈钢(Stainless Steel，SUS)。
根据本发明的一些实施例，所述导电层包括铜。
根据本发明的一些实施例，所述半导体封装结构的制造方法进一步包括将所述第一半导体装置平坦化。将所述第一半导体装置平坦化包括移除所述电磁干扰膜的顶部部分并暴露出所述金属层的第二表面。
根据本发明的一些实施例，所述半导体封装结构的制造方法进一步包括形成封装结构。形成所述封装结构至少包括以下步骤。在所述模制化合物、所述电磁干扰膜的所述顶部部分及所述金属层的所述第二表面上形成与所述模制化合物、所述电磁干扰膜的所述顶部部分及所述金属层的所述第二表面实体接触的重布线层(RDL)。所述重布线层在所述金属层的所述第二表面处电连接至金属层。在所述重布线层上形成外部连接件，所述外部连接件与所述重布线层电连接。
根据本发明的一些实施例，所述半导体封装结构的制造方法进一步包括以下步骤。形成在横向上与所述第一半导体装置隔开且在横向上被所述模制化合物环绕的通孔(via)。在所述第一半导体装置的与所述重布线层相对的表面上安置第二半导体装置，且所述通孔将所述第二半导体装置电连接至所述重布线层。
根据本发明的一些实施例，所述半导体封装结构的制造方法进一步包括在第三半导体装置的顶表面及侧壁上形成所述电磁干扰膜。
根据本发明的一些替代性实施例，一种半导体封装结构的制造方法至少包括以下步骤。形成封装。形成所述封装至少包括以下步骤。形成在横向上环绕第一半导体装置的包封体(encapsulant)及形成位于所述第一半导体装置上且电连接至所述第一半导体装置的重布线层(RDL)。所述半导体封装结构的制造方法也包括对所述包封体的暴露出的表面及所述重布线层的暴露出的表面的一部分执行表面准备工艺(surface preparationprocess)。所述半导体封装结构的制造方法还包括在所述封装的外表面上形成电磁干扰(Electromagnetic Interference，EMI)膜，且所述表面准备工艺增强所述电磁干扰膜对所述封装的粘合。
根据本发明的一些替代性实施例，执行所述表面准备工艺包括执行富氧处理工艺(oxygen enrichment treatment process)。
根据本发明的一些替代性实施例，执行所述表面准备工艺包括执行表面粗糙度处理工艺(surface roughness treatment process)。
根据本发明的一些替代性实施例，执行所述表面准备工艺包括执行干式等离子体工艺(dry plasma process)。
根据本发明的一些替代性实施例，形成所述电磁干扰膜至少包括以下步骤。在所述封装的外表面上形成导电层。在所述导电层上形成保护层。
根据本发明的一些替代性实施例，所述导电层包括铜。
根据本发明的一些替代性实施例，所述保护层(Stainless Steel，SUS)包括不锈钢。
根据本发明的一些替代性实施例，所述重布线层包含金属层，且所述金属层具有暴露出的侧壁。
根据本发明的一些替代性实施例，所述电磁干扰膜在所述金属层的所述暴露出的侧壁处实体接触所述重布线层的所述金属层。
根据本发明的再一些替代性实施例，一种半导体封装结构包括半导体装置、导电膜、包封体(encapsulant)以及重布线层(RDL)。所述半导体装置包括安置于半导体衬底上的金属层，且所述金属层的侧壁与所述半导体衬底的侧壁实质上共面(coplanar)。导电膜安置于所述半导体装置上。所述导电膜与所述金属层的所述侧壁实体接触且与所述半导体衬底的所述侧壁实体接触，且所述导电膜包括内粘合层及外导电层。包封体安置于所述导电膜上且与所述导电膜实体接触。重布线层安置于所述半导体装置及所述包封体上且与所述半导体装置及所述包封体实体接触。所述重布线层与所述金属层电连接。
根据本发明的再一些替代性实施例，所述内粘合层包括不锈钢且所述外导电层包括铜。
根据本发明的再一些替代性实施例，半导体封装结构进一步包括位于顶部衬底与所述重布线层之间并连接所述顶部衬底与所述重布线层的第一组穿孔，所述第一组穿孔与所述包封体实体接触并通过所述包封体而与所述半导体装置隔开。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，他们可容易地利用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种变化、代替、及变更。

Claims (1)

1.一种半导体封装结构的制造方法，其特征在于，包括：
形成第一半导体装置，其中所述第一半导体装置包括顶表面及底表面，其中所述第一半导体装置包括金属层，且所述金属层具有暴露出的第一表面；
在所述第一半导体装置的所述顶表面及侧壁上形成电磁干扰膜，其中所述电磁干扰膜与所述金属层的所述暴露出的第一表面电接触；以及
在所述电磁干扰膜上形成模制化合物。
CN201710140203.4A 2016-11-29 2017-03-10 半导体封装结构的制造方法 Pending CN108122788A (zh)

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