CN110660682A - 叠层封装结构的制造方法 - Google Patents

叠层封装结构的制造方法 Download PDF

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Publication number
CN110660682A
CN110660682A CN201811286453.XA CN201811286453A CN110660682A CN 110660682 A CN110660682 A CN 110660682A CN 201811286453 A CN201811286453 A CN 201811286453A CN 110660682 A CN110660682 A CN 110660682A
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package
conductive bumps
semiconductor device
tape carrier
base portion
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CN201811286453.XA
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CN110660682B (zh
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郭炫廷
谢静华
陈正庭
林修任
裴浩然
蔡钰芃
张家纶
曹智强
钟宇轩
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种叠层封装结构的制造方法包括以下步骤。在条带载体上提供第一封装，其中所述第一封装包括经包封半导体装置、设置在所述经包封半导体装置上的第一重布线结构及设置在所述第一重布线结构上且贴合到所述条带载体的多个导电凸块。通过多个电端子利用热压合工艺在所述第一封装上安装第二封装，所述热压合工艺使所述导电凸块变形成多个经变形导电凸块。所述经变形导电凸块中的每一者包括对所述第一重布线结构进行连接的基底部分及对所述基底部分进行连接的顶端部分，且所述基底部分的曲率大体上小于所述顶端部分的曲率。

Description

叠层封装结构的制造方法
技术领域
本发明实施例涉及一种叠层封装结构的制造方法。
背景技术
自集成电路(integrated circuit，IC)的发明以来，半导体行业已因各种电子组件(即，晶体管、二极管、电阻器、电容器等)的集成密度不断提高而经历了快速发展。在很大程度上，集成密度的此种提高来自于最小特征尺寸(minimum feature size)的重复减小，此使得更多组件能够集成到给定区域中。
这些集成上的改善基本上是二维(two-dimensional，2D)性质的，因为集成组件占据的体积基本上位于半导体晶片的表面上。尽管微影的明显改善已使得二维集成电路的形成得到相当大的改善，然而可在二维中实现的密度存在实体(physical)限制。这些限制中的一者是制作这些组件所需要的最小尺寸。此外，当将更多装置设置于一个芯片中时，需要更复杂的设计。
在尝试进一步提高电路密度时，已探究了三维(three-dimensional，3D)集成电路。在三维集成电路的典型形成工艺中，将两个管芯结合在一起，且在每一管芯与衬底上的接触垫之间形成电连接。举例来说，一种尝试涉及了将两个管芯堆叠结合。然后将经堆叠的管芯结合到载体衬底，且焊线将每一管芯上的电耦合接触垫结合到载体衬底上的接触垫。
发明内容
本发明实施例是针对一种叠层封装结构的制造方法，其可简化制造工艺，可降低生产成本，且可提高叠层封装结构的生产率。
根据本发明的实施例，一种叠层封装结构的制造方法包括以下步骤。在条带载体上提供第一封装，其中所述第一封装包括经包封半导体装置、设置在所述经包封半导体装置上的第一重布线结构及设置在所述第一重布线结构上且贴合到所述条带载体的多个导电凸块。通过多个电端子利用热压合工艺将第二封装设置在所述第一封装上，所述热压合工艺使所述导电凸块变形成多个经变形导电凸块。所述经变形导电凸块中的每一者包括连接所述第一重布线结构的基底部分及连接所述基底部分的顶端部分，且所述基底部分的曲率大体上小于所述顶端部分的曲率。
根据本发明的实施例，一种叠层封装结构的制造方法包括以下步骤。在条带载体上提供第一封装，其中所述第一封装包括经重构晶片及设置在所述经重构晶片的第一侧上且贴合到所述条带载体的多个导电凸块，且所述经重构晶片包括由包封材料包封的多个半导体装置。通过多个电端子利用热压合工艺将第二封装设置在所述经重构晶片的第二侧上，所述热压合工艺使所述导电凸块变形成多个经变形导电凸块。所述经变形导电凸块中的每一者包括连接所述经重构晶片的基底部分及连接所述基底部分的顶端部分，且所述基底部分的曲率大体上小于所述顶端部分的曲率。
根据本发明的实施例，一种叠层封装结构的制造方法包括以下步骤。在载体衬底上形成第一封装，其中所述第一封装包括经重构晶片及设置在所述经重构晶片的第一侧上的多个导电凸块，且所述经重构晶片包括由包封材料所包封的多个半导体装置。将具有所述载体衬底的所述第一封装设置在条带载体上。将所述载体衬底从条带载体上的第一封装剥离。通过热压合工艺将第二封装设置在所述经重构晶片的第二侧上以形成晶片上封装结构，所述热压合工艺通过将所述导电凸块压抵所述条带载体而使所述导电凸块变形成多个经变形导电凸块。所述经变形导电凸块中的每一者包括基底部分及顶端部分，且所述基底部分的曲率不同于所述顶端部分的曲率。对所述条带载体上的所述晶片上封装结构执行单体化工艺以形成多个叠层封装结构。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1到图13示出根据本公开一些示例性实施例在叠层封装结构的制造中的中间阶段的剖视图。
图14示出根据本公开一些示例性实施例的叠层封装结构的导电凸块的剖视图。
图15示出根据本公开一些示例性实施例的叠层封装结构的经变形导电凸块的剖视图。
图16示出根据本公开一些示例性实施例的叠层封装结构的经变形导电凸块的示意性俯视图。
[符号的说明]
10：叠层封装结构
10’：晶片上封装结构
100、100’：第一封装
101：经包封半导体装置
105：经重构晶片
110：半导体装置/装置管芯
110’：半导体装置
110a、110a’：第一半导体装置
110b、110b’：第二半导体装置
112：衬底
113：接触垫
114：导通孔
116、116’、143：介电层
120、120’：包封材料
130：导电柱
140：重布线结构/第一重布线结构
142：重布线路
143：介电层
144：凸块下金属层
160：图案化介电层
162：开口
165：焊料
170：重布线结构/第二重布线结构
180：导电凸块
180’：经变形导电凸块
182：顶端部分
184：基底部分
200：第二封装
210：电端子
300：载体衬底
310：粘合层
400：条带载体
410：框架结构
500：刀具
D1、D2：最大直径
H1、h1、h2：高度
T1：厚度
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及配置的具体实例以简化本公开。当然，这些仅为实例而非旨在进行限制。举例来说，在以下说明中，在第二特征之上或第二特征上形成第一特征可包括其中第一特征与第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成附加特征从而使得第一特征与第二特征可不直接接触的实施例。另外，本公开在各种实例中可重复使用参考编号和/或字母。此种重复使用是为了简明及清晰起见，且自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”等空间相对性用语来阐述图中所示一个元件或特征与另一(其他)元件或特征的关系。除附图中所绘示的取向以外，所述空间相对性用语旨在涵盖装置在使用或操作中的不同取向。设备可被另外取向(旋转90度或处于其他取向)，且本文所使用的空间相对性描述语可同样相应地作出解释。
另外，为易于说明，本文中可使用例如“第一”、“第二”、“第三”、“第四”等用语来阐述图中所示的相似或不同的元件或特征，且可依据存在的次序或说明的上下文而互换地使用。
还可包括其他特征及工艺。举例来说，可包括测试结构以帮助进行三维封装或三维集成电路装置的验证测试。测试结构可包括例如形成于重布线层中或衬底上的测试垫，所述测试垫使得能够测试三维封装或3DIC、使用探针(probe)和/或探针卡(probe card)等。可对中间结构及最终结构执行验证测试。另外，本文中所公开的结构及方法可结合包括对已知良好管芯的中间验证的测试方法一起使用，以提高良率(yield)并降低成本。
图1到图13示出根据本公开一些示例性实施例在叠层封装结构的制造中的中间阶段的剖视图。应注意，将关于特定上下文中的一些实施例、即叠层封装结构来阐述本公开。然而，本公开中的概念也可适用于其他半导体结构或电路。根据各种实施例提供适用于叠层封装结构的半导体封装、叠层封装结构及形成叠层封装结构的方法。根据一些实施例对形成叠层封装结构的中间阶段进行说明。对各实施例的变型进行论述。在所有各图及说明性实施例中，相同的参考编号用于标示相同的元件。
在一些实施例中，形成图13所示叠层封装结构的中间阶段阐述如下。参照图1，提供载体衬底300，且可在载体衬底300上设置粘合层310。在一些实施例中，载体衬底300可包括例如硅系材料(例如玻璃、陶瓷或氧化硅)或其他材料(例如氧化铝)、这些材料的任一组合等。载体衬底300为平坦的，以便于例如半导体装置110/110’(未示于图1中，但以下关于图2及图4进行示出及论述)等半导体装置的贴合。粘合剂层310可放置在载体衬底300上，以有助于上覆(overlying)结构(例如，重布线结构170)的粘附。在实施例中，粘合剂层310可包括紫外胶(ultra-violet glue)，所述紫外胶在暴露于紫外光时会减低或丧失其粘合性质。然而，也可使用例如压敏粘合剂(pressure sensitive adhesive)、可辐射固化粘合剂(radiation curable adhesive)、光热转换释放涂层(light to heat conversionrelease coating，LTHC)、环氧化物、其组合等其他类型的粘合剂。可将粘合剂层310以在压力下易于变形的半液体形式或凝胶形式放置到载体衬底300上。
在一些实施例中，可在载体衬底300上或在粘合层310(如果存在)上形成第一封装(例如，图6所示的第一封装100)。在一些实施例中，第一封装100是集成扇出型(IntegratedFan-Out，InFO)封装，但作为另一选择也可使用任何合适的封装。在本实施例中，第一封装100包括经重构晶片(reconstructed wafer)(例如，图6所示的经重构晶片105)及设置在经重构晶片的第一侧上的多个导电凸块(例如，图6所示导电凸块180)。经重构晶片包括由包封材料120所包封的多个半导体装置110。形成第一封装100可包括以下步骤。
现在参照图1，可选择性地在载体衬底300上或在粘合层310(如果存在)上形成(第二)重布线结构170。在一些实施例中，重布线结构170可包括至少一个绝缘层。绝缘层可放置在粘合剂层310之上，且绝缘层可用于对例如半导体装置110/110’提供保护(在半导体装置110/110’贴合后)。在实施例中，绝缘层可为聚苯并恶唑(polybenzoxazole，PBO)，但作为另一选择也可利用例如聚酰亚胺(polyimide)或聚酰亚胺衍生物等任何合适的材料。可利用例如旋转涂布工艺来将绝缘层设置为介于约2μm与约15μm之间(例如约5μm)的厚度，但作为另一选择也可利用任何合适的方法及厚度。在一些实施例中，重布线结构170还可包括电路层，所述电路层用于在半导体装置110/110’贴合后电连接半导体装置110/110’。
然后，在载体衬底300上提供多个导电柱(through vias)130，且导电柱130环绕欲设置半导体装置110/110’的至少一个装置区域。在本实施例中，导电柱130形成在位于载体衬底300上的重布线结构170上且电连接到重布线结构170，但本公开并非仅限于此。在其他实施例中，导电柱130可为预制的，然后再将导电柱130放置在载体衬底300上。
在导电柱130形成在载体衬底300上的实施例中，形成导电柱130可包括以下步骤。首先，可在重布线结构170之上形成晶种层。晶种层为导电材料的薄层，此有助于在后续处理步骤期间形成更厚的层。举例来说，晶种层可包括约
Figure BDA0001849155080000051
厚的钛层、然后是约
Figure BDA0001849155080000052
厚的铜层。可依据期望的材料使用例如溅射工艺、蒸镀工艺或等离子体增强型化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)工艺等工艺来形成晶种层。
然后，在晶种层之上形成光刻胶。在实施例中，光刻胶可利用例如旋转涂布技术放置在晶种层上。一旦设置光刻胶，便可通过以下方式对光刻胶进行图案化：将光刻胶曝光于图案化能量源(例如，图案化光源)，由此引发光刻胶的被曝光于图案化光源的那些部分的物理变化。然后对被曝光的光刻胶施加显影剂，以利用所述物理变化并依据期望的图案选择性地移除光刻胶的被曝光部分或光刻胶的未曝光部分。形成于光刻胶上的图案是用于形成导电柱130的图案。导电柱130形成于此种位置以便位于随后贴合的半导体装置110/110’的不同侧上。换句话说，半导体装置110/110’被导电柱130环绕。然而，作为另一选择也可利用导电柱130的图案的任何合适的配置。
然后，在光刻胶中形成导电柱130。在实施例中，导电柱130包括一种或多种导电材料(例如铜、钨、其他导电材料等)，且可例如通过电镀、无电镀覆等形成。在实施例中，使用电镀工艺在光刻胶的开口内镀覆晶种层的被暴露导电区域。在用光刻胶及晶种层形成导电柱130之后，便可使用合适的移除工艺来移除光刻胶。在实施例中，可使用等离子体灰化工艺来移除光刻胶，因此可升高光刻胶的温度直到光刻胶经历热分解且可被移除。然而，作为另一选择也可利用任何其他合适的工艺，例如湿式剥除。移除光刻胶可暴露出晶种层的下面的部分。
然后，可通过例如湿式刻蚀工艺或干式刻蚀工艺来移除晶种层的被暴露部分(例如，未被导电柱130覆盖的那些部分)。举例来说，在干式刻蚀工艺中，可使用导电柱130作为掩膜将反应剂朝晶种层引导。作为另一选择，可喷涂刻蚀剂或以其他方式使刻蚀剂接触晶种层，以移除晶种层的被暴露部分。在已刻蚀掉晶种层的被暴露部分之后，在导电柱130之间暴露出重布线结构170的一部分。此时，大体上完成了导电柱130的形成。
现在参照图2，在一些实施例中，可在载体衬底300上及在导电柱130内或导电柱130之间提供至少一个半导体装置110’(图中示出多个半导体装置110’，但并非仅限于此)。在实施例中，半导体装置110’可包括至少一个半导体装置组(图中示出多个半导体装置组，但并非仅限于此)，且半导体装置组中的每一者可包括第一半导体装置110a’及第二半导体装置110b’。在每一组中，第一半导体装置110a’与第二半导体装置110b’通过例如(第一)重布线结构140(未示于图2中但以下关于图5进行示出及论述)进行电连接，且可一起用于为最终用户提供期望的功能。在实施例中，第一半导体装置110a’及第二半导体装置110b’可使用例如粘合材料贴合到载体衬底300(或重布线结构170)，但作为另一选择也可利用任何合适的贴合方法。导电柱130可环绕半导体装置110’的每一组。通过此种配置，对于批量生产来说可同时形成多个叠层封装结构。为简洁及清晰起见，以下制造工艺是针对一个叠层封装结构进行阐述。
在一些实施例中，半导体装置110’可为其中包括逻辑电路的逻辑装置管芯。在一些示例性实施例中，半导体装置110’是为移动应用而设计的管芯，且可例如包括电源管理集成电路(Power Management Integrated Circuit，PMIC)管芯及收发器(TRX)管芯。应注意，更多或更少的半导体装置110’可放置在载体衬底300之上且彼此齐平。
在一些示例性实施例中，半导体装置110’中的每一者可包括衬底112、多个有源装置(图中未示出)、多个接触垫113、至少一个介电层116’及多个导通孔114。导通孔114(例如铜通孔)可形成在半导体装置110’的有源表面(例如，顶表面)上且电耦合到衬底112上的接触垫113。衬底112可包括经掺杂或未经掺杂的块体硅(bulk silicon)或者绝缘体上硅(silicon-on-insulator，SOI)衬底的有源层。一般来说，SOI衬底包括一层半导体材料，例如硅、锗、硅锗、SOI、绝缘体上硅锗(silicon germanium on insulator，SGOI)或其组合。可使用的其他衬底包括多层式衬底、梯度(gradient)衬底或混合方向(hybrid orientation)衬底。有源装置包括可用来产生半导体装置110’的设计的期望结构及功能要求的各种有源装置及无源装置(例如电容器、电阻器、电感器等)。有源装置可利用任何合适的方法形成在衬底112内或衬底112上。
在一些实施例中，介电层116’可形成在半导体装置110’的有源表面上，且可覆盖导通孔114的顶表面。在其他实施例中，介电层116’的顶表面可与导通孔114的顶表面大体上齐平。作为另一选择，可省略介电层116’，且导通孔114从半导体装置110’的有源表面突出。介电层116’可由例如氧化硅、氮化硅、低介电常数介电质(例如，掺杂碳的氧化物)、极低介电常数介电质(例如，掺杂多孔碳的二氧化硅)、其组合等一或多种合适的介电材料制成。可通过例如化学气相沉积(chemical vapor deposition，CVD)等工艺来形成介电层116’，但也可利用任何合适的工艺。
在一些实施例中，导电柱130的顶端可与导通孔114的顶表面大体上齐平。在其他实施例中，导电柱130的顶端可大体上高于导通孔114的顶表面。作为另一选择，导电柱130的顶端可大体上低于导通孔114的顶表面，但大体上高于导通孔114的底表面。
现在参照图3，在一些实施例中，由包封材料120’来包封载体衬底300上的半导体装置110’及导电柱130。换句话说，在载体衬底300上形成包封材料120’，以包封导电柱130及半导体装置110’。在一些实施例中，包封材料120’填充半导体装置110’与导电柱130之间的间隙，且可接触重布线结构170。包封材料120’可包括例如聚酰亚胺、聚苯硫醚(polyphenylene sulfide，PPS)、聚醚醚酮(polyetheretherketone，PEEK)、聚醚砜(polyethersulfone，PES)、耐热水晶树脂、其组合等模制化合物树脂。可在模制装置(图3中未单独示出)中执行半导体装置110’及导电柱130的包封。可将包封材料120’放置在模制装置的模制空腔内，或者可通过注射口将包封材料120’注射到模制空腔中。
一旦已将包封材料120’放置到模制空腔中以使得包封材料120’包封载体衬底300、半导体装置110’及导电柱130，便可将包封材料120’固化以硬化包封材料120’来实现最佳保护。另外，可在包封材料120’内包括引发剂和/或催化剂以更好地控制固化工艺。在一些实施例中，包封材料120’的顶表面可高于导电柱130的顶端及介电层116’的顶表面。即，包封材料120’覆盖导电柱130的顶端及介电层116’的顶表面。
现在参照图4，可对包封材料120’(及介电层116’)执行薄化工艺，以显露出导电柱130的顶端及导通孔114的顶表面以用于进一步处理。薄化工艺可为例如利用化学刻蚀剂及磨料使包封材料120’、半导体装置110’反应且研磨掉包封材料120’、半导体装置110’直到导电柱130、导通孔114已被显露出的机械研磨或化学机械抛光(Chemical MechanicalPolishing，CMP)工艺。所得结构示出于图4中。在执行薄化工艺之后，导电柱130的顶端与导通孔114的顶表面大体上齐平，且与包封材料120的顶表面及介电层116的顶表面大体上齐平，如图4所示。然而，尽管上述CMP工艺被呈现为一个说明性实施例，但其并不旨在限制所述实施例。作为另一选择也可使用任何其他合适的移除工艺来将包封材料120、半导体装置110薄化并暴露出导电柱130。举例来说，作为另一选择可利用一系列化学刻蚀剂。作为另一选择可利用此工艺及任何其他合适的工艺来将包封材料120、半导体装置110及导电柱130薄化，且所有这些工艺均旨在包括于实施例的范围内。
在说明书通篇中，将图4所示的包括半导体装置110(包括图4所示第一半导体装置110a及第二半导体装置110b)、导电柱130及包封材料120的所得结构称为经包封半导体装置101，经包封半导体装置101可在所述工艺中具有晶片形式。因此，在经包封半导体装置101中，半导体装置110设置在管芯区域处，导电柱130延伸穿过管芯区域外的经包封半导体装置101，且包封材料120包封半导体装置110及导电柱130。换句话说，包封材料120将半导体装置110包封在包封材料120中，且导电柱130延伸穿过包封材料120。
现在参照图5，在经包封半导体装置101的第一侧上形成第一重布线结构140。第一重布线结构140电连接到半导体装置110及导电柱130。在一些实施例中，在经包封半导体装置101(包括包封材料120及半导体装置110)之上形成第一重布线结构140，以连接到半导体装置110的导通孔114及导电柱130。在一些实施例中，第一重布线结构140也可将导通孔114与导电柱130内连。可通过以下步骤来形成第一重布线结构140：例如沉积导电层，对导电层进行图案化以形成重布线路142，局部地覆盖重布线路142，且利用介电层143填充重布线路142之间的间隙等。重布线路142的材料可包括金属或金属合金，所述金属或金属合金包括铝、铜、钨和/或其合金。介电层143可由例如氧化物、氮化物、碳化物、碳氮化物、其组合和/或其多个层等介电材料形成。重布线路142形成在介电层143中，且电连接到装置管芯110及导电柱130。在经包封半导体装置101设置在重布线结构170上的实施例中，第二重布线结构170位于经包封半导体装置101的与设置有第一重布线结构140的第一侧相对的第二侧上。即，第一重布线结构140与第二重布线结构170分别设置在经包封半导体装置101的相对两侧上。
在说明书通篇中，将图5所示的包括第一重布线结构140、经包封半导体装置101(及第二重布线结构170)的所得结构称为经重构晶片105，经重构晶片105在所述工艺中具有晶片形式。
现在参照图6，在第一重布线结构140上设置多个导电凸块180。换句话说，在经重构晶片105的侧面上设置导电凸块180。在一些实施例中，可通过溅射、蒸镀或无电镀覆等在第一重布线结构140上形成凸块下金属(Under Bump Metallurgy，UBM)层144，且可在UBM层144上设置导电凸块180。在一些实施例中，根据一些示例性实施例，也可在第一重布线结构140上设置至少一个集成无源装置(Integrated Passive Device，IPD)。形成导电凸块180可包括：将焊料球放置在UBM层144上(或第一重布线结构140上)，然后对焊料球进行回焊。在替代实施例中，形成导电凸块180可包括：执行镀覆工艺以在UBM层144上(或第一重布线结构140上)形成焊料区，然后对焊料区进行回焊。IPD可利用例如薄膜及光刻处理等标准晶片制作技术来制作，且可通过例如倒装芯片结合或焊线结合等安装在UBM层144上(或第一重布线结构140上)。
在说明书通篇中，将图6所示的包括第一重布线结构140、经包封半导体装置101、第二重布线结构170及导电凸块180的所得结构称为第一封装100，第一封装100可在所述工艺中具有晶片形式。
图14示出根据本公开一些示例性实施例的叠层封装结构的导电凸块的剖视图。现在参照图7及图14，在载体衬底300上形成第一封装100之后，可将具有载体衬底300的第一封装100翻转且通过将导电凸块180贴合到条带载体(tape carrier)400而将具有载体衬底300的第一封装100设置在条带载体400上。用以承载具有载体衬底300的第一封装100的条带载体400还可包括框架结构410，框架结构410可用于在后续的工艺期间为此结构提供支撑及稳定性的金属环。在一些实施例中，条带载体400是由例如具有柔性的聚合物材料制成。在一个实施例中，条带载体400的杨氏模量(young’s modulus)大体上小于10Mpa，且条带载体400的玻璃转变温度(Tg)大体上低于室温。即，当在室温下或高于室温使用条带载体400时，条带载体400处于橡胶状态，其中条带载体400为柔软且具有柔性的。因此，当导电凸块180贴合到条带载体400时，条带载体400会变形且包围导电凸块180中的每一者的至少下部部分，如图14所示。
现在参照图7及图8，将载体衬底300从条带载体400上的第一封装100剥离。可使用例如热工艺来改变粘合层310的粘性从而将载体衬底300剥离。在实施例中，利用例如紫外(UV)激光、二氧化碳(CO2)激光或红外(infrared，IR)激光等能量源来辐照及加热粘合层310，直到粘合层310丧失至少部份粘性。一旦执行，便可将载体衬底300及粘合层310从第一封装100实体地分离及移除，如图8所示。
在将载体衬底300剥离之后，可显露出第二重布线结构170。在第二重布线结构170被省略的实施例中，可执行研磨工艺以轻微地研磨包封材料120、半导体装置110的背面及导电柱130的底端。在其他实施例中，可省略研磨工艺。
现在参照图9，在一些实施例中，可在经重构晶片105上形成图案化介电层160，以提供对第二重布线结构170及其他下伏(underlying)结构的保护及隔离。在实施例中，图案化介电层160可为聚苯并恶唑(PBO)，但作为另一选择也可利用例如聚酰亚胺或聚酰亚胺衍生物等任何合适的材料。可通过以下方式来形成图案化介电层160：使用例如旋转涂布工艺放置介电层，然后对介电层进行图案化以形成显露出经重构晶片105的多个电接触件(例如，第二重布线结构170的电接触件)的多个开口162。可利用合适的光刻掩膜及刻蚀工艺来形成开口162，但也可使用任何合适的工艺。
现在参照图9及图10，在一些实施例中，在开口162中形成多种焊料165。在一些实施例中，使用网版印刷工艺来形成焊料165。举例来说，在印刷表面(例如，第二重布线结构170)之上放置网版框架(screen frame)，且将焊料165沉积到网版框架上。然后，可在整个网版框架上驱动柔性刮板等以推压焊料165通过网版框架的开口。然而，也可使用任何合适的工艺在开口162中设置焊料165。
现在参照图11，通过多个电端子210将至少一个第二封装200(在此中示出多个第二封装200)设置在第一封装100上。在实施例中，第二封装200用于分别与半导体装置110(包括图4所示第一半导体装置110a及第二半导体装置110b)一起运作以为最终用户提供期望的功能。在第一封装100中具有一组半导体装置110(例如，包括一个第一半导体装置110a及一个第二半导体装置110b)的实施例中，一个第二封装200可设置在第一封装100上。
在实施例中，第二封装200可包括例如存储器装置等半导体装置，所述半导体装置可用于为半导体装置110提供所存储的数据。在此种实施例中，半导体装置110可包括存储器控制模块(图中未示出)，所述存储器控制模块除由半导体装置110提供的其他功能以外还对第二封装200的存储器装置提供控制功能。然而，在其他实施例中，第二封装200可包括自身的存储器控制模块。
在一些实施例中，通过以下方式将第二封装200设置在第一封装100上：首先，使电端子210与图案化介电层160的开口对准，且将电端子210放置成实体地接触焊料165。因此，第二封装200电连接到焊料165。一旦接触，便可使用例如热压合工艺等工艺将电端子210结合到第一封装100。作为另一选择可利用任何合适的结合方法将第二封装200结合到第一封装100。在热压合工艺(包括回焊工艺)的高温下将导电凸块180压抵在具有柔性的条带载体400上，导电凸块180会变形成多个经变形导电凸块180’，如图11所示。
在说明书通篇中，将图11所示的包括晶片形式的第一封装100及安装在第一封装100上的第二封装200的所得结构称为晶片上封装(package on wafer)结构10’，晶片上封装结构10’在所述工艺中具有晶片形式。
图15示出根据本公开一些示例性实施例的叠层封装结构的经变形导电凸块的剖视图。图16示出根据本公开一些示例性实施例的叠层封装结构的经变形导电凸块的示意性俯视图。现在参照图15及图16，在一些实施例中，经变形导电凸块180’中的每一者包括顶端部分182及基底部分184。基底部分184连接到第一重布线结构140，且顶端部分182连接到基底部分184。顶端部分182与基底部分184直接彼此连接并一体成型。
由于在高温下条带载体400的包围，导电凸块接触条带载体400的顶端受到挤压并变形成顶端部分182。因此，基底部分184的曲率不同于顶端部分182的曲率。换句话说，经变形导电凸块180’中的每一者经历顶端部分182与基底部分184之间的曲率变化。此曲率变化可为渐进变化，但在其他实施例中，曲率变化也可为更急剧的变化。从图16所示经变形导电凸块180’的俯视图，可以看出经变形导电凸块180’不具有均匀的圆顶形状。为了实现变形，条带载体400的厚度T1大体上大于每一经变形导电凸块180’的高度H1的20％，且条带载体400的厚度T1大体上小于每一经变形导电凸块180’的高度H1的80％，即20％H1<T1<80％H1。在一些实施例中，条带载体400的厚度T1对顶端部分182的高度h1的比率可大体上介于50％到150％之间。在一些实施例中，顶端部分182的高度h1大体上小于基底部分184的高度h2。
在一些实施例中，基底部分184的曲率大体上小于顶端部分182的曲率。在几何学上，曲率是测量曲线的单位切向量(unit tangent vector)旋转的速度。也就是说，在一些实施例中，基底部分184的曲线的单位切向量的变化略小于顶端部分182的曲线的单位切向量的变化。换句话说，顶端部分182的曲率可经历更急剧的转弯。在一些实施例中，顶端部分182的最大直径D1大体上小于基底部分184的最大直径D2。举例来说，顶端部分182的最大直径D1对基底部分184的最大直径D2的比率(即，D1/D2)大体上介于50％到90％范围内。
由于经变形导电凸块180’的变形，条带载体400与经变形导电凸块180’之间的接触面积增加，因而可提高条带载体400与经变形导电凸块180’之间的结合强度。因此，可以更牢固及更稳定的方式将第一封装100固定到条带载体400上，以提高在晶片上封装结构10’上执行的结合工艺的良率。另外，条带载体400通过在结合工艺及例如单体化工艺等后续工艺期间包围经变形导电凸块180’的至少一部分来提供对经变形导电凸块180’的可靠保护。
现在参照图12，对条带载体400上的晶片上封装结构10’执行单体化工艺，以形成彼此独立的多个叠层封装结构10。因此，经单体化第一封装中的每一者可包括第一半导体装置110a中的一者及第二半导体装置110b中的一者。在实施例中，可使用刀具500执行单体化工艺以切穿第一封装100的经重构晶片105。因此，第一封装100的一个区段(例如，包括第一半导体装置110a中的一者及第二半导体装置110b中的一者)从另一区段分离以形成多个叠层封装结构10。叠层封装结构10中的每一者包括第一封装100’以及结合到第一封装100’的第二封装200。
然而，如所属领域中的一般技术人员将知，利用刀具将晶片上封装结构10’单体化仅为一个说明性实施例，而并不旨在进行限制。作为另一选择也可利用对晶片上封装结构10’进行单体化的替代方法，例如利用一种或多种刻蚀剂对晶片上封装结构10’进行分离并形成叠层封装结构10。作为另一选择也可利用这些方法及任何其他合适的方法来进行单体化工艺。
现在参照图13，通过包括多个戳针(poker pin)600的设备将所述多个叠层封装结构10从条带载体400分离，所述多个戳针600在条带载体400下方进行戳刺。在一些实施例中，戳针600中的每一者位于与剩余戳针600共同的平面上。将所述多个叠层封装结构10与条带载体400一起放置在设备上，因此戳针600被配置成在条带载体400的背面上进行戳刺。在实施方案中的一者中，可在戳针600之间形成真空条件，且真空条件将条带载体400的至少部分朝戳针600牵拉且因此减小叠层封装结构10与条带载体400之间的接触面积。在一些实施例中，可通过对至少条带载体400施加热来促进移除工艺的进行，以使得叠层封装结构10与条带载体400之间的粘附力进一步减小。
通过此种配置，在叠层封装结构10的制造工艺中，对载体衬底300进行剥离的剥离工艺、将第二封装200安装到第一封装100上的结合及回焊工艺以及单体化工艺全部在条带载体400上执行。因此，可简化制造工艺，可降低生产成本，且可提高叠层封装结构10的生产率。另外，通过在条带载体400上执行结合及回焊工艺从而引起经变形导电凸块180’变形，条带载体400与经变形导电凸块180’之间的结合强度得到提高。因此，在晶片上封装结构10’上执行的结合工艺的良率也得到提高。此外，条带载体400通过包围经变形导电凸块180’的至少一部分来提供对经变形导电凸块180’的可靠保护。
基于以上论述，可看出本公开提供各种优点。然而，应理解，本文中未必论述所有优点，其他实施例可提供不同优点，且对于所有实施例来说并不需要特定优点。
根据本公开的一些实施例，一种叠层封装结构的制造方法包括以下步骤。在条带载体上提供第一封装，其中所述第一封装包括经包封半导体装置、设置在所述经包封半导体装置上的第一重布线结构及设置在所述第一重布线结构上且贴合到所述条带载体的多个导电凸块。通过多个电端子利用热压合工艺将第二封装设置在所述第一封装上，所述热压合工艺使所述导电凸块变形成多个经变形导电凸块。所述经变形导电凸块中的每一者包括连接所述第一重布线结构的基底部分及连接所述基底部分的顶端部分，且所述基底部分的曲率大体上小于所述顶端部分的曲率。
根据本公开的一些实施例，所述顶端部分的最大直径小于所述基底部分的最大直径。
根据本公开的一些实施例，所述顶端部分的最大直径对所述基底部分的最大直径的比率介于50％到90％之间。
根据本公开的一些实施例，所述条带载体的厚度大于所述经变形导电凸块中的每一者的高度的20％，且小于所述经变形导电凸块中的每一者的所述高度的80％。
根据本公开的一些实施例，提供所述经包封半导体装置的方法包括：提供多个导电柱；提供半导体装置，其中所述半导体装置被所述多个导电柱环绕；以及由包封材料包封所述半导体装置及所述多个导电柱。
根据本公开的一些实施例，所述经包封半导体装置设置在第二重布线结构上，且所述第二重布线结构位于所述经包封半导体装置的与所述第一侧相对的第二侧上。
根据本公开的一些实施例，所述的叠层封装结构的制造方法还包括：在所述经包封半导体装置上形成图案化介电层，其中所述图案化介电层包括显露出所述经包封半导体装置的多个电接触件的多个开口；以及在所述多个开口中形成多个焊料，且所述第二封装安装在所述图案化介电层上并电连接到所述多个焊料。
根据本公开的一些实施例，一种叠层封装结构的制造方法包括以下步骤。在条带载体上提供第一封装，其中所述第一封装包括经重构晶片及设置在所述经重构晶片的第一侧上且贴合到所述条带载体的多个导电凸块，且所述经重构晶片包括由包封材料包封的多个半导体装置。通过多个电端子利用热压合工艺将第二封装设置在所述经重构晶片的第二侧上，所述热压合工艺使所述导电凸块变形成多个经变形导电凸块。所述经变形导电凸块中的每一者包括连接所述经重构晶片的基底部分及连接所述基底部分的顶端部分，且所述基底部分的曲率大体上小于所述顶端部分的曲率。
根据本公开的一些实施例，所述顶端部分的最大直径小于所述基底部分的最大直径。
根据本公开的一些实施例，所述顶端部分的最大直径对所述基底部分的最大直径的比率介于50％到90％之间。
根据本公开的一些实施例，所述条带载体的杨氏模量小于10Mpa。
根据本公开的一些实施例，形成所述经重构晶片的方法包括：提供多个导电柱；提供所述多个半导体装置，其中所述多个半导体装置被所述多个导电柱环绕；由所述包封材料包封所述多个半导体装置及所述导电柱；以及在所述经重构晶片的所述第一侧上形成第一重布线结构，其中所述第一重布线结构在所述包封材料及所述多个半导体装置上延伸。
根据本公开的一些实施例，所述经包封半导体装置设置在第二重布线结构上，且所述第二重布线结构位于所述经包封半导体装置的与所述第一侧相对的第二侧上。
根据本公开的一些实施例，所述的叠层封装结构的制造方法，还包括：在所述经包封半导体装置上形成图案化介电层，其中所述图案化介电层包括显露出所述经包封半导体装置的多个电接触件的多个开口；以及在所述开口中形成多种焊料，且所述第二封装安装在所述图案化介电层上并电连接到所述焊料。
根据本公开的一些实施例，一种叠层封装结构的制造方法包括以下步骤。在载体衬底上形成第一封装，其中所述第一封装包括经重构晶片及设置在所述经重构晶片的第一侧上的多个导电凸块，且所述经重构晶片包括由包封材料所包封的多个半导体装置。将具有所述载体衬底的所述第一封装设置在条带载体上。将所述载体衬底从条带载体上的第一封装剥离。通过热压合工艺将第二封装设置在所述经重构晶片的第二侧上以形成晶片上封装结构，所述热压合工艺通过将所述导电凸块压抵所述条带载体而使所述导电凸块变形成多个经变形导电凸块。所述经变形导电凸块中的每一者包括基底部分及顶端部分，且所述基底部分的曲率不同于所述顶端部分的曲率。对所述条带载体上的所述晶片上封装结构执行单体化工艺以形成多个叠层封装结构。
根据本公开的一些实施例，形成所述经重构晶片的方法包括：在所述载体衬底上提供多个导电柱；在所述载体衬底上提供所述多个半导体装置，其中所述半导体装置被所述导电柱环绕；由所述包封材料包封所述多个半导体装置及所述导电柱；以及在所述经重构晶片的所述第一侧上形成第一重布线结构，其中所述第一重布线结构在所述包封材料及所述多个半导体装置之上延伸。
根据本公开的一些实施例，在所述载体衬底上形成所述第一封装还包括：在所述载体衬底上提供所述多个半导体装置及所述多个导电柱之前在所述载体衬底上形成第二重布线结构。
根据本公开的一些实施例，所述的叠层封装结构的制造方法还包括：在所述经重构晶片上形成图案化介电层，其中所述图案化介电层包括显露出所述经重构晶片的多个电接触件的多个开口；以及在所述多个开口中形成多个焊料，且所述第二封装安装在所述图案化介电层上并电连接到所述多个焊料。
根据本公开的一些实施例，所述单体化工艺还包括：对所述条带载体上的所述经重构晶片进行切割以形成所述多个叠层封装结构。
根据本公开的一些实施例，所述单体化工艺还包括：通过以多个在所述条带载体下方进行戳刺的戳针将所述多个叠层封装结构从所述条带载体分离。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解，其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (10)

1.一种叠层封装结构的制造方法，其特征在于，包括：
在条带载体上提供第一封装，其中所述第一封装包括经包封半导体装置、设置在所述经包封半导体装置的第一侧上的第一重布线结构及设置在所述第一重布线结构上且贴合到所述条带载体的多个导电凸块；以及
通过多个电端子利用热压合工艺将第二封装设置在所述第一封装上，所述热压合工艺使所述多个导电凸块变形成多个经变形导电凸块，
其中所述多个经变形导电凸块中的每一者包括连接所述第一重布线结构的基底部分及连接所述基底部分的顶端部分，且所述基底部分的曲率小于所述顶端部分的曲率。
2.根据权利要求1所述的叠层封装结构的制造方法，所述顶端部分的最大直径小于所述基底部分的最大直径或是所述顶端部分的最大直径对所述基底部分的最大直径的比率介于50％到90％之间。
3.根据权利要求1所述的叠层封装结构的制造方法，所述条带载体的厚度大于所述经变形导电凸块中的每一者的高度的20％，且小于所述经变形导电凸块中的每一者的所述高度的80％。
4.根据权利要求1所述的叠层封装结构的制造方法，所述经包封半导体装置设置在第二重布线结构上，且所述第二重布线结构位于所述经包封半导体装置的与所述第一侧相对的第二侧上。
5.一种叠层封装结构的制造方法，其特征在于，包括：
在条带载体上提供第一封装，其中所述第一封装包括经重构晶片及设置在所述经重构晶片的第一侧上且贴合到所述条带载体的多个导电凸块，且所述经重构晶片包括由包封材料所包封的多个半导体装置；以及
通过多个电端子利用热压合工艺将多个第二封装设置在所述经重构晶片的第二侧上，所述热压合工艺使所述导电凸块变形成多个经变形导电凸块，
其中所述经变形导电凸块中的每一者包括连接所述经重构晶片的基底部分及连接所述基底部分的顶端部分，且所述基底部分的曲率小于所述顶端部分的曲率。
6.根据权利要求5所述的叠层封装结构的制造方法，所述顶端部分的最大直径小于所述基底部分的最大直径或是所述顶端部分的最大直径对所述基底部分的最大直径的比率介于50％到90％之间。
7.根据权利要求5所述的叠层封装结构的制造方法，所述条带载体的杨氏模量小于10Mpa。
8.根据权利要求5所述的叠层封装结构的制造方法，其中所述经包封半导体装置设置在第二重布线结构上，且所述第二重布线结构位于所述经包封半导体装置的与所述第一侧相对的第二侧上。
9.一种叠层封装结构的制造方法，其特征在于，包括：
在载体衬底上形成第一封装，其中所述第一封装包括经重构晶片及设置在所述经重构晶片的第一侧上的多个导电凸块，且所述经重构晶片包括由包封材料包封的多个半导体装置；
将具有所述载体衬底的所述第一封装设置在条带载体上；
将所述载体衬底从所述条带载体上的所述第一封装剥离；
通过热压合工艺在所述经重构晶片的第二侧上安装多个第二封装以形成晶片上封装结构，所述热压合工艺通过将所述导电凸块压抵所述条带载体而使所述导电凸块变形成多个经变形导电凸块，
其中所述经变形导电凸块中的每一者包括基底部分及顶端部分，且所述基底部分的曲率不同于所述顶端部分的曲率；以及
对所述条带载体上的所述晶片上封装结构执行单体化工艺以形成多个叠层封装结构。
10.根据权利要求9所述的叠层封装结构的制造方法，所述单体化工艺还包括：
对所述条带载体上的所述经重构晶片进行切割以形成所述多个叠层封装结构。
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