TWI681470B - 疊層封裝結構的製造方法 - Google Patents

疊層封裝結構的製造方法 Download PDF

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TWI681470B
TWI681470B TW107139398A TW107139398A TWI681470B TW I681470 B TWI681470 B TW I681470B TW 107139398 A TW107139398 A TW 107139398A TW 107139398 A TW107139398 A TW 107139398A TW I681470 B TWI681470 B TW I681470B
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Taiwan
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package
semiconductor device
base portion
conductive bumps
carrier
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TW107139398A
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TW202002100A (zh
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郭炫廷
謝靜華
陳正庭
林修任
裴浩然
蔡鈺芃
張家綸
曹智強
宇軒 鍾
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台灣積體電路製造股份有限公司
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Publication of TW202002100A publication Critical patent/TW202002100A/zh

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Abstract

一種疊層封裝結構的製造方法包括以下步驟。在條帶載體上提供第一封裝，其中所述第一封裝包括經包封半導體裝置、設置在所述經包封半導體裝置上的第一重佈線結構及設置在所述第一重佈線結構上且貼合到所述條帶載體的多個導電凸塊。通過多個電性端子利用熱壓合製程將第二封裝設置在所述第一封裝上，所述熱壓合製程使所述導電凸塊變形成多個經變形導電凸塊。所述經變形導電凸塊中的每一者包括對所述第一重佈線結構進行連接的基底部分及對所述基底部分進行連接的頂端部分，且所述基底部分的曲率實質上小於所述頂端部分的曲率。

Description

疊層封裝結構的製造方法
本發明實施例是有關於一種疊層封裝結構的製造方法。
自積體電路(integrated circuit，IC)的發明以來，半導體行業已因各種電子元件(即，電晶體、二極體、電阻器、電容器等)的集成密度不斷提高而經歷了快速發展。在很大程度上，集成密度的此種提高來自於最小特徵尺寸(minimum feature size)的重複減小，此使得更多元件能夠集成到給定區域中。
這些集成上的改善基本上是二維(two-dimensional，2D)性質的，因為集成元件佔據的體積基本上位於半導體晶圓的表面上。儘管微影的明顯改善已使得二維積體電路的形成得到相當大的改善，然而可在二維中實現的密度存在實體(physical)限制。這些限制中的一者是製作這些元件所需要的最小尺寸。此外，當將更多裝置設置於一個晶片中時，需要更複雜的設計。
在嘗試進一步提高電路密度時，已探究了三維(three-dimensional，3D)積體電路。在三維積體電路的典型形成製程中，將兩個晶粒結合在一起，且在每一晶粒與基板上的接觸墊之間形成電性連接。舉例來說，一種嘗試涉及了將兩個晶粒堆疊結合。然後將經堆疊的晶粒結合到載體基板，且焊線將每一晶粒上的電性耦合接觸墊結合到載體基板上的接觸墊。
本發明實施例是針對一種疊層封裝結構的製造方法，其可簡化製造製程，可降低生產成本，且可提高疊層封裝結構的生產率。
根據本發明的實施例，一種疊層封裝結構的製造方法包括以下步驟。在條帶載體上提供第一封裝，其中所述第一封裝包括經包封半導體裝置、設置在所述經包封半導體裝置上的第一重佈線結構及設置在所述第一重佈線結構上且貼合到所述條帶載體的多個導電凸塊。通過多個電性端子利用熱壓合製程將第二封裝設置在所述第一封裝上，所述熱壓合製程使所述導電凸塊變形成多個經變形導電凸塊。所述經變形導電凸塊中的每一者包括連接所述第一重佈線結構的基底部分及連接所述基底部分的頂端部分，且所述基底部分的曲率實質上小於所述頂端部分的曲率。
根據本發明的實施例，一種疊層封裝結構的製造方法包括以下步驟。在條帶載體上提供第一封裝，其中所述第一封裝包括 經重構晶圓及設置在所述經重構晶圓的第一側上且貼合到所述條帶載體的多個導電凸塊，且所述經重構晶圓包括由包封材料包封的多個半導體裝置。通過多個電性端子利用熱壓合製程將第二封裝設置在所述經重構晶圓的第二側上，所述熱壓合製程使所述導電凸塊變形成多個經變形導電凸塊。所述經變形導電凸塊中的每一者包括連接所述經重構晶圓的基底部分及連接所述基底部分的頂端部分，且所述基底部分的曲率實質上小於所述頂端部分的曲率。
根據本發明的實施例，一種疊層封裝結構的製造方法包括以下步驟。在載體基板上形成第一封裝，其中所述第一封裝包括經重構晶圓及設置在所述經重構晶圓的第一側上的多個導電凸塊，且所述經重構晶圓包括由包封材料所包封的多個半導體裝置。將具有所述載體基板的所述第一封裝設置在條帶載體上。將所述載體基板從條帶載體上的第一封裝剝離。通過熱壓合製程將第二封裝設置在所述經重構晶圓的第二側上以形成晶圓上封裝結構，所述熱壓合製程通過將所述導電凸塊壓抵所述條帶載體而使所述導電凸塊變形成多個經變形導電凸塊。所述經變形導電凸塊中的每一者包括基底部分及頂端部分，且所述基底部分的曲率不同於所述頂端部分的曲率。對所述條帶載體上的所述晶圓上封裝結構執行單體化製程以形成多個疊層封裝結構。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10‧‧‧疊層封裝結構
10’‧‧‧晶圓上封裝結構
100、100’‧‧‧第一封裝
101‧‧‧經包封半導體裝置
105‧‧‧經重構晶圓
110‧‧‧半導體裝置/裝置晶粒
110’‧‧‧半導體裝置
110a、110a’‧‧‧第一半導體裝置
110b、110b’‧‧‧第二半導體裝置
112‧‧‧基板
113‧‧‧接觸墊
114‧‧‧導通孔
116、116’、143‧‧‧介電層
120、120’‧‧‧包封材料
130‧‧‧導電柱
140‧‧‧重佈線結構/第一重佈線結構
142‧‧‧重佈線路
143‧‧‧介電層
144‧‧‧凸塊下金屬層
160‧‧‧圖案化介電層
162‧‧‧開口
165‧‧‧焊料
170‧‧‧重佈線結構/第二重佈線結構
180‧‧‧導電凸塊
180’‧‧‧經變形導電凸塊
182‧‧‧頂端部分
184‧‧‧基底部分
200‧‧‧第二封裝
210‧‧‧電性端子
300‧‧‧載體基板
310‧‧‧黏合層
400‧‧‧條帶載體
410‧‧‧框架結構
500‧‧‧刀具
D1、D2‧‧‧最大直徑
H1、h1、h2‧‧‧高度
T1‧‧‧厚度
結合附圖閱讀以下詳細說明，會最好地理解本發明實施例的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1到圖13示出根據本揭露一些示例性實施例在疊層封裝結構的製造中的中間階段的剖視圖。
圖14示出根據本揭露一些示例性實施例的疊層封裝結構的導電凸塊的剖視圖。
圖15示出根據本揭露一些示例性實施例的疊層封裝結構的經變形導電凸塊的剖視圖。
圖16示出根據本揭露一些示例性實施例的疊層封裝結構的經變形導電凸塊的示意性俯視圖。
以下揭露內容提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及配置的具體實例以簡化本發明實施例。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而 使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)”、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外更囊括裝置在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對性描述語可同樣相應地進行解釋。
另外，為易於說明，本文中可能使用例如“第一(first)”、“第二(second)”、“第三(third)”、“第四(fourth)”等用語來闡述與圖中所示者相似或不同的一個或多個元件或特徵，且可依據呈現次序或本說明的上下文來可互換地使用所述用語。
還可包括其他特徵及製程。舉例來說，可包括測試結構以說明進行三維封裝或三維積體電路裝置的驗證測試。測試結構可包括例如形成於重佈線層中或基板上的測試墊，所述測試墊使得能夠測試三維封裝或3DIC、使用探針(probe)和/或探針卡(probe card)等。可對中間結構及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合包括對已知良好晶粒的中間驗證的測試方法一起使用，以提高良率(yield)並降低成本。
圖1到圖13示出根據本揭露一些示例性實施例在疊層封裝結構的製造中的中間階段的剖視圖。應注意，將關於特定上下文中的一些實施例、即疊層封裝結構來闡述本揭露。然而，本揭露中的概念也可適用於其他半導體結構或電路。根據各種實施例提供適用於疊層封裝結構的半導體封裝、疊層封裝結構及形成疊層封裝結構的方法。根據一些實施例對形成疊層封裝結構的中間階段進行說明。對各實施例的變型進行論述。在所有各圖及說明性實施例中，相同的參考編號用於標示相同的元件。
在一些實施例中，形成圖13所示疊層封裝結構的中間階段闡述如下。參照圖1，提供載體基板300，且可在載體基板300上設置黏合層310。在一些實施例中，載體基板300可包括例如矽系材料(例如玻璃、陶瓷或氧化矽)或其他材料(例如氧化鋁)、這些材料的任一組合等。載體基板300為平坦的，以便於例如半導體裝置110/110’(未示於圖1中，但以下關於圖2及圖4進行示出及論述)等半導體裝置的貼合。黏合劑層310可放置在載體基板300上，以有助於上覆(overlying)結構(例如，重佈線結構170)的黏附。在實施例中，黏合劑層310可包括紫外膠(ultra-violet glue)，所述紫外膠在暴露於紫外光時會減低或喪失其黏合性質。然而，也可使用例如壓敏黏合劑(pressure sensitive adhesive)、可輻射固化黏合劑(radiation curable adhesive)、光熱轉換釋放塗層(light to heat conversion release coating，LTHC)、環氧化物、其組合等其他類型的黏合劑。可將黏合劑層310以在壓力下易於 變形的半液體形式或凝膠形式放置到載體基板300上。
在一些實施例中，可在載體基板300上或在黏合層310(如果存在)上形成第一封裝(例如，圖6所示的第一封裝100)。在一些實施例中，第一封裝100是集成扇出型(Integrated Fan-Out，InFO)封裝，但作為另一選擇也可使用任何合適的封裝。在本實施例中，第一封裝100包括經重構晶圓(reconstructed wafer)(例如，圖6所示的經重構晶圓105)及設置在經重構晶圓的第一側上的多個導電凸塊(例如，圖6所示導電凸塊180)。經重構晶圓包括由包封材料120所包封的多個半導體裝置110。形成第一封裝100可包括以下步驟。
現在參照圖1，可選擇性地在載體基板300上或在黏合層310(如果存在)上形成(第二)重佈線結構170。在一些實施例中，重佈線結構170可包括至少一個絕緣層。絕緣層可放置在黏合劑層310之上，且絕緣層可用於對例如半導體裝置110/110’提供保護(在半導體裝置110/110’貼合後)。在實施例中，絕緣層可為聚苯並噁唑(polybenzoxazole，PBO)，但作為另一選擇也可利用例如聚醯亞胺(polyimide)或聚醯亞胺衍生物等任何合適的材料。可利用例如旋轉塗布製程來將絕緣層設置為介於約2μm與約15μm之間(例如約5μm)的厚度，但作為另一選擇也可利用任何合適的方法及厚度。在一些實施例中，重佈線結構170還可包括電路層，所述電路層用於在半導體裝置110/110’貼合後電性連接半導體裝置110/110’。
然後，在載體基板300上提供多個導電柱(through vias)130，且導電柱130環繞欲設置半導體裝置110/110’的至少一個裝置區域。在本實施例中，導電柱130形成在位於載體基板300上的重佈線結構170上且電性連接到重佈線結構170，但本揭露並非僅限於此。在其他實施例中，導電柱130可為預製的，然後再將導電柱130放置在載體基板300上。
在導電柱130形成在載體基板300上的實施例中，形成導電柱130可包括以下步驟。首先，可在重佈線結構170之上形成晶種層。晶種層為導電材料的薄層，此有助於在後續處理步驟期間形成更厚的層。舉例來說，晶種層可包括約1,000Å厚的鈦層、然後是約5,000Å厚的銅層。可依據期望的材料使用例如濺射製程、蒸鍍製程或等離子體增強型化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)製程等製程來形成晶種層。
然後，在晶種層之上形成光阻層。在實施例中，光阻層可利用例如旋轉塗布技術放置在晶種層上。一旦設置光阻層，便可通過以下方式對光阻層進行圖案化：將光阻層曝光於圖案化能量源(例如，圖案化光源)，由此引發光阻層的被曝光於圖案化光源的那些部分的物理變化。然後對被曝光的光阻層施加顯影劑，以利用所述物理變化並依據期望的圖案選擇性地移除光阻層的被曝光部分或光阻層的未曝光部分。形成於光阻層上的圖案是用於形成導電柱130的圖案。導電柱130形成於此種位置以便位於隨後貼合的半導體裝置110/110’的不同側上。換句話說，半導體裝置110/110’ 被導電柱130環繞。然而，作為另一選擇也可利用導電柱130的圖案的任何合適的配置。
然後，在光阻層中形成導電柱130。在實施例中，導電柱130包括一種或多種導電材料(例如銅、鎢、其他導電材料等)，且可例如通過電鍍、無電鍍覆等形成。在實施例中，使用電鍍製程在光阻層的開口內鍍覆晶種層的被暴露導電區域。在用光阻層及晶種層形成導電柱130之後，便可使用合適的移除製程來移除光阻層。在實施例中，可使用等離子體灰化製程來移除光阻層，因此可升高光阻層的溫度直到光阻層經歷熱分解且可被移除。然而，作為另一選擇也可利用任何其他合適的製程，例如濕式剝除。移除光阻層可暴露出晶種層的下面的部分。
然後，可通過例如濕式蝕刻製程或乾式蝕刻製程來移除晶種層的被暴露部分(例如，未被導電柱130覆蓋的那些部分)。舉例來說，在乾式蝕刻製程中，可使用導電柱130作為罩幕將反應劑朝晶種層引導。作為另一選擇，可噴塗蝕刻劑或以其他方式使蝕刻劑接觸晶種層，以移除晶種層的被暴露部分。在已蝕刻掉晶種層的被暴露部分之後，在導電柱130之間暴露出重佈線結構170的一部分。此時，實質上完成了導電柱130的形成。
現在參照圖2，在一些實施例中，可在載體基板300上及在導電柱130內或導電柱130之間提供至少一個半導體裝置110’(圖中示出多個半導體裝置110’，但並非僅限於此)。在實施例中，半導體裝置110’可包括至少一個半導體裝置組(圖中示出多個半 導體裝置組，但並非僅限於此)，且半導體裝置組中的每一者可包括第一半導體裝置110a’及第二半導體裝置110b’。在每一組中，第一半導體裝置110a’與第二半導體裝置110b’通過例如(第一)重佈線結構140(未示於圖2中但以下關於圖5進行示出及論述)進行電性連接，且可一起用於為最終用戶提供期望的功能。在實施例中，第一半導體裝置110a’及第二半導體裝置110b’可使用例如黏合材料貼合到載體基板300(或重佈線結構170)，但作為另一選擇也可利用任何合適的貼合方法。導電柱130可環繞半導體裝置110’的每一組。通過此種配置，對於批量生產來說可同時形成多個疊層封裝結構。為簡潔及清晰起見，以下製造製程是針對一個疊層封裝結構進行闡述。
在一些實施例中，半導體裝置110’可為其中包括邏輯電路的邏輯裝置晶粒。在一些示例性實施例中，半導體裝置110’是為移動應用而設計的晶粒，且可例如包括電源管理積體電路(Power Management Integrated Circuit，PMIC)晶粒及收發器(TRX)晶粒。應注意，更多或更少的半導體裝置110’可放置在載體基板300之上且彼此齊平。
在一些示例性實施例中，半導體裝置110’中的每一者可包括基板112、多個主動裝置(圖中未示出)、多個接觸墊113、至少一個介電層116’及多個導通孔114。導通孔114(例如銅通孔)可形成在半導體裝置110’的主動表面(例如，頂表面)上且電性耦合到基板112上的接觸墊113。基板112可包括經摻雜或未經摻 雜的塊體矽(bulk silicon)或者絕緣體上矽(silicon-on-insulator，SOI)基板的主動層。一般來說，SOI基板包括一層半導體材料，例如矽、鍺、矽鍺、SOI、絕緣體上矽鍺(silicon germanium on insulator，SGOI)或其組合。可使用的其他基板包括多層式基板、梯度(gradient)基板或混合方向(hybrid orientation)基板。主動裝置包括可用來產生半導體裝置110’的設計的期望結構及功能要求的各種主動裝置及被動裝置(例如電容器、電阻器、電感器等)。主動裝置可利用任何合適的方法形成在基板112內或基板112上。
在一些實施例中，介電層116’可形成在半導體裝置110’的主動表面上，且可覆蓋導通孔114的頂表面。在其他實施例中，介電層116’的頂表面可與導通孔114的頂表面實質上齊平。作為另一選擇，可省略介電層116’，且導通孔114從半導體裝置110’的主動表面突出。介電層116’可由例如氧化矽、氮化矽、低介電常數介電質(例如，摻雜碳的氧化物)、極低介電常數介電質(例如，摻雜多孔碳的二氧化矽)、其組合等一或多種合適的介電材料製成。可通過例如化學氣相沉積(chemical vapor deposition，CVD)等製程來形成介電層116’，但也可利用任何合適的製程。
在一些實施例中，導電柱130的頂端可與導通孔114的頂表面實質上齊平。在其他實施例中，導電柱130的頂端可實質上高於導通孔114的頂表面。作為另一選擇，導電柱130的頂端可實質上低於導通孔114的頂表面，但實質上高於導通孔114的底表面。
現在參照圖3，在一些實施例中，由包封材料120’來包封載體基板300上的半導體裝置110’及導電柱130。換句話說，在載體基板300上形成包封材料120’，以包封導電柱130及半導體裝置110’。在一些實施例中，包封材料120’填充半導體裝置110’與導電柱130之間的間隙，且可接觸重佈線結構170。包封材料120’可包括例如聚醯亞胺、聚苯硫醚(polyphenylene sulfide，PPS)、聚醚醚酮(polyetheretherketone，PEEK)、聚醚碸(polyethersulfone，PES)、耐熱水晶樹脂、其組合等模制化合物樹脂。可在模製裝置(圖3中未單獨示出)中執行半導體裝置110’及導電柱130的包封。可將包封材料120’放置在模製裝置的模製空腔內，或者可通過注射口將包封材料120’注射到模製空腔中。
一旦已將包封材料120’放置到模製空腔中以使得包封材料120’包封載體基板300、半導體裝置110’及導電柱130，便可將包封材料120’固化以硬化包封材料120’來實現最佳保護。另外，可在包封材料120’內包括引發劑和/或催化劑以更好地控制固化製程。在一些實施例中，包封材料120’的頂表面可高於導電柱130的頂端及介電層116’的頂表面。即，包封材料120’覆蓋導電柱130的頂端及介電層116’的頂表面。
現在參照圖4，可對包封材料120’(及介電層116’)執行薄化製程，以顯露出導電柱130的頂端及導通孔114的頂表面以用於進一步處理。薄化製程可為例如利用化學蝕刻劑及磨料使包封材料120’、半導體裝置110’反應且研磨掉包封材料120’、半導 體裝置110’直到導電柱130、導通孔114已被顯露出的機械研磨或化學機械拋光(Chemical Mechanical Polishing，CMP)製程。所得結構示出於圖4中。在執行薄化製程之後，導電柱130的頂端與導通孔114的頂表面實質上齊平，且與包封材料120的頂表面及介電層116的頂表面實質上齊平，如圖4所示。然而，儘管上述CMP製程被呈現為一個說明性實施例，但其並不旨在限制所述實施例。作為另一選擇也可使用任何其他合適的移除製程來將包封材料120、半導體裝置110薄化並暴露出導電柱130。舉例來說，作為另一選擇可利用一系列化學蝕刻劑。作為另一選擇可利用此製程及任何其他合適的製程來將包封材料120、半導體裝置110及導電柱130薄化，且所有這些製程均旨在包括於實施例的範圍內。
在說明書通篇中，將圖4所示的包括半導體裝置110(包括圖4所示第一半導體裝置110a及第二半導體裝置110b)、導電柱130及包封材料120的所得結構稱為經包封半導體裝置101，經包封半導體裝置101可在所述製程中具有晶圓形式。因此，在經包封半導體裝置101中，半導體裝置110設置在晶粒區域處，導電柱130延伸穿過晶粒區域外的經包封半導體裝置101，且包封材料120包封半導體裝置110及導電柱130。換句話說，包封材料120將半導體裝置110包封在包封材料120中，且導電柱130延伸穿過包封材料120。
現在參照圖5，在經包封半導體裝置101的第一側上形成第一重佈線結構140。第一重佈線結構140電性連接到半導體裝置 110及導電柱130。在一些實施例中，在經包封半導體裝置101(包括包封材料120及半導體裝置110)之上形成第一重佈線結構140，以連接到半導體裝置110的導通孔114及導電柱130。在一些實施例中，第一重佈線結構140也可將導通孔114與導電柱130內連。可通過以下步驟來形成第一重佈線結構140：例如沉積導電層，對導電層進行圖案化以形成重佈線路142，局部地覆蓋重佈線路142，且利用介電層143填充重佈線路142之間的間隙等。重佈線路142的材料可包括金屬或金屬合金，所述金屬或金屬合金包括鋁、銅、鎢和/或其合金。介電層143可由例如氧化物、氮化物、碳化物、碳氮化物、其組合和/或其多個層等介電材料形成。重佈線路142形成在介電層143中，且電性連接到裝置晶粒110及導電柱130。在經包封半導體裝置101設置在重佈線結構170上的實施例中，第二重佈線結構170位於經包封半導體裝置101的與設置有第一重佈線結構140的第一側相對的第二側上。即，第一重佈線結構140與第二重佈線結構170分別設置在經包封半導體裝置101的相對兩側上。
在說明書通篇中，將圖5所示的包括第一重佈線結構140、經包封半導體裝置101(及第二重佈線結構170)的所得結構稱為經重構晶圓105，經重構晶圓105在所述製程中具有晶圓形式。
現在參照圖6，在第一重佈線結構140上設置多個導電凸塊180。換句話說，在經重構晶圓105的側面上設置導電凸塊180。在一些實施例中，可通過濺射、蒸鍍或無電鍍覆等在第一重佈線結 構140上形成凸塊下金屬(Under Bump Metallurgy，UBM)層144，且可在UBM層144上設置導電凸塊180。在一些實施例中，根據一些示例性實施例，也可在第一重佈線結構140上設置至少一個集成被動裝置(Integrated Passive Device，IPD)。形成導電凸塊180可包括：將焊料球放置在UBM層144上(或第一重佈線結構140上)，然後對焊料球進行迴焊。在替代實施例中，形成導電凸塊180可包括：執行鍍覆製程以在UBM層144上(或第一重佈線結構140上)形成焊料區，然後對焊料區進行迴焊。IPD可利用例如薄膜及微影處理等標準晶圓製作技術來製作，且可通過例如覆晶接合或打線接合等安裝在UBM層144上(或第一重佈線結構140上)。
在說明書通篇中，將圖6所示的包括第一重佈線結構140、經包封半導體裝置101、第二重佈線結構170及導電凸塊180的所得結構稱為第一封裝100，第一封裝100可在所述製程中具有晶圓形式。
圖14示出根據本揭露一些示例性實施例的疊層封裝結構的導電凸塊的剖視圖。現在參照圖7及圖14，在載體基板300上形成第一封裝100之後，可將具有載體基板300的第一封裝100翻轉且通過將導電凸塊180貼合到條帶載體400而將具有載體基板300的第一封裝100設置在條帶載體400上。用以承載具有載體基板300的第一封裝100的條帶載體400還可包括框架結構410，框架結構410可用於在後續的製程期間為此結構提供支撐及穩定 性的金屬環。在一些實施例中，條帶載體400是由例如具有可撓性的聚合物材料製成。在一個實施例中，條帶載體400的楊氏模量(young’s modulus)實質上小於10Mpa，且條帶載體400的玻璃轉變溫度(Tg)實質上低於室溫。即，當在室溫下或高於室溫使用條帶載體400時，條帶載體400處於橡膠狀態，其中條帶載體400為柔軟且具有可撓性的。因此，當導電凸塊180貼合到條帶載體400時，條帶載體400會變形且包圍導電凸塊180中的每一者的至少下部部分，如圖14所示。
現在參照圖7及圖8，將載體基板300從條帶載體400上的第一封裝100剝離。可使用例如熱製程來改變黏合層310的黏性從而將載體基板300剝離。在實施例中，利用例如紫外(UV)鐳射、二氧化碳(CO2)鐳射或紅外(infrared，IR)鐳射等能量源來輻照及加熱黏合層310，直到黏合層310喪失至少部份黏性。一旦執行，便可將載體基板300及黏合層310從第一封裝100實體地分離及移除，如圖8所示。
在將載體基板300剝離之後，可顯露出第二重佈線結構170。在第二重佈線結構170被省略的實施例中，可執行研磨製程以輕微地研磨包封材料120、半導體裝置110的背面及導電柱130的底端。在其他實施例中，可省略研磨製程。
現在參照圖9，在一些實施例中，可在經重構晶圓105上形成圖案化介電層160，以提供對第二重佈線結構170及其他下伏(underlying)結構的保護及隔離。在實施例中，圖案化介電層160 可為聚苯並噁唑(PBO)，但作為另一選擇也可利用例如聚醯亞胺或聚醯亞胺衍生物等任何合適的材料。可通過以下方式來形成圖案化介電層160：使用例如旋轉塗布製程放置介電層，然後對介電層進行圖案化以形成顯露出經重構晶圓105的多個電性接觸件(例如，第二重佈線結構170的電性接觸件)的多個開口162。可利用合適的微影罩幕及蝕刻製程來形成開口162，但也可使用任何合適的製程。
現在參照圖9及圖10，在一些實施例中，在開口162中形成多種焊料165。在一些實施例中，使用網版印刷製程來形成焊料165。舉例來說，在印刷表面(例如，第二重佈線結構170)之上放置網版框架(screen frame)，且將焊料165沉積到網版框架上。然後，可在整個網版框架上驅動可撓性刮板等以推壓焊料165通過網版框架的開口。然而，也可使用任何合適的製程在開口162中設置焊料165。
現在參照圖11，通過多個電性端子210將至少一個第二封裝200(在此中示出多個第二封裝200)設置在第一封裝100上。在實施例中，第二封裝200用於分別與半導體裝置110(包括圖4所示第一半導體裝置110a及第二半導體裝置110b)一起運作以為最終用戶提供期望的功能。在第一封裝100中具有一組半導體裝置110(例如，包括一個第一半導體裝置110a及一個第二半導體裝置110b)的實施例中，一個第二封裝200可設置在第一封裝100上。
在實施例中，第二封裝200可包括例如記憶體裝置等半導體裝置，所述半導體裝置可用於為半導體裝置110提供所存儲的資料。在此種實施例中，半導體裝置110可包括記憶體控制模組(圖中未示出)，所述記憶體控制模組除由半導體裝置110提供的其他功能以外還對第二封裝200的記憶體裝置提供控制功能。然而，在其他實施例中，第二封裝200可包括自身的記憶體控制模組。
在一些實施例中，通過以下方式將第二封裝200設置在第一封裝100上：首先，使電性端子210與圖案化介電層160的開口對準，且將電性端子210放置成實體地接觸焊料165。因此，第二封裝200電性連接到焊料165。一旦接觸，便可使用例如熱壓合製程等製程將電性端子210結合到第一封裝100。作為另一選擇可利用任何合適的結合方法將第二封裝200結合到第一封裝100。在熱壓合製程(包括迴焊製程)的高溫下將導電凸塊180壓抵在具有可撓性的條帶載體400上，導電凸塊180會變形成多個經變形導電凸塊180’，如圖11所示。
在說明書通篇中，將圖11所示的包括晶圓形式的第一封裝100及安裝在第一封裝100上的第二封裝200的所得結構稱為晶圓上封裝(package on wafer)結構10’，晶圓上封裝結構10’在所述製程中具有晶圓形式。
圖15示出根據本揭露一些示例性實施例的疊層封裝結構的經變形導電凸塊的剖視圖。圖16示出根據本揭露一些示例性實 施例的疊層封裝結構的經變形導電凸塊的示意性俯視圖。現在參照圖15及圖16，在一些實施例中，經變形導電凸塊180’中的每一者包括頂端部分182及基底部分184。基底部分184連接到第一重佈線結構140，且頂端部分182連接到基底部分184。頂端部分182與基底部分184直接彼此連接並一體成型。
由於在高溫下條帶載體400的包圍，導電凸塊接觸條帶載體400的頂端受到擠壓並變形成頂端部分182。因此，基底部分184的曲率不同於頂端部分182的曲率。換句話說，經變形導電凸塊180’中的每一者經歷頂端部分182與基底部分184之間的曲率變化。此曲率變化可為漸進變化，但在其他實施例中，曲率變化也可為更急劇的變化。從圖16所示經變形導電凸塊180’的俯視圖，可以看出經變形導電凸塊180’不具有均勻的圓頂形狀。為了實現變形，條帶載體400的厚度T1實質上大於每一經變形導電凸塊180’的高度H1的20%，且條帶載體400的厚度T1實質上小於每一經變形導電凸塊180’的高度H1的80%，即20% H1<T1<80% H1。在一些實施例中，條帶載體400的厚度T1對頂端部分182的高度h1的比率可實質上介於50%到150%之間。在一些實施例中，頂端部分182的高度h1實質上小於基底部分184的高度h2。
在一些實施例中，基底部分184的曲率實質上小於頂端部分182的曲率。在幾何學上，曲率是測量曲線的單位切向量(unit tangent vector)旋轉的速度。也就是說，在一些實施例中，基底部分184的曲線的單位切向量的變化略小於頂端部分182的曲線的 單位切向量的變化。換句話說，頂端部分182的曲率可經歷更急劇的轉彎。在一些實施例中，頂端部分182的最大直徑D1實質上小於基底部分184的最大直徑D2。舉例來說，頂端部分182的最大直徑D1對基底部分184的最大直徑D2的比率(即，D1/D2)實質上介於50%到90%範圍內。
由於經變形導電凸塊180’的變形，條帶載體400與經變形導電凸塊180’之間的接觸面積增加，因而可提高條帶載體400與經變形導電凸塊180’之間的結合強度。因此，可以更牢固及更穩定的方式將第一封裝100固定到條帶載體400上，以提高在晶圓上封裝結構10’上執行的結合製程的良率。另外，條帶載體400通過在結合製程及例如單體化製程等後續製程期間包圍經變形導電凸塊180’的至少一部分來提供對經變形導電凸塊180’的可靠保護。
現在參照圖12，對條帶載體400上的晶圓上封裝結構10’執行單體化製程，以形成彼此獨立的多個疊層封裝結構10。因此，經單體化第一封裝中的每一者可包括第一半導體裝置110a中的一者及第二半導體裝置110b中的一者。在實施例中，可使用刀具500執行單體化製程以切穿第一封裝100的經重構晶圓105。因此，第一封裝100的一個區段(例如，包括第一半導體裝置110a中的一者及第二半導體裝置110b中的一者)從另一區段分離以形成多個疊層封裝結構10。疊層封裝結構10中的每一者包括第一封裝100’以及結合到第一封裝100’的第二封裝200。
然而，如所屬領域中的一般技術人員將知，利用刀具將晶圓上封裝結構10’單體化僅為一個說明性實施例，而並不旨在進行限制。作為另一選擇也可利用對晶圓上封裝結構10’進行單體化的替代方法，例如利用一種或多種蝕刻劑對晶圓上封裝結構10’進行分離並形成疊層封裝結構10。作為另一選擇也可利用這些方法及任何其他合適的方法來進行單體化製程。
現在參照圖13，通過包括多個戳針(poker pin)600的設備將所述多個疊層封裝結構10從條帶載體400分離，所述多個戳針600在條帶載體400下方進行戳刺。在一些實施例中，戳針600中的每一者位於與剩餘戳針600共同的平面上。將所述多個疊層封裝結構10與條帶載體400一起放置在設備上，因此戳針600被配置成在條帶載體400的背面上進行戳刺。在實施方案中的一者中，可在戳針600之間形成真空條件，且真空條件將條帶載體400的至少部分朝戳針600牽拉且因此減小疊層封裝結構10與條帶載體400之間的接觸面積。在一些實施例中，可通過對至少條帶載體400施加熱來促進移除製程的進行，以使得疊層封裝結構10與條帶載體400之間的黏附力進一步減小。
通過此種配置，在疊層封裝結構10的製程中，對載體基板300進行剝離的剝離製程、將第二封裝200安裝到第一封裝100上的結合及迴焊製程以及單體化製程全部在條帶載體400上執行。因此，可簡化製程，可降低生產成本，且可提高疊層封裝結構10的生產率。另外，通過在條帶載體400上執行結合及迴焊製程從 而引起經變形導電凸塊180’變形，條帶載體400與經變形導電凸塊180’之間的結合強度得到提高。因此，在晶圓上封裝結構10’上執行的結合製程的良率也得到提高。此外，條帶載體400通過包圍經變形導電凸塊180’的至少一部分來提供對經變形導電凸塊180’的可靠保護。
基於以上論述，可看出本揭露提供各種優點。然而，應理解，本文中未必論述所有優點，其他實施例可提供不同優點，且對於所有實施例來說並不需要特定優點。
根據本揭露的一些實施例，一種疊層封裝結構的製造方法包括以下步驟。在條帶載體上提供第一封裝，其中所述第一封裝包括經包封半導體裝置、設置在所述經包封半導體裝置上的第一重佈線結構及設置在所述第一重佈線結構上且貼合到所述條帶載體的多個導電凸塊。通過多個電性端子利用熱壓合製程將第二封裝設置在所述第一封裝上，所述熱壓合製程使所述導電凸塊變形成多個經變形導電凸塊。所述經變形導電凸塊中的每一者包括連接所述第一重佈線結構的基底部分及連接所述基底部分的頂端部分，且所述基底部分的曲率實質上小於所述頂端部分的曲率。
根據本揭露的一些實施例，所述頂端部分的一最大直徑實質上小於所述基底部分的一最大直徑。
根據本揭露的一些實施例，所述頂端部分的一最大直徑對所述基底部分的一最大直徑的一比率實質上介於50%到90%之間。
根據本揭露的一些實施例，所述條帶載體的一厚度大於所述經變形導電凸塊中的每一者的一高度的20%，且小於所述經變形導電凸塊中的每一者的所述高度的80%。
根據本揭露的一些實施例，提供所述經包封半導體裝置的方法包括：提供多個導電柱；提供一半導體裝置，其中所述半導體裝置被所述多個導電柱環繞；以及由一包封材料包封所述半導體裝置及所述多個導電柱。
根據本揭露的一些實施例，所述經包封半導體裝置設置在一第二重佈線結構上，且所述第二重佈線結構位於所述經包封半導體裝置的與所述第一側相對的一第二側上。
根據本揭露的一些實施例，所述的疊層封裝結構的製造方法更包括：在所述經包封半導體裝置上形成一圖案化介電層，其中所述圖案化介電層包括顯露出所述經包封半導體裝置的多個電性接觸件的多個開口；以及在所述多個開口中形成多個焊料，且所述第二封裝設置在所述圖案化介電層上並電連接到所述多個焊料。
根據本揭露的一些實施例，一種疊層封裝結構的製造方法包括以下步驟。在條帶載體上提供第一封裝，其中所述第一封裝包括經重構晶圓及設置在所述經重構晶圓的第一側上且貼合到所述條帶載體的多個導電凸塊，且所述經重構晶圓包括由包封材料包封的多個半導體裝置。通過多個電性端子利用熱壓合製程將第二封裝設置在所述經重構晶圓的第二側上，所述熱壓合製程使所述導電凸塊變形成多個經變形導電凸塊。所述經變形導電凸塊中 的每一者包括連接所述經重構晶圓的基底部分及連接所述基底部分的頂端部分，且所述基底部分的曲率實質上小於所述頂端部分的曲率。
根據本揭露的一些實施例，所述頂端部分的一最大直徑實質上小於所述基底部分的一最大直徑。
根據本揭露的一些實施例，所述頂端部分的一最大直徑對所述基底部分的一最大直徑的一比率實質上介於50%到90%之間。
根據本揭露的一些實施例，所述條帶載體的一楊氏模量小於10Mpa。
根據本揭露的一些實施例，形成所述經重構晶片的方法包括：提供多個導電柱；提供所述多個半導體裝置，其中所述多個半導體裝置被所述多個導電柱環繞；由所述包封材料包封所述多個半導體裝置及所述導電柱；以及在所述經重構晶片的所述第一側上形成一第一重佈線結構，其中所述第一重佈線結構在所述包封材料及所述多個半導體裝置上延伸。
根據本揭露的一些實施例，所述經包封半導體裝置設置在一第二重佈線結構上，且所述第二重佈線結構位於所述經包封半導體裝置的與所述第一側相對的一第二側上。
根據本揭露的一些實施例，所述的疊層封裝結構的製造方法更包括：在所述經包封半導體裝置上形成一圖案化介電層，其中所述圖案化介電層包括顯露出所述經包封半導體裝置的多個電 性接觸件的多個開口；以及在所述開口中形成多種焊料，且所述第二封裝設置在所述圖案化介電層上並電連接到所述焊料。
根據本揭露的一些實施例，一種疊層封裝結構的製造方法包括以下步驟。在載體基板上形成第一封裝，其中所述第一封裝包括經重構晶圓及設置在所述經重構晶圓的第一側上的多個導電凸塊，且所述經重構晶圓包括由包封材料所包封的多個半導體裝置。將具有所述載體基板的所述第一封裝設置在條帶載體上。將所述載體基板從條帶載體上的第一封裝剝離。通過熱壓合製程將第二封裝設置在所述經重構晶圓的第二側上以形成晶圓上封裝結構，所述熱壓合製程通過將所述導電凸塊壓抵所述條帶載體而使所述導電凸塊變形成多個經變形導電凸塊。所述經變形導電凸塊中的每一者包括基底部分及頂端部分，且所述基底部分的曲率不同於所述頂端部分的曲率。對所述條帶載體上的所述晶圓上封裝結構執行單體化製程以形成多個疊層封裝結構。
根據本揭露的一些實施例，形成所述經重構晶片的方法包括：在所述載體基板上提供多個導電柱；在所述載體基板上提供所述多個半導體裝置，其中所述半導體裝置被所述導電柱環繞；由所述包封材料包封所述多個半導體裝置及所述導電柱；以及在所述經重構晶片的所述第一側上形成一第一重佈線結構，其中所述第一重佈線結構在所述包封材料及所述多個半導體裝置之上延伸。
根據本揭露的一些實施例，在所述載體基板上形成所述第一封裝更包括：在所述載體基板上提供所述多個半導體裝置及 所述多個導電柱之前在所述載體基板上形成一第二重佈線結構。
根據本揭露的一些實施例，所述的疊層封裝結構的製造方法更包括：在所述經重構晶片上形成一圖案化介電層，其中所述圖案化介電層包括顯露出所述經重構晶片的多個電性接觸件的多個開口；以及在所述多個開口中形成多個焊料，且所述第二封裝設置在所述圖案化介電層上並電連接到所述多個焊料。
根據本揭露的一些實施例，所述單體化製程更包括：對所述條帶載體上的所述經重構晶片進行切割以形成所述多個疊層封裝結構。
根據本揭露的一些實施例，所述單體化製程更包括：通過以多個在所述條帶載體下方進行戳刺的戳針將所述多個疊層封裝結構從所述條帶載體分離。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100：第一封裝 101：經包封半導體裝置 105：經重構晶圓 110：半導體裝置/裝置晶粒 120：包封材料 130：導電柱 140：重佈線結構/第一重佈線結構 142：重佈線路 143：介電層 144：凸塊下金屬層
160‧‧‧圖案化介電層
165‧‧‧焊料
170‧‧‧重佈線結構/第二重佈線結構
180’‧‧‧經變形導電凸塊
200‧‧‧第二封裝
210‧‧‧電性端子
400‧‧‧條帶載體
410‧‧‧框架結構

Claims (10)

  1. 一種疊層封裝結構的製造方法，包括：在一條帶載體上提供一第一封裝，其中所述第一封裝包括一經包封半導體裝置、設置在所述經包封半導體裝置的一第一側上的一第一重佈線結構及設置在所述第一重佈線結構上且貼合到所述條帶載體的多個導電凸塊；以及通過多個電性端子利用熱壓合製程將一第二封裝設置在所述第一封裝上，所述熱壓合製程使所述多個導電凸塊變形成多個經變形導電凸塊，其中所述多個經變形導電凸塊中的每一者包括連接所述第一重佈線結構的一基底部分及連接所述基底部分的一頂端部分，且所述基底部分的一曲率小於所述頂端部分的一曲率。
  2. 如申請專利範圍第1項所述的疊層封裝結構的製造方法，其中所述頂端部分的一最大直徑實質上小於所述基底部分的一最大直徑或是所述頂端部分的一最大直徑對所述基底部分的一最大直徑的一比率實質上介於50%到90%之間。
  3. 如申請專利範圍第1項所述的疊層封裝結構的製造方法，其中所述條帶載體的一厚度大於所述經變形導電凸塊中的每一者的一高度的20%，且小於所述經變形導電凸塊中的每一者的所述高度的80%。
  4. 如申請專利範圍第1項所述的疊層封裝結構的製造方法，其中所述經包封半導體裝置設置在一第二重佈線結構上，且 所述第二重佈線結構位於所述經包封半導體裝置的與所述第一側相對的一第二側上。
  5. 一種疊層封裝結構的製造方法，包括：在一條帶載體上提供一第一封裝，其中所述第一封裝包括一經重構晶片及設置在所述經重構晶片的一第一側上且貼合到所述條帶載體的多個導電凸塊，且所述經重構晶片包括由一包封材料所包封的多個半導體裝置；以及通過多個電性端子利用熱壓合製程將多個第二封裝設置在所述經重構晶片的一第二側上，所述熱壓合製程使所述導電凸塊變形成多個經變形導電凸塊，其中所述經變形導電凸塊中的每一者包括連接所述經重構晶片的一基底部分及連接所述基底部分的一頂端部分，且所述基底部分的一曲率小於所述頂端部分的一曲率。
  6. 如申請專利範圍第5項所述的疊層封裝結構的製造方法，其中所述頂端部分的一最大直徑實質上小於所述基底部分的一最大直徑或是所述頂端部分的一最大直徑對所述基底部分的一最大直徑的一比率實質上介於50%到90%之間。
  7. 如申請專利範圍第5項所述的疊層封裝結構的製造方法，其中所述條帶載體的一楊氏模量小於10Mpa。
  8. 如申請專利範圍第5項所述的疊層封裝結構的製造方法，其中由所述包封材料所包封的所述半導體裝置設置在一第二 重佈線結構上，且所述第二重佈線結構位於由所述包封材料所包封的所述半導體裝置的與所述第一側相對的一第二側上。
  9. 一種疊層封裝結構的製造方法，包括：在一載體基板上形成一第一封裝，其中所述第一封裝包括一經重構晶片及設置在所述經重構晶片的一第一側上的多個導電凸塊，且所述經重構晶片包括由一包封材料包封的多個半導體裝置；將具有所述載體基板的所述第一封裝設置在一條帶載體上；將所述載體基板從所述條帶載體上的所述第一封裝剝離；通過熱壓合製程在所述經重構晶片的一第二側上設置多個第二封裝以形成一晶片上封裝結構，所述熱壓合製程通過將所述導電凸塊壓抵所述條帶載體而使所述導電凸塊變形成多個經變形導電凸塊，其中所述經變形導電凸塊中的每一者包括一基底部分及一頂端部分，且所述基底部分的一曲率不同於所述頂端部分的一曲率；以及對所述條帶載體上的所述晶片上封裝結構執行一單體化製程以形成多個疊層封裝結構。
  10. 如申請專利範圍第9項所述的疊層封裝結構的製造方法，所述單體化製程更包括：對所述條帶載體上的所述經重構晶片進行切割以形成所述多個疊層封裝結構。
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