CN101315924A - 一种半导体封装体 - Google Patents

一种半导体封装体 Download PDF

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Publication number
CN101315924A
CN101315924A CNA2007101659995A CN200710165999A CN101315924A CN 101315924 A CN101315924 A CN 101315924A CN A2007101659995 A CNA2007101659995 A CN A2007101659995A CN 200710165999 A CN200710165999 A CN 200710165999A CN 101315924 A CN101315924 A CN 101315924A
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China
Prior art keywords
crystal grain
package body
semiconductor package
distribution
body according
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Granted
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CNA2007101659995A
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CN100592511C (zh
Inventor
陈承先
卿恺明
陈志华
郭正铮
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Advanced Manufacturing Innovation Co
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN101315924A publication Critical patent/CN101315924A/zh
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Abstract

本发明涉及一种半导体封装体，至少包含多颗晶粒(die)整合在同一个堆栈型结构中，其中在底下或中间的晶粒中形成多个穿透硅通道(through－siliconvia)，其电性连接至上方的晶粒，底下的晶粒面朝上方的一面有一组再配线(redistribution lines)，再配线底下的半导体结构，由再配线电性连接至穿透硅通道。在上方的晶粒的多个接合垫(contact pad)可面向或背向底下的晶粒。堆栈型晶粒由焊线(wire bond)或锡球(solder ball)电性连接至再配线，此外，在底下的晶粒面朝下方的一面，可具有另一组在配线，使引脚(pin－out)配置多样化。

Description

一种半导体封装体
技术领域
本发明是有关于集成电路(integrated circuit；IC)，且特别是有关于一种多晶粒晶片级封装(Multi-Die Wafer Level Packaging)的技术。
背景技术
从集成电路发明以来，半导体工业蓬勃发展。主要的原因在于电子组件(例如：晶体管、二极管、电阻器、电容器、…等)的尺寸愈来愈小，提高集成电路的密度，使得集成电路每单位面积，可容纳更多的电子组件。
上述的集成电路本质上属于二维集成电路，也就是说在晶片平面上形成集成电路。虽然微影技术的进步，使得二维集成电路的工艺有相当多的改进，不过在二维集成电路中，电子组件的最小尺寸仍受到二维平面的限制。当芯片必须容纳更多组件时，则需要更复杂的电路设计。
另一个组件尺寸的限制，在于组件的数量增加时，组件之间的互连数目增加及互连长度(length of interconnection)增长，造成电阻电容延迟(RC delay)与功率损耗增加。
为了提高集成电路的密度，三维集成电路的研究应运而生。典型的三维集成电路工艺中，两颗晶粒彼此接合，每颗晶粒与基板上的接合垫(contact pad)之间产生电性连接。举例来说，两颗晶粒彼此接合，然后该堆栈晶粒(stackeddies)接合基板，且每颗晶粒上的接合垫经由焊线电性连接至该基板上的接合垫。
一般的封装技术是先把晶片切割成晶粒，再进行封装，而晶片级封装技术可先执行后段工艺(back-end-of-line processing)，再切割晶片。晶片级封装可包含：形成接触构造、密封或晶背保护(back-side protection)、研磨以及晶片级相关技术。晶片级封装的好处是可降低成本，并产生较薄的封装体。
不幸的是，晶片级封装技术的发展，大多与单一晶粒有关且是关于前端锡球配置(front-side ball solder ball mounts)。当系统整合型封装结构(a system in apackage configuration)将多颗晶粒整合在同一封装体之内，需要分离的基板，如此会增加封装体积和封装厚度，还会提高电阻电容延迟。
因此，对于堆栈型晶粒而言，需要晶片级封装。
发明内容
本发明的所要解决的技术问题在于提供一种多晶粒晶片级封装，用以解决多晶粒晶片级封装的问题。
为了实现上述目的，本发明提供一半导体封装体，包含两颗晶粒，其中第一晶粒的第一基板具有第一组再配线(redistribution lines)电性连接至一个或多个半导体组件，其中半导体组件在第一晶粒的第一表面上；第一晶粒也具有导电通道穿过第一晶粒电性连接至再配线。第二晶粒连接至于第一晶粒，第一晶粒的第一表面面对第二晶粒。接合垫位于第二晶粒上，用以电性连接至再配线，其中接合垫可为焊线或锡球。此外，第一晶粒具有第二组再配线位于第一表面的反面，其中第二组再配线电性连接至各个导电通道。
为了实现上述目的，本发明还提供一半导体封装体，包含第一晶粒与第二晶粒，其中第一晶粒与第二晶粒都具有一组件面与一底面，第二晶粒与第一晶粒接合，第一晶粒的组件面面对第二晶粒。第一组再配线介于在第一晶粒与第二晶粒之间，并电性连接至穿过第一晶粒的导电通道。第二晶粒上的接触垫电性连接导电组件，借以连接至第一组再配线的各个线路，其中导电组件可为焊线或锡球。在第一晶粒的第一组再配线的反面形成第二组再配线，其中第二组再配线电性连接至各个导电通道。
为了实现上述目的，本发明还提供一半导体封装体包含：第一晶粒具有第一基板，其中第一基板的第一表面上形成半导体结构；在第二表面上形成保护层(protective layer)，其中第二表面在第一表面的反面；穿透硅通道穿过第一基板与保护层；在第一面上形成第一再配线，半导体结构由第一再配线电性连接至穿透硅通道；在接合垫上堆放第二晶粒，其中接合垫在第一晶粒上下两面的其中一面，且第二晶粒由焊线或锡球电性连接至第一再配线。此外，在第一晶粒的第一再配线的反面形成第二再配线，其中第二再配线电性连接至各个穿透硅通道。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图说明
为让本发明的上述和其它目的、特征、优点与实施例能明显易懂，所附图式的详细说明如下：
图1～6是依照本发明一实施例的一种堆栈型封装体的制造流程图；
图7是依照本发明另一实施例的一种堆栈型封装体的结构图；
图8～10是依照本发明一实施例的一种堆栈型封装体的制造流程图；
图11是依照本发明另一实施例的一种堆栈型封装的结构图；以及
图12～13是依照本发明实施例的引脚配置的平面图。
【主要组件符号说明】
100：晶片          110：半导体基板
112：电路          114：穿透硅通道
116：再配线        118：接触插塞
120：内层介电层    122：钝化层
200：晶片          210：运送晶片
310：保护层        510：第二晶粒
512：接合垫        514：锡球
516：底部填胶材料  610：绿漆
612：第二锡球      710：焊线
810：背面再配线    812：绿漆
1010：锡球         1110：焊线
具体实施方式
以下将以图式及详细说明清楚说明本发明的精神，任何所属技术领域的普通技术人员在了解本发明的实施例后，当可由本发明所揭示的技术，加以改变及修饰，其并不脱离本发明的精神与范围。
以下为本发明的附图及各种实施例，附图中相同的号码代表相同的组件。
请参照图1，晶片100的第一晶粒包含：具有电路112的半导体基板110，其中半导体基板110例如可为掺杂的或未掺杂的块状硅，或可为绝缘层上覆半导体(semiconductor-on-insulator，SOI)基板上的主动层(active layer)。一般而言，绝缘层上覆半导体包含在绝缘层上形成一层半导体材料，其中半导体材料可为硅，绝缘层可为埋入氧化(BOX)层或氧化硅层。在基板上具有绝缘层，其中典型的基板为硅基板或玻璃基板，也可为多层基板或倾斜基板
为了配合实际上的应用，在半导体基板110上形成的电路112可为任何形式电路。依照本发明一实施例，电路包含：在基板上形成电子组件，且一层或多层介电层覆盖电子组件；在多层介电层之间形成金属层，用以传递电子组件之间的信号；在一层或多层介电层内可形成电子组件。
举例来说，电路112可包含NMOS组件、PMOS组件、晶体管、电容器、电阻器、二极管、光侦测二极管、保险丝以及其它相关组件，将上述组件做适当连接，用以执行一种或数种功能，这些功能可包含：存储、程序处理、传感器、放大器、功率分配、输入、输出以及其它相关功能。上述仅为本发明一实施例，并非用以限定本发明，在不脱离本发明的精神和范围内，任何熟悉本技术的人员，当可视实际应用，对电路做各种的更动与润饰。
请参照图1，电路112由接触插塞(contact plugs)118与再配线116电性连接至穿透硅通道114。其中再配线116可用一般制造方法制成，作为集成电路的互连。举例来说，依照本发明一实施例，再配线116可先形成一层铜，接着在该层铜上形成一层镍，其制造步骤是经由溅镀、化学气相沉积、电镀、图案化电镀层，或是无电镀(electroless plating)，接着蚀刻多余的金属，最后形成再配线116。再配线116也可用其它材料制成，像是铝、钨、钛及其任意阻合所组成的族群，或相似材料。在本实施例中，再配线116的厚度在约0.5微米到约30微米之间。再配线116可选择其它材料与其它制造方法，其中其它制造方法可为金属镶嵌法。
穿透硅通道114可通过适合的制造方法制成，举例来说，依照本发明一实施例，先形成电路112，然后再形成穿透硅通道114。依照本发明一实施例，开孔(opening)穿过内层介电层120与部分的半导体基板110。举例来说，形成开孔的方法可为单一或多个蚀刻程序，例如研磨、激光或其它相关技术；开孔内形成扩散阻障(diffusion barrier)层、粘着层、绝缘层或相关物质，并且在开孔内填充导电材料，其中扩散阻障层(图中未标示)最好由一层或数层材料所组成，这些材料包含：氮化钽、钽、氮化钛、钛、钨化钴或相关化合物，而导电材料包含：铜、钨、铝、银及其任意组合所组成的族群，或其它相似材料，最后，形成穿透硅通道114。在本实施例中，穿透硅通道114内形成扩散阻障层，其中扩散阻障层的材料为氮化钽；用电化学电镀法在穿透硅通道114内填充铜。补充一点，先沉积晶种层，再进行电化学电镀，以利于填充导电材料。
依照本发明另一实施例，先形成穿透硅通道114，然后再形成电路112。依照此实施例，先形成穿透硅通道114，接下来填充介电质材料，然后研磨晶粒的底部，经过蚀刻之后，移除介电质材料，并由导电材料取代原来的介电质材料。上述仅为本发明一实施例，并非用以限定本发明，在不脱离本发明的精神和范围内，任何熟悉本技术的人员，当可视实际应用，选择其它材料与其它制造方法。
钝化层122最好覆盖于再配线116上，且钝化层122最好包含耐高温电阻材料，附带一提，图1所示的钝化层122只有一层，但实际上可包含多层材料。可形成钝化层122的材料包含：聚亚酰胺、苯环丁烯(BCB)、旋涂式玻璃(SOG)、多氧化硅(SiOx)、多氮化硅(SiNx)、多氮氧化硅(SiONx)、其它无机材料、其它硅相似材料、其它耐高温聚合物及相似物质。
请参照图2，依照本发明一实施例，为贴附一运送晶片210后的晶片100示图。接下来的工艺中，运送晶片210是个临时工具，用来支撑晶片100。用此方法保护半导体基板，或降低半导体基板的损害。
运送晶片210可包含：玻璃、氧化硅、氧化铝及相关物质。依照本发明一实施例，用胶粘剂把运送晶片210接着在钝化层(passivation layer)122的一上平面，其中胶粘剂可为任意适合的胶粘剂，像是紫外光胶(ultraviolet glue)，其经由紫外光照射后即可完全干燥固化，达到粘着效果。运送晶片210较佳的厚度最好大于约12密耳。
请参照图2，依照本发明一较佳实施例，通过平坦化工艺与蚀刻工艺，使穿透硅通道114露出。首先，执行平坦化工艺，像是研磨或化学机械研磨(CMP)，穿透硅通道114开始露出。然后，执行蚀刻工艺，除去部分半导体基板110，使得穿透硅通道114从半导体基板110底部伸出，如图2所示。在本实施例中，穿透硅通道114由铜制成。执行干蚀刻工艺，除去部分的半导体基板110，其中干蚀刻用氢溴酸/氧气、氢溴酸/氯气/氧气、六氟化硫/氯气、六氟化硫所组成的等离子体或其它等离子体。穿透硅通道114露出的部分最好是大约5微米至大约30微米。
请参照图3，其示出依照本发明一实施例，用来表示晶片100中形成保护层310。依照本发明一较佳实施例，保护层310可为环氧树脂(epoxy)、凝胶、硅胶(silicon rubber)或其它相似物质，并通过旋转涂布技术或喷墨印刷技术制成。
保护层310最好具有足够的厚度，以包覆露出的穿透硅通道114，在本实施例中，执行平坦化制程，像是研磨或化学机械研磨，用以形成平坦表面以及露出穿透硅通道114的端点，如图3所示。
请参照图4，其示出依照本发明一实施例，用来表示晶片100中移除运送晶片210。依照本发明一实施例，先前所述中，用紫外光胶把晶片100粘着于运送晶片210，其中紫外光胶，经由紫外光照射后即可完全干燥固化，使运送晶片210达到粘着效果。上述仅为本发明一实施例，并非用以限定本发明，在不脱离本发明的精神和范围内，任何熟悉本技术的人员，当可视实际应用，选择其它粘着技术，像是热熔胶、溶剂/等离子去除剂(solvent/plasma stripper)、激光或其它相关技术。
请参照图5，其示出依照本发明一实施例，用来表示晶片100与第二晶粒510连接，附带一提，图5所示的第二晶粒510比第一晶粒小，但实际上第二晶粒510可比第一晶粒小，第二晶粒510也可以比第一晶粒大，或是第二晶粒510与第一晶粒大小相同。
第二晶粒510电性连接至第一晶粒，最好采用倒装晶片(flip-chip)结构，意即接合垫512面向第一晶粒的配置方式。接合垫512经由锡球514电性连接至再配线116，其中锡球514可包含：高铅焊锡(high-lead)、共熔锡铅、无铅焊锡(lead free solder)、铜凸块(Cu bump)、铜/锡或其它相似材料。
在第二晶粒510与钝化层122之间，注入或用其它方式填充选择的底部填胶(underfill)材料516，底部填胶材料516可包含环氧树脂，填充至第二晶粒510与钝化层122之间；然后进行固化。用底部填胶材料516填充，避免因热应力而造成锡球514断裂。
变形胶(deformable gel)或硅胶也可以填充至第二晶粒510与钝化层122之间，防止锡球514断裂。在第二晶粒510与钝化层122之间，注入或用其它方式填充变形胶或硅胶，用以分担应力。
上述是使用倒装晶片封装结构，当然，其它封装结构也可运用于本发明中。请参照图7，举例来说，第二晶粒的接合垫由焊线电性连接至再配线，其中第二晶粒有接合垫的一面朝上。
请参照图6，其示出依照本发明一实施例，用来表示绿漆(solder mask)610与第二锡球612。首先，通过沉积法形成绿漆610，接着图案化绿漆材料，然后露出穿透硅通道114。锡球514可包含：高铅焊锡、共熔锡铅、无铅焊锡、铜凸块、铜/锡或其它相材料。形成绿漆与锡球的方式是现有技术，这边就不再赘述了。
熟悉该项技术的人员也可了解到第二锡球612可以其它方法来加以形成。举例来说，在保护层310上沉积凸点下金属化层(under-bump metallization；UBM)，然后于其中形成第二锡球612，形成第二锡球612的步骤包含：蒸发、电镀、转印、喷射、金柱植球(stud bumping)、直接定位，或相关步骤。再者，直接在穿透硅通道114上形成第二锡球612。
附带一提，再配线116可包含多条金属线，电性连接第一半导体晶粒的半导体结构，至穿透硅信道114以及第二锡球612，其中半导体结构如电路112；或是电性连接第二半导体晶粒510的半导体结构(图中未标示)至穿透硅通道114和第二锡球61，其中半导体结构如电路112。总之，相同的再配线用以在第一晶粒的半导体结构与在第二晶粒510的半导体结构间产生电性连接。
接着，执行其它的后段工艺，作为特殊应用，举例来说，执行单一组件化(singulation)工艺，从晶片中切割出每一颗堆栈型晶粒封装体或其它封装体。
先前所述的实施例中，第二晶粒510由锡球514电性连接至第一晶粒。除了运用锡球之外，也可用其它技术达到相同的目的，举例来说，请参照图7，第二晶粒510由焊线710电性连接至第一晶粒，其中使用焊线710为一现有技术。此实施例中，第二晶粒510与第一晶粒连接，在第二晶粒510上，接合垫512的位置背向第一晶粒，如图7所示。多条焊线710接合至第一晶粒，且该些接合垫512经由这些焊线710分别电性连接至相对应的再配线116。
请参照图8～10，其示出依照本发明实施例使用双面再配线(double-sidedredistribution lines)，使得引脚(Pin-out)的配置具有更大的弹性。请参照图8，晶片200的制造过程与图1～3表示的制造过程类似，图中相同的号码代表相同的组件。
依照本发明实施例，图8的晶片200好比图3的晶片100形成后，接着形成背面再配线810以及形成绿漆812。形成背面再配线810的方法与图1中形成再配线116的方法相同，形成绿漆812的方法与图6中形成绿漆的方法相同。
请参照图9，其示出依照本发明一实施例，通过如图5所示的锡球514与底部填胶材料516，使第二晶粒510连接至晶片200。请参照图10，其示出依照本发明一实施例，形成锡球1010。
本实施例提供别的方法，使第二晶粒510的接合垫512电性连接至第一再配线116，举例来说，请参照图11，其示出依照本发明一实施例，其为一现有技术，第二晶粒510由焊线1110电性连接至第一晶粒。本实施例中，第二晶粒510与第一晶粒连接，第二晶粒510上接合垫512的位置，如图11所示。多条焊线1110接合至第一晶粒，且这些接合垫512由这些焊线1110分别电性连接至相对应的再配线116。
比照图1～7与图8～11，在图8～11的实施例中，引脚(Pin-out)的配置具有较大的弹性。请参照图1～7，穿透硅通道所在的位置限制锡球所在的位置，意即限制引脚所在的位置，依此，在晶片上需更加小心配置电路，以让穿透硅通道的位置在锡球所要求的位置上。请参照图8～11，在晶片上设计电路，可做引脚的配置，换句话说，如有设计上的需要，设计者可重新分配背面再配线的线路。
举例来说，请参照图12，其示出图1～7实施例中引脚的配置图，引脚的配置对应穿透硅通道所在的位置，引脚仅在晶粒的环绕周边。请参照图13，其示出图8～10实施例中引脚的配置图，提供更多的引脚，并提供多元化的引脚配置方式。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变型，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims (20)

1、一种半导体封装体，其特征在于，至少包含：
一第一晶粒有一第一表面且一第二表面在该第一表面的反面；
多个通道穿过该第一晶粒；
一第一组再配线电性连接该第一晶粒的半导体部分至所述通道；以及
一第二晶粒有一第一表面且一第二表面在该第一表面的反面，其中该第二晶粒的该第一表面有多个接合垫，该第二晶粒的所述接合垫由该第一组再配线电性连接至所述通道。
2、根据权利要求1所述的半导体封装体，其特征在于，该第二晶粒的所述接合垫背向该第一晶粒。
3、根据权利要求2所述的半导体封装体，其特征在于，该第二晶粒的所述接合垫由多个焊线电性连接至该第一组再配线。
4、根据权利要求1所述的半导体封装体，其特征在于，该第二晶粒的所述接合垫面向该第一晶粒。
5、根据权利要求4所述的半导体封装体，其特征在于，该第二晶粒的所述接合垫由多个锡球电性连接至该第一组再配线。
6、根据权利要求1所述的半导体封装体，其特征在于，还包含：一第二组再配线于该第一晶粒的该第二表面上，该第一晶粒的该第二表面在该第一组再配线的反面，每一该第二组再配线电性连接至相对应的所述通道。
7、根据权利要求1所述的半导体封装体，其特征在于，还包含：一环氧层于该第一晶粒的该第二表面上，该通道穿过该环氧层。
8、一种半导体封装体，其特征在于，至少包含：
一第一晶粒与一第二晶粒，该第一晶粒与该第二晶粒均有一组件面与一底面，该第一晶粒的该组件面面向该第二晶粒；
多个通道由该组件面至该底面穿过该第一晶粒；
一第一组再配线介于该第一晶粒与该第二晶粒之间，该第一组再配线电性连接至相对应的所述通道；以及
多个导体电性连接该第二晶粒的该组件面上的接触垫至相对应的该第一组再配线。
9、根据权利要求8所述的半导体封装体，其特征在于，该第二晶粒的该组件面面向该第一晶粒，且所述导体包含多个锡球。
10、根据权利要求8所述的半导体封装体，其特征在于，该第二晶粒的该底面面向该第一晶粒，且所述导体包含多个焊线。
11、根据权利要求8所述的半导体封装体，其特征在于，还包含：一第二组再配线于该第一晶粒的该底面上，该第二组再配线电性连接至相对应的通道。
12、根据权利要求8所述的半导体封装体，其特征在于，还包含：一环氧层形成于该第一晶粒的该底面，所述通道穿过该环氧层。
13、一种半导体封装体，其特征在于，至少包含：
一第一晶粒有一第一基板与多个半导体结构，所述半导体结构形成于该第一基板的一第一表面上；
一保护层形成于该第一基板的一第二表面上，该第二表面在该第一表面的反面；
多个穿透硅通道，穿过该第一基板与该保护层；以及
多个第一再配线电性连接所选择的所述半导体结构至相对应的所述穿透硅通道。
14、根据权利要求13所述的半导体封装体，其特征在于，还包含：一第二晶粒具有多个半导体结构形成于一第二基板的一第一表面上，该第二晶粒接合至该第一晶粒，该第一晶粒的该第一基板的该第一表面面向该第二晶粒。
15、根据权利要求14所述的半导体封装体，其特征在于，该第二基板的该第一表面面向该第一晶粒。
16、根据权利要求15所述的半导体封装体，其特征在于，该第二晶粒的多个接合垫由多个锡球电性连接至所述第一再配线。
17、根据权利要求14所述的半导体封装体，其特征在于，该第二基板的该第一表面背向该第一晶粒。
18、根据权利要求17所述的半导体封装体，其特征在于，该第二晶粒的多个接合垫由多个焊线电性连接至该些第一再配线。
19、根据权利要求14所述的半导体封装体，其特征在于，还包含：多个第二再配线于一保护层上，所述第二再配线电性连接至相对应的所述穿透硅通道。
20、根据权利要求14所述的半导体封装体，其特征在于，该第一晶粒为一晶片中的一晶粒。
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