KR101121320B1 - 구리 기둥을 갖는 웨이퍼 후면 구조 - Google Patents

구리 기둥을 갖는 웨이퍼 후면 구조 Download PDF

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KR101121320B1
KR101121320B1 KR1020100037554A KR20100037554A KR101121320B1 KR 101121320 B1 KR101121320 B1 KR 101121320B1 KR 1020100037554 A KR1020100037554 A KR 1020100037554A KR 20100037554 A KR20100037554 A KR 20100037554A KR 101121320 B1 KR101121320 B1 KR 101121320B1
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South Korea
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rdl
substrate
layer
copper pillar
opening
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KR1020100037554A
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KR20100119507A (ko
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첸-화 유
혼-린 황
큐오-칭 수
첸-시엔 첸
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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Abstract

집적 회로 구조는, 전면 및 후면을 갖는 반도체 기판, 및 상기 반도체 기판을 관통하는 기판-관통 비아(via)를 포함한다. 상기 기판-관통 비아는 상기 반도체 기판의 후면으로 연장된 후단을 포함한다. 재분배 라인(RDL: redistribution line)은 상기 반도체 기판의 후면 상에 배치되어 상기 기판-관통 비아의 후단에 전기적으로 연결된다. 패시베이션 층은 상기 RDL 위에 배치되며 그 내부에 개구를 구비하며, 상기 RDL의 일부분은 상기 개구를 통해 노출된다. 구리 기둥(copper pillar)은 상기 개구 내에 그 일부분이 있으며 상기 RDL에 전기적으로 연결된다.

Description

구리 기둥을 갖는 웨이퍼 후면 구조 {Wafer Backside Structures Having Copper Pillars}
본 발명은 일반적으로 집적 회로 구조들(integrated circuit structures)에 관한 것으로서, 보다 특정적으로는 관통-실리콘 비아들(through-silicon vias), 및 상기 관통-실리콘 비아들에 연결된 결합 패드들(bond pads)의 형성에 관한 것이다.
집적 회로가 발명된 이래로, 다양한 전자 부품들(즉, 트랜지스터, 다이오드, 저항, 커패시터, 등)의 집적도의 꾸준한 향상으로 인해 반도체 산업은 계속적인 고속 성장을 겪어 왔다. 대체적으로, 이러한 집적도 향상은 최소 피처(feature) 크기의 꾸준한 감소에서 비롯되었으며, 그러한 크기의 감소는 주어진 칩 영역 내에 보다 많은 부품들의 집적을 가능케 한다.
이러한 집적 개선은 본질적으로 원래 2차원적(2D)으로서, 집적 부품들이 차지하는 공간은 본질적으로 반도체 웨이퍼의 표면 상에 있다. 비록 리소그래피(lithography)의 극적인 개선으로 인해 2D 집적 회로 형성이 상당히 개선되었으나, 2차원에서 달성 가능한 밀도에는 물리적인 제약들이 있다. 이러한 제약들 중 하나는 상기 부품들을 제조하는데 요구되는 최소 크기이다. 또한, 보다 많은 장치들이 하나의 칩 상에 배치될 경우, 보다 복잡한 설계가 요구된다.
추가적인 제약은 장치 개수가 증가함에 따라 장치들 사이의 상호연결부(interconnection)들의 개수 및 길이가 상당히 증가하는 것에서 비롯된다. 상호연결부들의 개수 및 길이가 증가할 경우, 회로 RC 지연(circuit RC delay) 및 전력 소비가 증가한다.
전술한 제약들을 해결하기 위한 노력들 중에서, 3차원 집적 회로(3DIC: three-dimensional integrated circuit) 및 적층 다이들(stacked dies)이 흔히 사용된다. 따라서 3DIC 및 적층 다이들에서는 관통-실리콘 비아들(TSVs: through-silicon vias)이 사용된다. 이러한 경우, TSV들은 다이 상의 집적 회로를 그 다이의 후면(backside)에 연결하기 위해 종종 사용된다. 또한 TSV들은 다이의 후면을 통하여 집적 회로들을 접지(ground)시키기 위한 짧은 접지 경로(short grounding path)들을 제공하기 위해 또한 사용되며, 상기 다이의 후면은 접지된 금속성 필름에 의해 덮여질 수 있다.
도 1은 칩(104)에 형성된 통상의 TSV(102)를 도시한다. TSV(102)는 실리콘 기판(106) 내에 있다. 금속배선 층들(metallization layers) 내의 상호연결부들(금속선들(metal lines) 및 비아들(vias), 미도시됨)을 통하여, TSV(102)는 결합 패드(108: bond pad)에 전기적으로 연결되며, 상기 결합 패드는 칩(104)의 전면에 있다. TSV(102)는 구리 포스트(copper post)의 형상으로 실리콘 기판(106)의 후면을 통해 노출된다. 칩(104)이 다른 칩에 결합될 경우, TSV(102)는 다른 칩 상의 결합 패드에 결합되며, 그것들 간에는 땜납(solder)이 있을 수도 있고 없을 수도 있다.
통상의 후면 TSV 연결(backside TSV connection)은 단점들로 인한 고충이 있다. TSV 결합은 TSV들 사이에 비교적 큰 피치(pitch)를 요구하기 때문에, TSV들의 배치가 제한적이며, TSV들 사이의 거리는 예로써 땜납 볼들(solder balls)을 위한 공간을 허용하도록 충분히 클 필요가 있다. 따라서 새로운 후면 구조들(backside structures)이 요구된다.
본 발명의 일 관점에 따르면, 집적 회로 구조는, 전면 및 후면을 갖는 반도체 기판, 및 상기 반도체 기판을 관통하는 기판-관통 비아(via)를 포함한다. 상기 기판-관통 비아는 상기 반도체 기판의 후면으로 연장된 후단을 포함한다. 재분배 라인(RDL: redistribution line)은 상기 반도체 기판의 후면 상에 배치되어 상기 기판-관통 비아의 후단에 전기적으로 연결된다. 패시베이션 층은 상기 RDL 위에 배치되며 그 내부에 개구를 구비하며, 상기 RDL의 일부분은 상기 개구를 통해 노출된다. 구리 기둥(copper pillar)은 상기 개구 내에 그 일부분이 있으며 상기 RDL에 전기적으로 연결된다.
다른 실시예들이 또한 개시된다.
본 발명의 유리한 특징들은 적층 다이들(stacked dies) 간의 개선된 결합성(bondability) 및 증가된 이격(standoff)을 포함한다.
본 발명 및 그것의 이점들에 대한 보다 완전한 이해를 위해, 이하에서는 첨부된 도면들과 연계한 이하의 설명들이 참조된다.
도 1은 관통-실리콘 비아(TSV)를 포함하는 통상의 집적 회로 구조를 도시하며, 여기서 TSV는 기판의 후면을 통해 돌출되어 있고, 구리 포스트(copper post)의 형상으로 다른 칩의 결합 패드에 결합되어 있다.
도 2 내지 11은 일 실시예에 따른 상호연결 구조의 제조에서 중간 단계들에 대한 평면도들 및 단면도들이다.
도 12 및 13은 다른 실시예에 따른 상호연결 구조 제조에서 중간 단계들에 대한 평면도들 및 단면도들이다.
이하에서는 본 발명의 실시예들에 대한 제조 및 사용이 설명된다. 하지만, 그 실시예들은 폭넓은 특정 항목들로 구체화될 수 있는 많은 응용 가능한 발명적 개념들을 제공함을 이해해야 할 것이다. 설명되는 특정 실시예들은 단지 본 발명을 제조하고 사용하는 특정 방법들에 대한 예시적인 것에 불과하며 본 발명의 범위를 제한하는 것은 아니다.
관통-실리콘 비아들(TSVs)에 연결된 신규한 후면 연결 구조 및 그것의 형성 방법이 제공된다. 본 발명의 일 실시예에 따른 제조의 중간 단계들이 예시된다. 다양한 실시예들이 논의된다. 본 발명의 다양한 관점들 및 예시적 실시예들에서, 동일 부재들을 가리키기 위해 동일한 참조 번호들이 사용된다.
도 2를 참조하면, 기판(10) 및 내부의 집적 회로들(블럭 4에 의해 상징됨)을 포함하는 칩(2)이 제공된다. 일 실시예에서, 칩(2)은, 그 칩(2)과 똑같은 복수의 칩들을 포함하는 웨이퍼의 일부분이다. 기판(10)은 벌크 실리콘 기판(bulk silicon substrate)과 같은 반도체 기판일 수 있으며, 다만 그것은 Ⅲ족, Ⅳ족, 및/또는 Ⅴ족 원소들과 같은 다른 반도체 물질들을 포함할 수 있다. 기판(10)의 전면(도 2에서 위를 향하고 있는 표면)에 트랜지스터들(마찬가지로 블럭 4로 예시됨)과 같은 반도체 장치들이 형성될 수 있다. 기판(10) 상에는 금속 라인들 및 그 안에 형성된 비아들(미도시)을 포함하는 상호연결 구조(12: interconnect structure)가 형성되어 상기 반도체 장치들과 연결된다. 상기 금속 라인들 및 비아들은 구리 또는 구리 합금들로 형성될 수 있으며, 잘 알려진 다마신 공정(damascene process)들을 사용하여 형성될 수 있다. 상호연결 구조(12)는 일반적으로 알려진 중간층(ILD: inter-layer dielectric) 유전체 및 중간금속 유전체들(IMDs: inter-metal dielectrics)을 포함할 수 있다.
TSV(20)는 기판(10)에 형성되며, 후면(도 2에서 아래를 향하는 표면)으로부터 전면(표면 상에 활성 회로들이 형성된 표면)으로 연장된다. 제1 실시예에서는, 도 2에 도시된 바와 같이, TSV(20)는 비아-퍼스트(via-first) 방법을 사용하여 형성되며, 바닥의 금속배선 층(M1으로 표시됨)을 형성하기 이전에 형성된다. 따라서, TSV(20)는 활성 장치들을 커버하기 위해 사용되는 ILD 안으로만 연장되고, 상호연결 구조(12) 내의 IMD 층들 안으로는 연장되지 않는다. 대안적인 실시예들에서, TSV(20)는 비아-라스트(via-last) 방법을 사용하여 형성되며, 상호연결 구조(12)를 형성한 이후 형성된다. 따라서, TSV(20)는 기판(10) 및 상호연결 구조(12)를 모두 관통한다. TSV(20)의 측벽들 상에 고립층(22: isolation layer)이 형성되어 TSV(20)를 기판(10)으로부터 전기적으로 절연시킨다. 고립층(22)은 실리콘 나이트라이드(silicon nitride), 실리콘 옥사이드(silicon oxide)(예로써, TEOS(tetra-ethyl-ortho-silicate) 옥사이드), 등과 같이 일반적으로 사용되는 유전체 물질들로 형성될 수 있다.
도 3을 참조하면, 결합 패드(14)는 칩(2)의 전면(도 3에서 위로 바라보는 측면)에 형성되어 칩(2)의 전면 밖으로 돌출된다. 이후 칩(2)(및 대응하는 웨이퍼)은 접착제(18)를 통해 캐리어 웨이퍼(16: carrier wafer)에 장착된다. 도 4에서, 기판(10)의 과잉 영역을 제거하기 위해 후면 그라인딩(backside grinding)이 수행된다. 칩(2)의 후면에 화학-기계적 연마(CMP: chemical mechanical polish)가 수행됨으로써, TSV(20)가 노출된다. 기판(10)의 후면을 커버하기 위해 후면 고립층(24)이 형성된다. 예시적인 일 실시예에서, 후면 고립층(24)의 형성은 기판(10)의 후면을 다시 에칭하는 것, 후면 고립층(24)을 블랭킷 형성(blanket forming)하는 것, 그리고 TSV(20) 바로 위의 후면 고립층(24) 부분을 제거하기 위해 약한 화학-기계적 연마(CMP)를 수행하는 것을 포함한다. 따라서, 후면 고립층(24)의 개구를 통해 TSV(20)가 노출된다. 대안적인 실시예들에서, TSV(20)를 노출시키는 상기 후면 고립층(24)의 개구는 에칭에 의해 형성된다.
도 5를 참조하면, 후면 고립층(24) 및 TSV(20) 상에, UBM(under-bump metallurgy)으로도 지칭되는 박형 시드층(26: thin seed layer)이 블랭킷 형성된다. UBM(26)에 대한 가용 물질들은 구리 또는 구리 합금들을 포함한다. 하지만, 은, 금, 알루미늄, 및 그것들의 조합들과 같은 다른 금속들이 또한 포함될 수 있다. 일 실시예에서, UBM(26)은 스퍼터링(sputtering)을 사용하여 형성된다. 다른 실시예들에서, 전기 도금(electro plating)이 사용될 수 있다.
도 5는 마스크(46)의 형성을 또한 도시하고 있다. 일 실시예에서, 마스크(46)는 포토레지스트(photoresist)이다. 대안적으로, 마스크(46)는 건조 필름(dry film)으로 형성되며, 상기 건조 필름은 ABF(Ajinimoto buildup film)와 같은 유기 물질을 포함할 수 있다. 이후 마스크(46)는 마스크(46)에 개구(50)를 형성하기 위해 패터닝되며(patterned), 이때 TSV(20)는 상기 개구(50)를 통해 노출된다.
도 6에서, 상기 개구(50)는 그 개구(50)에 RDL(52: redistribution line)을 형성하는 금속성 물질로 선택적으로 충진된다. 바람직한 실시예에서, 상기 충진 물질은 구리 또는 구리 합금들을 포함하며, 다만 알루미늄, 은, 금, 또는 그것들의 조합들과 같은 다른 금속들이 또한 사용될 수 있다. 상기 형성 방법들은 전기-화학적 도금(ECP: electro-chemical plating), 무전해 도금(electroless plating), 또는 스퍼터링(sputtering), 프린팅(printing), 및 화학기상증착(CVD: chemical vapor deposition) 방법들 같은 다른 상용적 증착 방법들을 포함할 수 있다. 이후 마스크(46)는 제거된다. 결과적으로, 마스크(46) 하측의 UBM(26) 영역들이 노출된다.
도 7을 참조하면, UBM(26)의 노출 영역들은 플래쉬 에칭(flash etching)에 의해 제거된다. 잔존 RDL(52)은, TSV(20) 바로 위의 영역으로서 상기 TSV(20)에 연결된 영역을 포함하는 RDL 스트립(521)(재분배 트레이스(redistribution trace)로도 지칭됨)을 포함하며, RDL 스트립(521)과 결합된 RDL 패드(522)를 선택적으로 포함한다. RDL(52)의 평면도는 도 9에서 볼 수 있다. 도 7 및 후속 도면들에서, UBM(26)은 전형적으로 RDL(52)와 유사 물질들로 형성되기 때문에 보여지지지 않으며, 따라서 RDL(52)와 병합된 것으로 보인다. 플래쉬 에칭의 결과로서, RDL(52)의 얇은 층이 또한 제거된다. 하지만, RDL(52)의 제거 부분은 전체 두께와 비교하여 매우 작다.
다음으로, 도 8에 도시된 바와 같이, 개구(58)를 형성하기 위해 패시베이션 층(56: passivation layer)이 블랭킷 형성되고 패터닝된다. 패시베이션 층(56)은 나이트라이드(nitrides), 옥사이드(oxides), 폴리이미드(polyimide), 등으로 형성될 수 있다. 포토레지스트(60: photoresist)가 적용되고 현상되어 개구(58)의 패턴을 형성한다. 패시베이션 층(56)의 개구(58)를 통하여 RDL 패드(522)의 일부분이 노출된다. 개구(58)는 RDL 패드(522, 도 9 참조 바람)의 중앙부를 점유할 수 있다. RDL 스트립 영역(521)은 패시베이션 층(56)에 의해 덮여지도록 유지될 수 있다.
도 9는 패시베이션 개구(58)와 RDL(52)의 개략적인 평면도를 도시한다. 도시된 특징(feature)들의 치수들은 실제 비율이 아님을 유의할 필요가 있다. 바람직하게는, 개구(58)는 RDL 패드(522)보다 작은 크기를 가지며 그것의 중앙부를 노출시킨다. 예시적인 일 실시예에서, RDL 스트립(521)은 약 5 ㎛ 내지 약 15 ㎛ 사이의 폭(W1)을 갖는다. RDL 패드(522)는 약 80 ㎛ 내지 약 100 ㎛의 폭(W2)을 갖는 한편, 패시베이션 개구(58)는 약 70 ㎛ 내지 약 90 ㎛의 폭(W3)을 갖는다. 패시베이션 개구(58)의 평면 모습은 팔각형, 육각형, 정사각형, 또는 다른 적용 가능한 형상을 포함하는 어떤 다각형의 형상을 가질 수 있으되, 그에 제한되지는 않는다.
다음으로, 도 10에 도시된 바와 같이, 포토레지스트(60)가 제거되고, 포토레지스트(62)가 형성된다. 포토레지스트(62)는 바람직하게는 포토레지스트(60)보다 더 두껍다. 일 실시예에서, 포토레지스트(62)의 두께는 약 20 ㎛보다 더 크거나, 심지어 약 60 ㎛보다 더 크다. 포토레지스트(62)는 RDL 패드(522)가 노출되는 개구(마찬가지로 58로 지시됨)를 형성하도록 패터닝된다. 다음으로, 전기 도금에 의해 개구(58)로부터 구리 기둥(64: copper pillar)이 형성된다. 구리 기둥(64)은 구리 및/또는 은, 금, 텅스텐, 알루미늄, 및 그것들의 조합들과 같은 다른 금속들을 포함할 수 있다.
패시베이션 층(56, 도 8 참조)의 에칭에서 폴리머(polymer)가 생성 가능한 것으로 관찰되며, 개구(58) 내의 그 잔존 폴리머는 개구(58) 내에 어떤 니켈 층(nickel layer)의 형성에 영향을 끼칠 수 있다. 또한, 개구(58) 내에 형성된 어떤 금속 피처(metal feature)는 칩(2)의 회로에 전기적으로 연결될 수 있다. 개구(58) 내의 금속 피처를 형성하기 위해 무전해 도금(electroless plating)이 사용된다면, 개구(58) 내의 금속 피처에 연결된 회로 영역들의 전위가 영향받을 가능성이 있다. 하지만, 본 발명의 실시예들에서는, 이러한 문제들을 해결하기 위해 구리 기둥(64) 형성에 전기 도금(electro plating)이 사용된다.
전기 도금을 통해, 구리 기둥(64)은 신뢰성 있게 형성될 수 있으며, 양호한 품질을 갖게 된다. 또한, 전기 도금의 증착율은 높다. 따라서, 구리 기둥(64)은 무전해 도금을 사용하여 증착되는 금속 피처들보다 현저하게 더 큰 두께로 증착될 수 있다. 예시적인 일 실시예에서, 구리 기둥(64)의 높이(H)는 약 15 ㎛보다 더 크거나, 심지어 약 60 ㎛보다 더 크다. 다음으로, 베리어 층(66: barrier layer)이 예로써 무전해 도금에 의해 형성되며, 이때 베리어 층(66)은 니켈로 형성될 수 있다. 대안적으로, 베리어 층(66)은 바나듐(V), 크롬(Cr), 및 그것들의 조합들을 포함할 수 있다. 베리어 층(66)의 상측에 땜납(68)이 또한 형성될 수 있으며, 상기 땜납도 전기 도금을 사용하여 형성될 수 있다. 일 실시예에서, 땜납(68)은 주석-납(tin-lead: Sn-Pb) 합금으로 형성된 공융 땜납(eutectic solder)을 포함할 수 있다. 대안적인 실시예에서, Sn-Ag 또는 Sn-Ag-Cu 합금과 같은 무연 땜납(lead-free solder) 물질로 형성된다. 베리어 층(66) 및 땜납(68)은 구리 기둥(64)의 측벽들에 실질적으로 정렬된 측벽들을 갖는다. 또한, 베리어 층(66) 및 땜납(68)은 구리 기둥(64) 바로 위의 영역에 한정된다.
도 11을 참조하면, 포토레지스트(62)가 제거되며, 도 10에 도시된 바와 같은 구조가 칩(80)과 같은 다른 칩에 결합될 수 있다. 예시적인 일 실시예에서, 칩(80)은 그것의 전방 표면에 구리 포스트(86: copper post), 베리어 층(84), 및 땜납(82)를 구비할 수 있으며, 이때 땜납들(82, 86)이 리플로우되어(reflowed) 서로 결합될 수 있다.
도 12 및 13은 대안적인 일 실시예를 도시한다. 이 실시예의 초기 단계들은 도 2 내지 9에 도시된 것과 본질적으로 동일할 수 있다. 다음으로, 도 12를 참조하면, 구리 기둥(64)을 형성한 후 베리어 층(66)을 형성함 없이, 포토레지스트(62)가 제거된다. 다음으로, 도 13에 도시된 바와 같이, 메탈 피니쉬(90: metal finish)가 형성된다. 메탈 피니쉬(90)의 형성 방법들은 ECP, 무전해 도금, 등을 포함한다. 일 실시예에서, 메탈 피니쉬(90)는 구리 기둥(64) 바로 위에서 그 구리 기둥과 접촉하는 니켈 층(92)을 포함한다. 또한, 메탈 피니쉬(90)는 구리 기둥(64)의 상측을 덮으며 구리 기둥(64)의 측벽들과 접한다. 선택적으로, 추가적인 층들이 형성됨으로써, 메탈 피니쉬는 무전해 니켈 금도금(ENIG: electroless nickel immersion gold), 무전해 니켈 팔라듐 금도금(ENEPIG: electroless nickel electroless palladium immersion gold), 또는 니켈 팔라듐 층(nickel palladium layer)일 수 있다. 메탈 피니쉬(90)도 칩(80)의 땜납(82)과 결합될 수 있다.
본 발명의 실시예들은 여러 가지 유리한 특징들을 갖는다. 무전해 도금을 사용하는 것 대신 전기 도금을 사용하여 구리 기둥(64)을 형성함으로써, 증착율이 훨씬 높고, 따라서 구리 기둥(64)의 높이가 현저히 짧은 시간 내에 수십 마이크론(micron)에 도달할 수 있다. 따라서 칩들(2, 80)(도 11 및 13 참조) 간의 이격(standoff)이 증가될 수 있고, 그리하여 후속의 패키징(packing) 공정에서, 칩들(2, 80) 사이의 공간 내로 언더필(underfill)이 용이하게 유입될 수 있다.
본 발명 및 그것의 이점들이 상세하게 기술되었으나, 첨부된 청구항들에 의해 정의된 본 발명의 사상 및 범위를 벗어남 없이 여러 가지 수정들, 치환들 및 변경들이 가능함을 이해해야 할 것이다. 더욱이, 본 출원의 범위는 명세서에서 기술되어진 공정, 기계, 제조, 물질의 조합, 수단, 방법들 및 단계들에 관한 특정 실시예들에 제한되도록 하려는 것은 아니다. 해당 분야의 당업자는 본 발명이 개시하는 것으로부터, 현존하는 또는 이후 개발될, 앞서 기술된 대응하는 실시예들과 동일한 기능을 실질적으로 수행하거나 실질적으로 동일한 결과를 달성하는 공정, 기계, 제조, 물질의 조합, 수단들, 방법들, 또는 단계들이 본 발명에 따라 유용될 수 있음을 이해할 것이다. 따라서, 첨부된 청구항들은 그 범위 내에서 그와 같은 공정들, 기계들, 제조, 물질의 조합, 수단들, 방법들, 또는 단계들을 포함하도록 의도되어진다. 추가적으로, 각각의 청구항은 개별 실시예를 구성하며, 여러 청구항들 및 실시예들의 조합은 본 발명의 범위 이내이다.

Claims (8)

  1. 전면 및 후면을 포함하는 반도체 기판;
    상기 반도체 기판을 관통하는 기판-관통 비아(via)로서, 상기 반도체 기판의 후면까지 연장된 후단을 포함하는 기판-관통 비아;
    상기 반도체 기판의 후면 상에 있으며 상기 기판-관통 비아의 후단에 전기적으로 연결된 재분배 라인(RDL);
    상기 RDL 위에 있으며 내부에 개구를 구비한 패시베이션 층으로서, 상기 개구를 통해 상기 RDL의 일부분이 노출되는 패시베이션 층; 및
    일부분이 상기 개구 내에 있으며 상기 RDL에 전기적으로 연결된 구리 기둥(copper pillar);을 포함하는 집적 회로 구조.
  2. 제1항에 있어서,
    상기 RDL은,
    일부분이 상기 기판-관통 비아 바로 위에 있으며 상기 기판-관통 비아와 접촉하는 RDL 스트립; 및
    상기 RDL 스트립보다 더 큰 폭을 갖는 RDL 패드;를 포함하며,
    상기 구리 기둥은 상기 RDL 패드의 상면과 접촉하는 저면을 포함하는 것인 집적 회로 구조.
  3. 제1항에 있어서,
    상기 구리 기둥 바로 위에 있는 베리어 층; 및
    상기 베리어 층 바로 위에 있는 땜납 층;을 더 포함하며,
    상기 구리 기둥, 상기 베리어 층, 및 상기 땜납 층의 측벽들은 실질적으로 수직 정렬된 것인 집적 회로 구조.
  4. 제1항에 있어서,
    상기 구리 기둥의 상면 및 측벽상의 메탈 피니쉬(metal finish)를 더 포함하며,
    상기 메탈 피니쉬는 니켈, 금, 팔라듐, 및 그것들의 조합들을 본질적으로 포함하는 그룹으로부터 선택된 금속을 포함하는 것인 집적 회로 구조.
  5. 전면 및 후면을 포함하는 반도체 기판;
    상기 반도체 기판의 후면으로부터 상기 반도체 기판 내부로 연장된 기판-관통 비아로서, 상기 기판-관통 비아의 후단은 상기 반도체 기판의 후면을 통해 노출된 기판-관통 비아;
    상기 반도체 기판의 후면 위에 있으며 상기 기판-관통 비아의 후단에 연결된 재분배 라인(RDL)으로서, 상기 기판-관통 비아와 접촉하는 RDL 스트립, 및 상기 RDL 스트립보다 더 큰 폭을 가지며 상기 RDL 스트립과 결합된 RDL 패드를 포함하는 재분배 라인;
    상기 RDL 위에 있는 패시베이션 층;
    상기 배시베이션 층 내에 있는 개구로서, 상기 RDL 패드의 중앙부는 상기 개구를 통해 노출되며, 상기 RDL 패드의 가장자리 부분들은 상기 패시베이션 층에 의해 덮여지는 개구; 및
    상기 개구 내에 있으며 상기 RDL의 중앙부와 접촉하는 구리 기둥;을 포함하는 집적 회로 구조.
  6. 제5항에 있어서,
    상기 구리 기둥 위에 있으며 상기 구리 기둥과 접촉하는 니켈 층을 더 포함하는 것인 집적 회로 구조.
  7. 제6항에 있어서,
    상기 니켈 층 바로 위에 있는 땜납 층을 더 포함하며,
    상기 땜납 층 및 상기 니켈 층은 상기 구리 기둥 바로 위의 영역에 실질적으로 한정되는 것인 집적 회로 구조.
  8. 제6항에 있어서,
    상기 니켈 층은 상기 구리 기둥 바로 위에 있는 일부분을 포함하며,
    상기 집적 회로 구조는 상기 니켈 층 위에 금 층(gold layer) 또는 팔라듐 층(paladium layer)을 더 포함하는 것인 집적 회로 구조.
KR1020100037554A 2009-04-30 2010-04-22 구리 기둥을 갖는 웨이퍼 후면 구조 KR101121320B1 (ko)

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