201118992 六、發明說明： 【發明所屬之技術領域】 本發明有關於一種半導體製程技術，特別是有關於一 種用於晶片導通孔（through substrate via，TSV )結構及其 製造方法。 【先前技術】 隨著半導體技術的向上發展，積體電路的集積度 (integration)或是電子元件（例如，電晶體、二極體、電 阻、電容等等）的密度得以不斷提升。一般來說，集積度 的提升來自於不斷縮小元件的尺寸。然而，因為電子元件 所佔的空間是位於晶圓的表面，所以集積度的提升事實上 是從二維（2D)方面著手。儘管藉由提升微影（lith〇graphy) 技術可以獲得更小的元件尺寸，然而二維空間所能擁有的 岔度仍是有限。因此，目前正積極開發三維積體電路 (three-dimensional integrated circuit, 3DIC)堆疊封裝，其 中透過晶片導通孔（TSV)作為其内部的連接路徑以實現 多重晶圓或晶片堆疊結構，進而達到提升集積度的目的。 二般而言，晶片導通孔是在晶圓或晶片上以蝕刻或雷 射方式形成鑽孔（Viahole)，再將導電材料填入鑽孔内並 進2晶圓或晶片薄化，使上述鑽孔變成通孔（thr〇ugh h〇le ) 並硌出填入的導電材料而形成Tsv。最後將具有的晶 圓或晶片加以堆疊便可構成3DIC堆疊封裝。相較於傳統 利用打線接合（wke bGnding)的堆4封裝技術而言，3脈 堆疊封裝具有TSV的3DIC可縮短内部連接路徑，進而增 201118992 加晶片的傳輸速度、降低雜訊及提升裝置效能。 一般而言，在進行晶圓薄化製程之後，需要在研磨面 進行絕緣製程以避免漏電流發生。第1八至1D圖係繪示出 在晶圓研磨面進行絕緣製程的剖面示意圖。請參照第1A 圖，提供一經由機械研磨（grinding )及化學機械研磨 (chemical mechanical polishing，CMP )進行薄化的矽晶圓 1〇〇，其具有至少一通孔l〇〇a。一晶片導通孔1〇5，包括： 設置於通孔100a内的一導電插塞1〇4及與其電性連接的接 鲁合塾。晶片導通孔105透過絕緣層1〇2以與石夕晶圓1〇〇 電性絕緣的，例如氧化石夕。 請參照第1B圖，在矽晶圓ι〇〇表面（通常稱之為晶圓 背面）沉積一絕緣層106。接著，在絕緣層106上形成一 光阻層108 °之後，藉由微影製程圖案化光阻層1〇8以露 出位於晶片導通孔105上方的絕緣層1〇6，並以圖案化的 光阻層108作為姓刻罩幕，以去除露出的絕緣層1〇6而形 成開口 109，如第1C圖所示。 •請參照第1D圖，在去除圖案化的光阻層1〇8之後， 在開口 109上方形成一凸塊（bmnp) no。凸塊no透過 開口 109而與下方的晶片導通孔1〇5電性連接並提供後續 晶圓堆疊對接之用。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor process technology, and more particularly to a through substrate via (TSV) structure and a method of fabricating the same. [Prior Art] With the advancement of semiconductor technology, the integration of integrated circuits or the density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) has been increasing. In general, the increase in the degree of accumulation comes from the constant reduction in the size of components. However, since the space occupied by electronic components is on the surface of the wafer, the increase in the degree of accumulation actually starts from the two-dimensional (2D) aspect. Although smaller component sizes can be obtained by lith〇graphy techniques, the two-dimensional space has limited latitude. Therefore, three-dimensional integrated circuit (3DIC) stacked packages are currently being actively developed, in which through-wafer vias (TSVs) are used as internal connection paths to realize multiple wafer or wafer stack structures, thereby achieving enhanced accumulation. The purpose of the degree. In general, a wafer via hole is formed by etching or laser forming a via hole on a wafer or a wafer, and then filling a conductive material into the hole and thinning the wafer or wafer to make the hole. It becomes a through hole (thr〇ugh h〇le) and throws out the filled conductive material to form Tsv. Finally, the wafers or wafers are stacked to form a 3DIC stacked package. Compared to the traditional stacking 4 package technology using wire bonding (wke bGnding), 3DIC stacked package with TSV 3DIC can shorten the internal connection path, thereby increasing the transmission speed of the 201118992 plus wafer, reducing noise and improving device performance. In general, after the wafer thinning process, an insulating process is required on the polished surface to avoid leakage current. The first eight to fifth drawings show a schematic cross-sectional view of the insulating process on the wafer polishing surface. Referring to FIG. 1A, there is provided a tantalum wafer 1 which is thinned by mechanical grinding and chemical mechanical polishing (CMP), and has at least one through hole 10a. A wafer via hole 1〇5 includes: a conductive plug 1〇4 disposed in the through hole 100a and a solder joint electrically connected thereto. The wafer via 105 is transmitted through the insulating layer 1〇2 to be electrically insulated from the X-ray wafer 1〇〇, such as oxidized oxide. Referring to Figure 1B, an insulating layer 106 is deposited on the surface of the wafer (commonly referred to as the back side of the wafer). Next, after forming a photoresist layer 108° on the insulating layer 106, the photoresist layer 1〇8 is patterned by a lithography process to expose the insulating layer 1〇6 located above the via hole 105 of the wafer, and patterned light. The resist layer 108 is used as a surname mask to remove the exposed insulating layer 1〇6 to form an opening 109 as shown in FIG. 1C. • Referring to FIG. 1D, after removing the patterned photoresist layer 1〇8, a bump (bmnp) no is formed over the opening 109. The bumps are electrically connected to the underlying wafer vias 1〇5 through the openings 109 and provide subsequent wafer stack docking.
然而’利用微影來進行絕緣層1〇6的開孔會增加TSV 結構的製造成本。再者，上述TSV結構需在晶片導通孔105 上額外形成凸塊110以供晶圓堆疊對接之用，因此也會進 一步增加製造成本。另外，隨著晶片導通孔105尺寸曰漸 縮小’進行微影時對位的困難度也隨之增加’而影響TSV 201118992 結構的可靠度。 因此，有必要尋求一種新的TSV結構及製造方法，其 能夠解決上述的問題。 【發明内容】 有鑑於此，本發明提供一種晶片導通孔結構，其包括： 一基底、一第一絕緣層、一導電插塞及一第二絕緣層。基 底具有至少一通孔自基底的一第一表面延伸至相對於第一 表面的一第二表面。第一絕緣層設置於通孔的側壁。導電 插塞設置於通孔内且突出於基底的該第一表面。導電插塞 藉由第一絕緣層而與基底絕緣。第二絕緣層具有一第一部 覆蓋基底的第一表面及一第二部垂直於第一部且環繞突出 於基底的第一表面的導電插塞。 本發明提供一種晶片導通孔結構之製造方法。提供一 基底，其中基底内具有至少一通孔自基底的一第一表面延 伸至相對於第一表面的一第二表面，且通孔内具有一導電 插塞以及夾設於通孔侧壁與導電插塞之間的一第一絕緣 層。自第一表面#刻基底至一既定深度以形成一第三表 面，使導電插塞突出於第三表面。在基底上形成一第二絕 緣層，其中第二絕緣層具有一第一部覆蓋基底的第三表面 及一第二部垂直於第一部且環繞突出於基底的第三表面的 導電插塞。 【實施方式】 201118992 以下說明本發明實施例之製作與使用。然而，可輕易 了％本發明所提供的實施例僅用於說明以特定方法製作及 使用本發明，並非用以侷限本發明的範圍。 第3圖係分別繪示出根據本發明一實施例之晶片導通 孔結構剖面示意圖。請參照第3圖，晶片導通孔結構2〇〇 包括一基底202，例如一半導體晶圓或晶片。在本實施例 中，基底202具有至少一通孔202a自基底202的下表面 203c延伸至基底202的上表面203b。此處，下表面2〇3c 籲表示半導體晶圓或晶片的一表面，其上未形成任何半導體 元件（或稱之為晶圓/晶片背面）。再者，上表面203b表 示半導體晶圓或晶片中相對於下表面203c的一表面，其上 可形成任何半導體元件或内連結構（或稱之為晶圓/晶片正 面）。 一絕緣層204，例如氧化矽、氮化矽、聚亞醯胺 (polyimide，PI)或苯環丁烯（benzozyzlobutene, BCB)， s史置於通孔202a的侧壁且自通孔202a的側壁延伸至基底 籲202的上表面203b。 一導電插塞206，例如銅、鋁、鎢、或多晶石夕或其組 合，β又置於通孔202a内，其藉由絕緣層2〇4而與基底202 絕緣。在本實施例中，導電插塞2〇6與絕緣層2〇4突出於 基底的下表面203c，其中突出於下表面203c的導電插塞 2 06部分可取代傳統晶圓/晶片堆疊中用以電性連接不同晶 圓/晶片的凸塊或接合墊。在一實施例中，突出於下表面 203c的導電插塞206部分，其高度可在2微米（μιη)至5 微米的範圍。 201118992 一接合墊208，設置於位在基底202的上表面203b的 絕緣層204上且連接至導電插塞206。接合墊208的材質 可相同或相似於導電插塞206，其同樣藉由絕緣層204而 與基底202絕緣。再者，導電插塞206與接合墊208係構 成一晶片導通孔209。 一絕緣層211與突出於基底的下表面203c的絕緣層 204相鄰。在本實施例t，絕緣層211具有一第一部210a 及垂直於第一部210a的一第二部210b。絕緣層211的第 一部21〇a係覆蓋基底202的下表面203c。再者，絕緣層 211的第二部21〇b係環繞突出於基底202的下表面203c 的導電插塞206，使絕緣層204夾設於導電插塞206與絕 緣層211的第二部21〇b之間。在一實施例中，絕緣層211 及204具有相同或相似的材質。在其他實施例中，絕緣層 211及204可具有不同的材質。舉例來說，絕緣層211可 由有機材料所構成，例如聚亞醯胺或笨環丁烯。而絕緣層 2〇4可由無機材料所構成，例如氧化矽或氮化矽。 第2A至2C及2C-1圖係繪示出根據本發明不同實施 例之晶片導通孔結構之製造方法剖面示意圖。請參照第2A 圖，提供一基底202例如一半導體晶圓或晶片。基底202 中可包含各種不同的元件，例如電晶體、電阻、及其他習 知的半導體元件。再者，基底2〇2亦可包含其他導電層， 例如銅金屬’其通常用於連接基底2〇2上分離的半導體裝 置。此處為了簡化圖式，僅以一平整基底表示之。在本實 化例中’基底202具有至少一通孔2〇2a自基底202的下表 面203a延伸至基底2〇2的上表面2〇3b。此處，下表面203a 201118992 表示半導體晶圓或晶片的一表面，其上未形成任何半導體 元件（或稱之為晶圓/晶片背面）。再者，上表面表 示半導體晶圓或晶片中相對於下表面203a的一表面，其上 可形成任何半導體元件或内連結構（或稱之為晶圓/晶片'正 面）。通孔202a内具有一導電插塞2〇6以及夾設於通孔 202a側壁與導電插塞206之間的一絕緣層204。再者，絕 緣層204自通孔202a的側壁延伸至基底2〇2的上表面 203b。一接合墊208，位於基底202的上表面203b的絕緣 層204上且連接至導電插塞206 〇在本實施例中，導電插 塞206的材質包括：銅、鋁、鎢、或多晶矽或其組合。接 合塾208的材質可相同或相似於導電插塞2〇6。再者，導 電插塞206與接合塾208係構成一晶片導通孔209。絕緣 層204的材質包括：氧化矽、氮化矽、聚亞醯胺（ρι)或 苯環丁烯（BCB)。導電插塞206與接合墊208藉由絕緣 層204而與基底202絕緣。 請參照第2B圖’自基底202的下表面203a (如第2A 圖所示）蝕刻基底202至一既定深度d，例如在2微米（μιη) 至5微米的範圍，以形成低於導電插塞2〇6的一下表面 203c。亦即’在蝕刻基底202後，原先位於通孔2〇2a内的 導電插塞206及絕緣層204會突出於下表面203c。突出於 下表面203C的導電插塞206部分可取代傳統晶圓/晶片堆 疊中用以電性連接不同晶圓/晶片的凸塊或接合墊。在一實 %例中’可藉由乾钕刻進行基底202的钱刻，例如反應離 子餘刻（reactive ion etching，RIE)或其他習用乾蝕刻技術。 請參照第2C圖，在基底202的下表面203c上形成一 201118992 絕緣層211並順應性覆蓋突出於下表面203c的導電插塞 206及絕緣層204,用以提供晶片導通孔絕緣之用，避免發 生漏電流。在一實施例中，絕緣層211的材質可相同或相 似於絕緣層204。在另一實施例中，絕緣層211的材質可 不同於絕緣層204。在本實施例中，絕緣層211包括一無 機絕緣材料，例如氧化矽或氮化矽，且藉由化學氣相沉積 (chemical vapor deposition，CVD)或其他習知沉積技術而 形成之。 之後，可藉由研磨（grinding)或化學機械研磨（CMP ) 去除部份的絕緣層211以露出導電插塞206。特別的是絕 緣層211具有一第一部210a覆蓋基底202的下表面203c 及一第二部210b垂直於第一部210a且環繞突出於基底202 的下表面203c的導電插塞206,如第3圖所示。如此一來， 便完成本實施例之晶片導通孔結構之製作。 另外，在其他實施例中，絕緣層211的材質可包括一 有機絕緣材料’例如PI或BCB，且藉由塗佈（coating)的 方式而形成之。由於突出的導電插塞206與基底202的下 表面203c形成高低落差（step height )，因此藉由塗佈所 形成的絕緣層211，其位於導電插塞206上方的厚度會低 於位於基底202的下表面203c上的厚度，如第3C-1圖所 示。因此，除了可藉由研磨或化學機械研磨去除部份的絕 緣層211之外’也可使用乾蝕刻，例如RIE，以露出導電 插塞206，如第4圖所示。 根據上述實施例，覆蓋導電插塞206的絕緣層211石夕 採用研磨的方式露出下方的導電插塞206。相較於傳統透 201118992 過微影及蝕刻的方式，上述實施例可有效降低製造成本同 時無進行微影時對位的問題。再者，本實施例中晶片導通 孔結構可利用突出於基底202的下表面203c的導電插塞 206作為後續晶圓/晶片堆疊對接之用，因此可進一步降低 製造成本。另外，除了絕緣層204可提供導電插塞206絕 緣保護之外，絕緣層211的第二部210b亦可進一步加強導 電插塞206絕緣保護，使晶片導通孔結構的可靠度增加。 雖然本發明已以較佳實施例揭露如上，然其並非用以 • 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作更動與潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者為準。However, the use of lithography for the opening of the insulating layer 1 〇 6 increases the manufacturing cost of the TSV structure. Moreover, the above TSV structure requires additional bumps 110 on the via vias 105 for wafer stack docking, thereby further increasing manufacturing costs. In addition, as the size of the via hole 105 is gradually reduced, the difficulty of alignment during lithography is also increased, which affects the reliability of the TSV 201118992 structure. Therefore, it is necessary to find a new TSV structure and manufacturing method that can solve the above problems. SUMMARY OF THE INVENTION In view of this, the present invention provides a wafer via structure comprising: a substrate, a first insulating layer, a conductive plug, and a second insulating layer. The substrate has at least one through hole extending from a first surface of the substrate to a second surface opposite the first surface. The first insulating layer is disposed on a sidewall of the through hole. A conductive plug is disposed in the through hole and protrudes from the first surface of the substrate. The conductive plug is insulated from the substrate by the first insulating layer. The second insulating layer has a first portion covering the first surface of the substrate and a second portion perpendicular to the first portion and surrounding the conductive plug protruding from the first surface of the substrate. The present invention provides a method of fabricating a via via structure. Providing a substrate, wherein the substrate has at least one through hole extending from a first surface of the substrate to a second surface opposite to the first surface, and the through hole has a conductive plug and is disposed on the sidewall of the through hole and electrically conductive a first insulating layer between the plugs. The substrate is etched from the first surface to a predetermined depth to form a third surface such that the conductive plug protrudes from the third surface. A second insulating layer is formed on the substrate, wherein the second insulating layer has a first portion covering the third surface of the substrate and a second portion perpendicular to the first portion and surrounding the conductive plug protruding from the third surface of the substrate. [Embodiment] 201118992 The following describes the production and use of the embodiments of the present invention. However, the present invention is not intended to limit the scope of the invention. Fig. 3 is a schematic cross-sectional view showing the structure of a via hole of a wafer according to an embodiment of the present invention. Referring to Figure 3, the wafer via structure 2A includes a substrate 202, such as a semiconductor wafer or wafer. In the present embodiment, the substrate 202 has at least one through hole 202a extending from the lower surface 203c of the substrate 202 to the upper surface 203b of the substrate 202. Here, the lower surface 2 〇 3c calls for a surface of a semiconductor wafer or wafer on which no semiconductor elements (or wafer/wafer backs) are formed. Further, the upper surface 203b represents a surface of the semiconductor wafer or wafer relative to the lower surface 203c on which any semiconductor element or interconnect structure (or wafer/wafer front side) can be formed. An insulating layer 204, such as hafnium oxide, tantalum nitride, polyimide (PI) or benzozyzlobutene (BCB), is placed on the sidewall of the via 202a and is from the sidewall of the via 202a. It extends to the upper surface 203b of the base call 202. A conductive plug 206, such as copper, aluminum, tungsten, or polycrystalline or a combination thereof, is again placed in the via 202a, which is insulated from the substrate 202 by an insulating layer 2〇4. In this embodiment, the conductive plug 2〇6 and the insulating layer 2〇4 protrude from the lower surface 203c of the substrate, wherein the conductive plug 206 portion protruding from the lower surface 203c can be used in place of the conventional wafer/wafer stack. Electrically connect bumps or bond pads of different wafers/wafers. In one embodiment, the portion of the conductive plug 206 that protrudes from the lower surface 203c may have a height in the range of 2 micrometers (μm) to 5 micrometers. 201118992 A bond pad 208 is disposed over the insulating layer 204 on the upper surface 203b of the substrate 202 and is coupled to the conductive plug 206. Bond pad 208 may be the same or similar to conductive plug 206, which is also insulated from substrate 202 by insulating layer 204. Moreover, the conductive plug 206 and the bonding pad 208 form a wafer via 209. An insulating layer 211 is adjacent to the insulating layer 204 that protrudes from the lower surface 203c of the substrate. In the present embodiment t, the insulating layer 211 has a first portion 210a and a second portion 210b perpendicular to the first portion 210a. The first portion 21a of the insulating layer 211 covers the lower surface 203c of the substrate 202. Furthermore, the second portion 21b of the insulating layer 211 surrounds the conductive plug 206 protruding from the lower surface 203c of the substrate 202, so that the insulating layer 204 is sandwiched between the conductive plug 206 and the second portion 21 of the insulating layer 211. Between b. In an embodiment, the insulating layers 211 and 204 have the same or similar materials. In other embodiments, the insulating layers 211 and 204 can have different materials. For example, the insulating layer 211 may be composed of an organic material such as polyamidene or stupid cyclobutene. The insulating layer 2〇4 may be composed of an inorganic material such as hafnium oxide or tantalum nitride. 2A to 2C and 2C-1 are schematic cross-sectional views showing a method of fabricating a via via structure in accordance with various embodiments of the present invention. Referring to FIG. 2A, a substrate 202 such as a semiconductor wafer or wafer is provided. A variety of different components can be included in substrate 202, such as transistors, resistors, and other conventional semiconductor components. Furthermore, the substrate 2〇2 may also comprise other conductive layers, such as copper metal, which are typically used to connect the semiconductor devices separated on the substrate 2〇2. Here, in order to simplify the drawing, it is represented only by a flat substrate. In the present embodiment, the substrate 202 has at least one through hole 2〇2a extending from the lower surface 203a of the substrate 202 to the upper surface 2〇3b of the substrate 2〇2. Here, the lower surface 203a 201118992 represents a surface of a semiconductor wafer or wafer on which no semiconductor elements (or wafer/wafer backs) are formed. Further, the upper surface represents a surface of the semiconductor wafer or wafer relative to the lower surface 203a on which any semiconductor component or interconnect structure (or wafer/wafer 'front side) can be formed. The through hole 202a has a conductive plug 2〇6 and an insulating layer 204 interposed between the sidewall of the through hole 202a and the conductive plug 206. Further, the insulating layer 204 extends from the sidewall of the via 202a to the upper surface 203b of the substrate 2〇2. A bonding pad 208 is disposed on the insulating layer 204 of the upper surface 203b of the substrate 202 and is connected to the conductive plug 206. In this embodiment, the material of the conductive plug 206 includes: copper, aluminum, tungsten, or polysilicon or a combination thereof. . The material of the joint 208 can be the same or similar to the conductive plug 2〇6. Furthermore, the conductive plug 206 and the bonding pad 208 form a wafer via 209. The material of the insulating layer 204 includes cerium oxide, cerium nitride, polyamidene (ρι) or benzocyclobutene (BCB). Conductive plug 206 and bond pad 208 are insulated from substrate 202 by insulating layer 204. Referring to FIG. 2B', the substrate 202 is etched from a lower surface 203a of the substrate 202 (as shown in FIG. 2A) to a predetermined depth d, for example, in the range of 2 micrometers (μm) to 5 micrometers to form a lower conductive plug. 2 〇 6 of the lower surface 203c. That is, after the substrate 202 is etched, the conductive plugs 206 and the insulating layer 204 originally located in the via holes 2〇2a protrude from the lower surface 203c. The portion of the conductive plug 206 that protrudes from the lower surface 203C can replace the bump or bond pad in the conventional wafer/wafer stack for electrically connecting different wafers/wafers. In a real example, the engraving of the substrate 202 can be performed by dry etching, such as reactive ion etching (RIE) or other conventional dry etching techniques. Referring to FIG. 2C, a 201118992 insulating layer 211 is formed on the lower surface 203c of the substrate 202 and the conductive plug 206 and the insulating layer 204 protruding from the lower surface 203c are compliantly covered to provide insulation for the via hole of the wafer. Leakage current occurs. In an embodiment, the material of the insulating layer 211 may be the same or similar to the insulating layer 204. In another embodiment, the material of the insulating layer 211 may be different from the insulating layer 204. In the present embodiment, the insulating layer 211 comprises an inorganic insulating material such as hafnium oxide or tantalum nitride, and is formed by chemical vapor deposition (CVD) or other conventional deposition techniques. Thereafter, a portion of the insulating layer 211 may be removed by grinding or chemical mechanical polishing (CMP) to expose the conductive plug 206. In particular, the insulating layer 211 has a first portion 210a covering the lower surface 203c of the substrate 202 and a second portion 210b perpendicular to the first portion 210a and surrounding the conductive plug 206 protruding from the lower surface 203c of the substrate 202, such as the third portion The figure shows. In this way, the fabrication of the via via structure of the present embodiment is completed. In addition, in other embodiments, the material of the insulating layer 211 may include an organic insulating material such as PI or BCB, and is formed by coating. Since the protruding conductive plug 206 forms a step height with the lower surface 203c of the substrate 202, the thickness of the insulating layer 211 formed above the conductive plug 206 may be lower than that of the substrate 202 by coating the formed insulating layer 211. The thickness on the lower surface 203c is as shown in Fig. 3C-1. Therefore, dry etching, such as RIE, may be used in addition to removing a portion of the insulating layer 211 by grinding or chemical mechanical polishing to expose the conductive plug 206, as shown in Fig. 4. According to the above embodiment, the insulating layer 211 covering the conductive plug 206 is exposed to the underlying conductive plug 206 by grinding. Compared with the conventional method of lithography and etching, the above embodiment can effectively reduce the manufacturing cost and the problem of alignment without lithography. Moreover, the wafer via structure in this embodiment can utilize the conductive plugs 206 protruding from the lower surface 203c of the substrate 202 for subsequent wafer/wafer stack docking, thereby further reducing manufacturing costs. In addition, in addition to the insulating layer 204 providing insulation protection of the conductive plug 206, the second portion 210b of the insulating layer 211 can further enhance the insulation protection of the conductive plug 206, thereby increasing the reliability of the wafer via structure. While the invention has been described above in terms of a preferred embodiment, it is not intended to be construed as limiting the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
11 201118992 【圖式簡單說明】 第1A至1D圖係繪示出習知晶片導通孔結構之製造方 法剖面示意圖。 第2A至2C及2C-1圖係繪示出根據本發明不同實施 例之晶片導通孔結構之製造方法剖面示意圖。 第3圖係繪示出根據本發明一實施例之晶片導通孔結 構剖面示意圖。 第4圖係繪示出根據本發明另一實施例之晶片導通孔 結構剖面示意圖。 【主要元件符號說明】 習知 100〜碎晶圓， 100a〜通孔； 102、106〜絕緣層； 103〜接合墊； 104〜導電插塞； 105〜晶片導通孔； 10 8〜光阻層； 109〜開口； 110〜凸塊。 本實施例 12 201118992 200〜晶片導通孔結構； 2 02〜基底， 202a〜通孔； 203a、203c〜下表面； 203b〜上表面； 204、211〜絕緣層； 206〜導電插塞； 208〜接合墊； • 209〜晶片導通孔； 210a〜第一部； 210b〜第二部； d〜既定厚度。 Γ 5； 1 1311 201118992 [Simple description of the drawings] Figs. 1A to 1D are schematic cross-sectional views showing a manufacturing method of a conventional wafer via structure. 2A to 2C and 2C-1 are schematic cross-sectional views showing a method of fabricating a via via structure in accordance with various embodiments of the present invention. Fig. 3 is a cross-sectional view showing the structure of a via hole of a wafer according to an embodiment of the present invention. Fig. 4 is a cross-sectional view showing the structure of a via hole of a wafer according to another embodiment of the present invention. [Major component symbol description] Conventional 100 ~ shredded wafer, 100a ~ through hole; 102, 106 ~ insulating layer; 103 ~ bonding pad; 104 ~ conductive plug; 105 ~ wafer via; 10 8 ~ photoresist layer; 109 ~ opening; 110 ~ bumps. This embodiment 12 201118992 200~ wafer via structure; 2 02~ substrate, 202a~ via hole; 203a, 203c~ lower surface; 203b~ upper surface; 204, 211~ insulating layer; 206~ conductive plug; 208~ bonding Pad; • 209~ wafer via; 210a~1; 210b~2; d~ predetermined thickness. Γ 5; 1 13