CN101771012A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN101771012A
CN101771012A CN200910141836A CN200910141836A CN101771012A CN 101771012 A CN101771012 A CN 101771012A CN 200910141836 A CN200910141836 A CN 200910141836A CN 200910141836 A CN200910141836 A CN 200910141836A CN 101771012 A CN101771012 A CN 101771012A
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semiconductor
silicon
perforation
semiconductor device
silicon perforation
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CN101771012B (zh
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张宏宾
许国经
陈承先
邱文智
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体装置及其制造方法，用于堆叠裸片的隔离结构。该制造方法包括：于一半导体基底中形成硅穿孔，并薄化该半导体基底的背侧以露出硅穿孔。形成一隔离层于半导体基底的背侧与硅穿孔上，并薄化隔离层以重新露出硅穿孔。之后，形成一导电元件于硅穿孔上。本发明中提供的隔离结构，其围绕露出的硅穿孔，因此提供一较大的湿润表面，使焊球和基板之间可形成良好的电性连接。如此一来，可增加焊球的密度。此外，隔离层也可增加接合界面的机械强度。

Description

半导体装置及其制造方法
技术领域
本发明涉及集成电路，且特别涉及一种堆叠裸片的隔离结构。
背景技术
自从发明集成电路以来，由于各种电子元件(例如晶体管，二极管，电阻，电容等)的集成度持续不断的改良，半导体产业已经经历了快速的成长。此种集成度的改良使得最小特征尺寸不断减少，让元件可以整合在一个特定区域。
上述集成度的改善在本质上是二维(平面)的性质，因为集成电路所占用的体积基本上是在半导体晶片的表面。虽然光刻技术的进步已使得二维集成电路的制作得到相当大的改良，但在二维上可达到的密度有其物理上的限制。其中一个限制便是制作这些元件所需的最小尺寸。而且当需要将更多元件放置在同一芯片上时，所需要的设计也越复杂。为了更进一步增加电路密度，业界提出了所谓的”三维(3D)集成电路”。在典型的三维(3D)集成电路工艺中是将两个裸片互相接合并与基底上的接触垫形成电性连接。例如，可将两个裸片的顶部互相接合，然后将堆叠的裸片接合至一载板，并以焊线将每一裸片的接合垫电性连接至载板的接合垫。
硅穿孔(TSV；Through-Silicon Via)技术为近来发展的重点。一般来说，TSV技术是将基板蚀刻出一垂直孔洞，并在孔洞中填入导电材料，如铜。将基板的背面薄化后露出TSV，并在TSV上直接设置焊球以提供电性接触。之后，在焊球放置另一裸片即可形成堆叠裸片封装。
由于基板经过了薄化，于基板电路面进行的介电工艺并未形成于背面，于是基板背面是在缺乏保护的情况下，把焊球放置在暴露的TSV，使得表面的润湿性不足，焊球和基板之间无法形成良好的电性连接。此外，该结构限制了接合面的机械强度并限制了I/O引脚总数。
因此，业界亟须一种接合TSV的改良结构与方法。
发明内容
为了解决现有存在的上述问题，本发明提供一种半导体装置，包括：一半导体基底，其具有相对的电路侧与背侧；多个硅穿孔，延伸进入半导体基底，且每一硅穿孔具有一突出部，突出于半导体基底的背侧；一隔离层，位于半导体基底的背侧且介于相邻的硅穿孔之间，隔离层未延伸超过每一硅穿孔的突出部的顶端；以及，一导电元件，位于每一硅穿孔的突出部上。
本发明也提供一种半导体装置的制造方法，包括：提供一半导体基底，其具有一硅穿孔从一电路侧延伸进入半导体基底；薄化半导体基底的背侧，使硅穿孔突出于半导体基底的背侧；形成一隔离层于半导体基底的背侧与硅穿孔上；薄化隔离层以露出硅穿孔；以及，形成一导电元件于硅穿孔上。
本发明另提供一种半导体装置的制造方法，包括：提供一半导体基底，其具有相对的第一侧与第二侧，半导体基底具有一硅穿孔从第一侧部分延伸进入半导体基底；露出硅穿孔，使硅穿孔至少一部分突出于半导体基底的第二侧；形成一介电层于半导体基底的第二侧；形成一图案化掩模于介电层上，并露出硅穿孔上的介电层；以及，去除硅穿孔上的介电层。
本发明中提供的隔离结构，其围绕露出的硅穿孔，因此提供一较大的湿润表面，使焊球和基板之间可形成良好的电性连接。如此一来，可增加焊球的密度。此外，隔离层也可增加接合界面的机械强度。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下。
附图说明
图1-图5显示本发明于裸片上形成隔离结构的实施例。
图6-图11显示本发明于裸片上形成隔离结构的另一实施例。
图12-图16显示本发明于裸片上形成隔离结构的又一实施例。
图17-图21显示本发明于裸片上形成隔离结构的再一实施例。
上述附图中的附图标记说明如下：
110～基底
112～电路
114～蚀刻停止层
116～内层介电层
118～接触插塞
120～金属间介电层
122～顶层金属接触
124～硅穿孔
126～衬层
128～导电凸块
130～载板
132～粘着剂
310、610～隔离层
510、1110～连接元件
710～掩模层
1210、1710～晶种层
1310～图案化掩模
1312、1712～开口
1410、1910～导电接垫
具体实施方式
图1～图5示出一种具有隔离结构的裸片的制作方法，其可用于三维(3D)集成电路或堆叠裸片结构。在以下的实施例与图示中，类似的元件将以类似的标号表示。
图1显示一半导体基底110，其上形成有电路112。半导体基底110例如可包括：掺杂或未掺杂的硅块材(bulk Si)、或绝缘层上半导体(SOI；semiconductor-on-insulator)的主动层。一般而言，SOI基底包含一层半导体材料(例如硅)设置于一绝缘层上，例如埋藏氧化层(buried oxide layer)或氧化硅层。该绝缘层设置于一基底上，通常为硅基底或玻璃基底。此外，也可使用多层基底、梯度(gradient)基底等其他基底。
半导体基底110上的电路112可以是具有特定用途的任何电路。在一实施例中，电路112包括基底上的数个电子元件，且其上具有一个或多个介电层。介电层之间可形成金属层以作为电子元件之间的电性连接。电子元件也可形成在一个或多个介电层之中。
举例而言，电路112可包括各种N型金属氧化物半导体(NMOS)晶体管、P型金属氧化物半导体(PMOS)晶体管、电容、电阻、二极管、光二极管、熔丝等互相连接的元件以进行一种或多种功能。这些功能可包括：存储器结构、运算结构、感应器、放大器、配电系统、输入/输出电路等。此技术领域普通技术人员当可了解，上述提到的例子只是作为举例之用，而非用来限定本发明的用途，因此，本发明也可使用其他的电路。
图1所示还包括一蚀刻停止层114与一内层介电层(ILD)116。蚀刻停止层114所使用的介电材质较佳与底下的半导体基底110及上方的内层介电层116具有不同的蚀刻选择率。在一实施例中，蚀刻停止层114可为SiN、SiCN、SiCO、CN、或前述的组合，其可利用化学气相沉积法(CVD；Chemical VaporDeposition)或等离子体加强化学气相沉积法(PECVD)等技术沉积。
内层介电层116可由氧化硅或低介电常数材料，例如磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、氟硅玻璃(FSG)、SiOxCy、旋涂式玻璃(Spin-On-Glass)、旋涂式高分子(Spin-On-Polymer)、碳化硅材料、前述的化合物、复合物、或组合所形成，其形成方式例如是旋转涂布、CVD、PECVD等各种公知技术。应注意的是，蚀刻停止层114与内层介电层116可各自包含数层介电层，且相邻的介电层之间可形成或不形成蚀刻停止层。
接触插塞118形成于内层介电层116中以提供电性接触至电路112。接触插塞118例如可用以下方式形成：首先，于内层介电层116上形成一光致抗蚀剂材料并利用光刻技术将之图案化，露出内层介电层116中欲形成接触插塞的部分。接着以蚀刻工艺，例如各向异性干蚀刻，在内层介电层116中形成开口。之后，较佳在开口中顺应性地形成扩散阻挡层和/或黏着层(未显示)后，填入导电材料。扩散阻挡层较佳包括TaN、Ta、TiN、Ti、CoW、或前述的组合。导电材料较佳包括铜、钨、铝、银、或前述的组合。如此，便可形成图1中的接触插塞118。
于内层介电层116上形成一层或多层金属间介电层(IMD)120以及相关的金属化层(未显示)，使电路之间能相互连通并提供外界的电性连接。金属间介电层120较佳是由低介电常数材料所形成，例如氟硅玻璃(FSG)，其可由PECVD或高密度等离子体CVD(HDP-CVD)等方式形成。金属间介电层120中可包含类似于蚀刻停止层114的蚀刻停止层。顶层金属接触(top metalcontact)122形成在最上层的金属间介电层120上以提供外界的电性连接。
图1更显示硅穿孔(through-silicon via)124。硅穿孔124可由适当方式形成，例如可在形成内层介电层116之前，以蚀刻、铣切(milling)、激光等一种或多种技术，形成穿入基底110的开口。开口中较佳形成衬层126作为隔离，然后再填入导电材料124。衬层126较佳包括氮化硅、氧化物、聚合物、或前述的组合。导电材料124可包括铜、钨、铝、银、或前述的组合。如此，便可形成硅穿孔124。此外，也可使用导电扩散阻挡层等其他材料，例如TaN、Ta、TiN、Ti、CoW、或前述的组合。
应注意的是，虽然图中所示的硅穿孔124是由基底110的上表面向下延伸，但在其他实施例中也可能是其他型态。例如，硅穿孔124可从内层介电层116或金属间介电层120的上表面向下延伸。在一实施例中，于接触插塞118形成后，利用蚀刻、铣切、激光等方式形成穿入基底110的开口，然后依照前述方式形成衬层与导电材料即可形成硅穿孔124。
顶层金属接触122上形成有导电凸块128，例如Cu、W、CuSn、AuSn、InAu、PbSn等金属凸块。载板130通过粘着剂(adhesive)132贴附于金属间介电层120的上表面。载板130可以在后续的工艺中提供机械上与结构上的暂时支撑，以减少或避免对半导体基底110的伤害。
载板130例如可包括：玻璃、氧化硅、氧化铝等。在一实施例中，可利用粘结剂132将载板130粘附到金属间介电层120(或保护层)的上表面。粘结剂132可以任何适当的粘结剂例如紫外光(UV)胶，其经过紫外光照射后会丧失黏性。载板130的较佳厚度可从数密尔(mil)到数十密尔(mil)的范围。
图2显示在基底110背面进行薄化工艺以露出硅穿孔124/衬层126。薄化工艺可使用机械磨削(Mechanical Grinding)、化学机械研磨、蚀刻工艺、或前述的组合。例如，可先利用磨削或化学机械研磨露出硅穿孔124，然后再以湿蚀刻或干蚀刻对半导体基底110进行凹蚀(recessing)，使硅穿孔124与衬层126突出于基底110表面，如图2所示，其中所用的湿蚀刻或干蚀刻对于衬层126材料与基底110材料具有高蚀刻选择比。在一实施例中，当硅穿孔124为铜，而衬层126为氧化物时，可以使用HBr/O2、HBr/Cl2/O2、SF6/Cl2、SF6等离子体等干蚀刻工艺对半导体基底110进行凹蚀。硅穿孔124与衬层126露出的部分较佳约从次微米到数微米。
图3显示在基底110背面(或基底表面的原生氧化层)形成隔离层310。在较佳实施例中，隔离层310为介电材料，例如SiN、氧化物、SiC、SiON、聚合物等，可利用旋转涂布、印刷、CVD等工艺形成。较佳者，隔离层310可利用低温工艺形成，例如低于250℃的PECVD工艺，如此可避免粘着剂劣化以确保整个工艺中的机械强度。
形成隔离层310后，视其形成的方式而定，可能需要进行平坦化工艺。有些沉积方式(如旋转涂布)可形成一平坦的表面，但有些沉积方式(如CVD)会形成顺应性(conformal)的表面，因此需要再进行磨削或化学机械研磨等平坦工艺以得到如图3所示的平坦表面。
图3显示以薄化工艺将硅穿孔124再次露出。薄化工艺可使用机械磨削、化学机械研磨、蚀刻工艺、或前述的组合。例如，可先利用磨削或化学机械研磨露出硅穿孔124，然后再以湿蚀刻或干蚀刻对隔离层310进行凹蚀，使硅穿孔124突出于隔离层310表面，如图4所示，其中所用的湿蚀刻或干蚀刻对硅穿孔124材料与衬层126、隔离层310材料具有高蚀刻选择比。在一实施例中，当硅穿孔124为铜时，可以使用干蚀刻工艺或氢氟酸的湿蚀刻工艺对隔离层310进行凹蚀。但在其他实施例中也可使用其他材料与蚀刻方式。硅穿孔124露出的部分较佳约从次微米到数微米。图4也显示衬层126在上述隔离层310的凹蚀步骤中被一并去除。
图5显示在露出的硅穿孔124上形成连接元件510。连接元件510可以是任何适当的导电材料，如Cu、Ni、Sn、Au、Ag等，且可用任何适当的方式形成，包括蒸镀、电镀、印刷、喷射(jetting)沉积、焊柱凸点(stud bump)技术、直接放置(direct placement)等方式。
之后可视实际需要进行各种后段工艺(BEOL；back-end-of-line)。例如，可去除载板130、形成封胶(encapsulant)、裸片切割(singulation)、晶片级或裸片级堆叠等工艺。应注意的是，本发明的实施例可以应用在各种情况，例如裸片对裸片接合、晶片对晶片接合、或裸片对晶片接合等。
图6-图11显示本发明于裸片上形成隔离结构的另一实施例，其适用于堆叠裸片结构。图6-图11的起始步骤具有如图2所示的结构，其中相似的元件符号代表相似的元件。
图6显示在基底110背面(或基底表面的原生氧化层)形成隔离层610。在一较佳实施例中，隔离层610为一层顺应性(conformal)的介电材料，例如SiN、氧化物、SiC、SiON、聚合物等，较佳者，隔离层610可利用低温工艺形成，例如低于250℃的PECVD工艺，如此可避免粘着剂劣化以确保整个工艺中的机械强度。隔离层610的厚度较佳数千埃
Figure G2009101418362D0000071
应注意的是，隔离层610的厚度小于硅穿孔124突出基板110的高度。
图7显示在隔离层610上形成掩模层710，图8显示进行回蚀刻工艺以露出位于硅穿孔124上的隔离层610。在一实施例中，掩模层710包括一光致抗蚀剂材料，但其他与底下隔离层610及衬层126具有高蚀刻选择性的材料也可使用。上述的回蚀刻工艺例如可使用干蚀刻。
之后，如图9所示，以干蚀刻或湿蚀刻工艺去除硅穿孔124上的隔离层610与衬层126以露出硅穿孔124。上述干蚀刻或湿蚀刻对于掩模层710、硅穿孔124材料与隔离层610、衬层126材料具有高蚀刻选择性。在一实施例中，当硅穿孔124为铜时，可以使用干蚀刻工艺或氢氟酸的湿蚀刻工艺以露出硅穿孔124。但在其他实施例中也可使用其他材料与蚀刻方式。
图10显示掩模层710的去除。在一实施例中，当掩模层710为光致抗蚀剂时，可使用等离子体灰化或湿式剥除工艺将掩模层710去除。等离子体灰化工艺条件较佳例如：氧气流量约1000-2000sccm、压力约300-600mTorr、功率约500-2000瓦、温度约80-200℃。进行等离子体灰化后，可视需要将晶片浸在一溶剂中进行清洁并去除任何残留的光致抗蚀剂材料。
图11显示在露出的硅穿孔124上形成连接元件1110。连接元件1110可以是任何适当的导电材料，如Cu、Ni、Sn、Au、Ag等，且可用任何适当的方式形成，包括蒸镀、电镀、印刷、喷射(jetting)沉积、焊柱凸点(stud bump)技术、直接放置(direct placement)等方式。
之后可视实际需要进行各种后段工艺(BEOL；back-end-of-line)。例如，可去除载板130、形成封胶(encapsulant)、裸片切割(singulation)、晶片级或裸片级堆叠等工艺。应注意的是，本发明的实施例可以应用在各种情况，例如裸片对裸片接合、晶片对晶片接合、或裸片对晶片接合等。
图12-图16显示本发明于裸片上形成隔离结构的又一实施例，其适用于堆叠裸片结构。图12-图16的起始步骤具有如图4所示的结构，其中相似的元件符号代表相似的元件。
请参照图12，在隔离层310与硅穿孔124露出的表面上沉积一顺应性的晶种层1210。晶种层1210为一导电薄膜，其可帮助后续形成较厚的膜层。在一实施例中，晶种层1210可利用CVD或物理气相沉积法(PVD；PhysicalVapor Deposition)形成例如Cu、Ti、Ta、TiN、TaN等薄导电层。例如，可利用PVD形成Ti阻挡层，再以PVD形成Cu晶种层。
图13显示在晶种层1210上形成一图案化掩模1310。图案化掩模1310较佳包括图案化光致抗蚀剂、硬掩模等。在一较佳实施例中，沉积一光致抗蚀剂材料并将之图案化而在硅穿孔124上形成开口1312。
之后，如图14所示，在开口1312中形成导电接垫(conductive pad)1410。导电接垫1410例如可利用电镀、无电电镀等方式形成。在一实施例中，可将晶片浸入电镀液中进行电镀工艺，其中晶片表面电性连接至外部直流电源供应器的负极，以使晶片在电镀过程中作为阴极(cathode)，而固态导电阳极(anode)，例如铜阳极，也浸入电镀液中并连接至电源供应器的正极。来自阳极的原子溶入电镀液中然后到达阴极(晶片)，如此可在晶片露出的导电区域上(例如开口1312)进行电镀。
图15显示将图案化掩模1310去除。在一实施例中，当掩模层1310为光致抗蚀剂时，可使用等离子体灰化或湿式剥除工艺将掩模层1310去除。
图16显示将露出的晶种层1210去除。晶种层1210例如可利用湿蚀刻工艺加以去除。
之后可视实际需要进行各种后段工艺(BEOL；back-end-of-line)。例如，可去除载板130、形成封胶(encapsulant)、裸片切割(singulation)、晶片级或裸片级堆叠等工艺。应注意的是，本发明的实施例可以应用在各种情况，例如裸片对裸片接合、晶片对晶片接合、或裸片对晶片接合等。
图17-图21显示本发明于裸片上形成隔离结构的再一实施例，其适用于堆叠裸片结构。图17-图21的起始步骤具有如图10所示的结构，其中相似的元件符号代表相似的元件。
请参照图17，在隔离层610与硅穿孔124露出的表面上沉积一顺应性的晶种层1710。晶种层1710为一导电薄膜，其可帮助后续形成较厚的膜层且可包括一阻挡层。晶种层1710的形成方式与材质类似于图12的晶种层1210。
图18显示在晶种层1710上形成一图案化掩模1810。图案化掩模1310较佳包括图案化光致抗蚀剂、硬掩模等。在一较佳实施例中，沉积一光致抗蚀剂材料并将之图案化而在硅穿孔124上形成开口1812。
之后，在开口1812中形成导电接垫1910。导电接垫1910例如可利用电镀、无电电镀等方式形成，如图14的导电接垫1410。
图20显示将图案化掩模1810去除。在一实施例中，当掩模层1810为光致抗蚀剂时，可使用等离子体灰化或湿式剥除工艺将掩模层1810去除。进行等离子体灰化后，可视需要将晶片浸在一溶剂中进行清洁并去除任何残留的光致抗蚀剂材料。
图21显示将露出的晶种层1710去除。晶种层1710例如可利用湿蚀刻工艺加以去除。
之后可视实际需要进行各种后段工艺(BEOL；back-end-of-line)。例如，可去除载板130、形成封胶(encapsulant)、裸片切割(singulation)、晶片级或裸片级堆叠等工艺。应注意的是，本发明的实施例可以应用在各种情况，例如裸片对裸片接合、晶片对晶片接合、或裸片对晶片接合等。
由以上实施例可知，本发明提供一种隔离结构，其围绕露出的硅穿孔，因此提供一较大的湿润表面，使焊球和基板之间可形成良好的电性连接。如此一来，可增加焊球的密度。此外，隔离层也可增加接合界面的机械强度。
虽然本发明已以数个较佳实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (15)

1.一种半导体装置，包括：
一半导体基底，其具有相对的电路侧与背侧；
多个硅穿孔，延伸进入该半导体基底，且每一硅穿孔具有一突出部，突出于该半导体基底的背侧；
一隔离层，位于该半导体基底的背侧且介于相邻的硅穿孔之间，该隔离层未延伸超过每一硅穿孔的突出部的顶端；以及
一导电元件，位于每一硅穿孔的突出部上。
2.如权利要求1所述的半导体装置，其中导电元件包括：一导电晶种层于每一硅穿孔的突出部上；以及，一导电接垫于该导电晶种层上。
3.如权利要求2所述的半导体装置，其中该导电晶种层延伸至部分的隔离层上。
4.如权利要求1所述的半导体装置，其中该隔离层延伸至每一硅穿孔的突出部的侧壁。
5.如权利要求1所述的半导体装置，其中该导电元件包含焊球。
6.一种半导体装置的制造方法，包括：
提供一半导体基底，其具有一硅穿孔从一电路侧延伸进入该半导体基底；
薄化该半导体基底的背侧，使该硅穿孔突出于该半导体基底的背侧；
形成一隔离层于该半导体基底的背侧与该硅穿孔上；
薄化该隔离层以露出该硅穿孔；以及
形成一导电元件于该硅穿孔上。
7.如权利要求6所述的半导体装置的制造方法，其中形成该导电元件的步骤包括：形成一焊球于该硅穿孔上。
8.如权利要求6所述的半导体装置的制造方法，其中形成该导电元件的步骤包括：形成一晶种层于该硅穿孔上；以及，形成一金属接垫于该晶种层上。
9.如权利要求6所述的半导体装置的制造方法，其中该半导体基底与该硅穿孔之间还包括一衬层，且还包括去除该硅穿孔上的该衬层。
10.如权利要求6所述的半导体装置的制造方法，其中去除该衬层的步骤是于该隔离层形成后进行。
11.如权利要求6所述的半导体装置的制造方法，其中该隔离层具有一平坦表面。
12.一种半导体装置的制造方法，包括：
提供一半导体基底，其具有相对的第一侧与第二侧，该半导体基底具有一硅穿孔从第一侧部分延伸进入该半导体基底；
露出该硅穿孔，使该硅穿孔至少一部分突出于该半导体基底的第二侧；
形成一介电层于该半导体基底的第二侧；
形成一图案化掩模于该介电层上，并露出该硅穿孔上的该介电层；以及
去除该硅穿孔上的该介电层。
13.如权利要求12所述的半导体装置的制造方法，其中该半导体基底与该硅穿孔之间更包括一衬层。
14.如权利要求13所述的半导体装置的制造方法，其中于形成该图案化掩模的后还包括：去除该衬层。
15.如权利要求13所述的半导体装置的制造方法，其中该衬层延伸至该硅穿孔的突出部分的侧壁。
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