CN102208393B - 半导体元件与其形成方法 - Google Patents

半导体元件与其形成方法 Download PDF

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CN102208393B
CN102208393B CN2010105257998A CN201010525799A CN102208393B CN 102208393 B CN102208393 B CN 102208393B CN 2010105257998 A CN2010105257998 A CN 2010105257998A CN 201010525799 A CN201010525799 A CN 201010525799A CN 102208393 B CN102208393 B CN 102208393B
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substrate
dielectric film
hole
layer
conductive unit
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CN102208393A (zh
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张宏宾
邱建明
吴仓聚
眭晓林
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体元件与其形成方法，应用于堆叠裸片形态的多层内连线结构。首先形成多个穿透基板通孔于半导体基板中。接着薄化半导体基板的背面以露出穿透基板通孔。之后形成绝缘膜于半导体基板背面上与露出的穿透基板通孔上。之后形成的第一导电单元分别电性耦合至每一穿透基板通孔，且第一导电单元延伸于绝缘膜上。接着形成一或多个额外绝缘膜与导电单元。之后形成连线单元如焊球以电性耦合至最上层的导电单元。本发明可避免或减少扩散的问题。

Description

半导体元件与其形成方法
技术领域
本发明涉及集成电路，且更特别涉及应用在含有穿透基板通孔的基板的内连线结构。
背景技术
半导体产业如集成电路的快速成长，奠基于不同电子元件如晶体管、二极管、电阻、电容、或类似物其集成密度的快速成长。集成密度的改善大部分归功于最小结构尺寸的持续缩减，这使整合至固定面积的元件数目不断增加。
对二维元件来说，改良集成度是基本的。在这里，集成元件主要存在于半导体晶片的表面。虽然大幅改善的光刻工艺会可观的改良二维集成电路，但二维的密度仍有其物理限制。限制之一为集成元件需有最小体积。此外，当越多的元件被置入单一芯片时，需要越复杂的设计。
三维的集成电路用以进一步增加集成密度。在三维的集成电路的一般工艺中，将两个裸片接合后，形成电性连接于每一裸片的接触垫与基板的接触垫之间。举例来说，某些公知方法接合两个裸片的顶部。接着将裸片堆叠接合至承载基板，并以打线接合的方法电性耦合每一裸片的接触垫至承载基板上的接触垫。上述方法中的承载基板需大于裸片堆叠，以利打线接合。
较新的方法则采用穿透基板通孔(TSV)。一般的TSV的形成方法是垂直蚀刻基板形成通孔，接着将导电材料如铜填入通孔。之后薄化基板背面以露出TSV，再将另一裸片接合至露出的TSV，以形成堆叠裸片封装。
发明内容
为克服现有技术中的缺陷，本发明提供一种半导体元件，包括第一基板；多个穿透基板通孔穿过第一基板，且穿透基板通孔自第一基板的背面凸起；第一绝缘膜位于第一基板的背面上及穿透基板通孔之间，且第一绝缘膜的上表面未超过凸起的穿透基板通孔；第一重新分布层延伸于第一绝缘膜上，第一重新分布层具有第一导电单元，且第一导电单元分别电性接触穿透基板通孔并延伸于第一绝缘膜上；第二绝缘膜位于第一重新分布层上；以及第二重新分布层延伸于第二绝缘膜上，第二重新分布层具有第二导电单元，且第二导电单元分别电性接触第一导电单元并延伸于第二绝缘膜上。
本发明也提供一种形成半导体元件的方法，包括提供第一基板，具有穿透基板通孔自第一基板的第一面穿入第一基板中；自第一基板的第二面露出穿透基板通孔；沿着第一基板的第二面形成第一绝缘膜，且第一绝缘膜仍露出穿透基板通孔；形成第一导电单元于穿透基板通孔上，且第一导电单元延伸于第一绝缘膜的上表面上；形成第二绝缘膜于第一绝缘膜上及第一导电单元上；以及形成第二导电单元电性耦合至第一导电单元，且第二导电单元延伸于第二绝缘膜的上表面上。
本发明更提供一种形成半导体元件的方法，包括提供基板，基板具有穿透基板通孔自基板的电路面延伸至基板的背面；形成重新分布层，包括形成第一绝缘膜于基板的背面上；露出至少部分上述穿透基板通孔；以及形成第一导电单元分别电性耦合至上述穿透基板通孔，且第一导电单元延伸于第一绝缘膜的上表面上；以及形成额外重新分布层，包括形成额外绝缘膜于最上层的绝缘膜上；露出至少部分较下层的导电单元；以及形成额外导电单元分别电性耦合至较下层的导电单元，且额外导电单元延伸于额外绝缘膜的上表面上。
本发明可避免或减少扩散的问题。
附图说明
图1-图16显示本发明一实施例中，多层内连线结构的工艺剖示图；
图17-图25显示本发明另一实施例中，多层内连线结构的工艺剖示图；
图26-图35显示本发明又一实施例中，多层内连线结构的工艺剖示图；以及
图36-图40显示本发明更一实施例中，多层内连线结构的工艺剖示图。
其中，附图标记说明如下：
110～半导体基板；112～电路；114～蚀刻停止层；116～层间介电层；118～接触物；120～金属间介电层；122～金属接触物；124～穿透基板通孔；126～衬垫物；128～导电凸块；130～承载基板；132～接着物；310、2610～第一绝缘膜；510、3210～第一导电层；610、1810、3310、3710～第一图案化掩模；710、1910、3410、3810～第一导电单元；810～第二绝缘膜；910、2210～第二图案化掩模；1110～第二导电层；1210～第三图案化掩模；1310、2310～第二导电单元；1410～第三绝缘膜；1510～第四图案化掩模；1610～连线单元；1710、3610～第一籽晶层；2110～第二籽晶层；2710～第一掩模层。
具体实施方式
本发明的实施例的制备与应用将详述于下。然而必需理解的是，实施例用以说明可应用于特定方面的概念，但该些特定实施例仅用以举例而非局限本发明范畴。
下述实施例有关于应用在含有穿透基板通孔的基板的内连线结构。如下所述，实施例中将整合多层内连线结构与重新分布层，可具有更佳的工艺弹性以应用于不同的接脚组态。值得注意的是，用以举例的实施例只含有两层内连线层。但在其他实施例中，实施例中的工艺或其他类似工艺可形成多层的内连线结构，其内连线层的数目大于二。
图1-图16适用于三维集成电路或堆叠裸片组态的裸片的工艺剖示图，上述裸片具有内连线结构及/或重新分布层。在不同图示中，相同标号用以标示相同元件。
如图1所示，半导体基板110具有电路112形成其上。半导体基板110可包含掺杂或未掺杂的基体硅，或绝缘层上半导体(SOI)基板的有源层。一般的SOI基板包含半导体材料层如硅形成于绝缘层上。绝缘层可为氧化埋层(BOX)或氧化硅层。绝缘层形成于基板如硅基板或玻璃基板上。除了上述例子外，基板可为其他材料如多层基板或组成渐变式(gradient)基板。
形成于半导体基板110上的电路112可为任何特定用途的电路。在一实施例中，电路包括形成于基板上的电子元件，与位于电子元件上的一或多层介电层。在介电层间可形成金属层以传递电子元件之间的电子信号。电子元件亦可形成于一或多个介电层中。
举例来说，电路112可包含多种内连线的n型金属氧化物半导体(NMOS)或p型金属氧化物半导体(pMOS)元件如晶体管、电容、电阻、光二极管、熔线、或类似物，以执行一或多个功能。上述元件包含存储器结构、处理器结构、传感器、放大器、功率分配器、输入/输出电路、及/或类似物。本领域技术人员应理解上述实施例仅用以解释本发明，并非用以限制其他实施例。其他电路亦可适用于本发明。
图1所示的结构也包含蚀刻停止层114与层间介电层116。蚀刻停止层114由介电材料组成，其蚀刻选择性不同于邻近的其他层，如其下的半导体基板110与其上的层间介电层116。在一实施例中，蚀刻停止层114可为SiN、SiCN、SiCO、CN、上述的组合、或类似物。蚀刻停止层114的形成方法可为沉积法如化学气相沉积(CVD)或等离子体增强式CVD(PECVD)。
层间介电层116的组成可为低介电常数的介电材料，如氧化硅、含磷硅酸盐玻璃(PSG)、含硼磷硅酸盐玻璃(BPSG)、氟化硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂高分子、碳化硅材料、上述的化合物、上述的复合物、或类似物。层间介电层116的形成方法可为本领域的任何合适方法如旋涂法、CVD、或PECVD。必需注意的是，蚀刻停止层114与层间介电层116可各自包含多层的介电层，在相邻的介电层之间可含有或不含有蚀刻停止层。
穿过层间介电层116的接触物118可提供电性接触至电路112。接触物118的形成方法包含以光刻工艺沉积并图案化光致抗蚀剂材料于层间介电层116上，露出的部分层间介电层116将对应后续形成的接触物118。接着以蚀刻工艺如各向异性干蚀刻工艺形成开口于层间介电层116中。接着将扩散阻挡层及/或粘着层(未图示)作为开口衬垫，再填入导电材料。上述扩散阻挡层可包含一或多层的TaN、Ta、、TiN、Ti、CoW、或类似物。上述导电材料可包含铜、钨、铝、银、上述的组合、或类似物。经上述步骤后，即形成图1所示的接触物118。
在层间介电层116上形成有金属间介电层120与相关的金属化层(未图示)。一般来说，一或多层的金属间介电层120与相关的金属化层用以使电路之间彼此内连线，并提供外部电性连线。金属间介电层120的组成可为适合的介电材料如低介电常数材料，例如PECVD或高密度等离子体CVD(HDPCVD)形成的FSG。金属间介电层120亦可包含层间蚀刻停止层如蚀刻停止层114。金属接触物122形成于最上层的金属间介电层中，以提供外部电性连接。
图1的结构中也包含穿透基板通孔124，其形成方法可为任何合适方法。举例来说，在形成层间介电层116前，即可以一或多道蚀刻工艺、钻孔工艺、激光技术、或类似方法形成开口延伸至半导体基板110中。开口衬有衬垫物126作为绝缘层，并填充导电材料。衬垫物126可包含一或多层介电层如SiN、氧化物、高分子、上述的组合、或类似物。导电材料可包含一或多层的导电材料如铜、钨、铝、银、上述的组合、或类似物。经上述工艺后即形成穿透基板通孔124。上述结构可采用其他材料如导电物的扩散阻挡层，例如TaN、Ta、TiN、Ti、CoW、或类似物。
必需注意的是，图中的穿透基板通孔124由半导体基板110的上表面延伸至半导体基板110中，但穿透基板通孔124也可采用其他型态。举例来说，其他实施例的穿透基板通孔124可由层间介电层116或多层金属间介电层120之一的上表面往下延伸。举例来说，一实施例在形成接触物118之后，再以一或多道蚀刻工艺、钻孔工艺、激光技术、或类似方法形成穿透基板通孔124。其他型态的开口也可衬有衬垫物126作为绝缘层，并填有上述的导电材料。
导电凸块128如金属凸块Cu、W、CuSn、AuSn、InAu、PbSn、或类似物形成于顶端的金属接触物122上。承载基板130是以接着物132粘合至金属间介电层120的上表面上。一般来说，承载基板130可在后续工艺步骤中提供暂时的机械与结构支撑力。上述组态可避免或减少半导体基板110受到损伤。
承载基板130可包含玻璃、氧化硅、氧化铝、或类似物。接着物132可包含适当接着物如紫外线胶，在曝晒紫外线后将失去其接着性。承载基板130的厚度介于几微米至数十微米之间，端视特定应用中材料组成与所需的支撑力而定。
如图2所示的实施例中，在半导体基板110的背面进行薄化工艺后，露出穿透基板通孔124/衬垫物126。薄化工艺可为机械研磨法、化学机械研磨(CMP)、蚀刻工艺、及/或上述的组合。举例来说，首先进行平坦化工艺如研磨或CMP，先露出穿透基板通孔124。接着进行在衬垫物126与半导体基板110之间具有高蚀刻选择比的湿式或干式蚀刻，让半导体基板110凹化，并使保留的穿透基板通孔124与衬垫物凸出保留的半导体基板110，如图2所示。在一实施例中，穿透基板通孔124由铜组成，衬垫物126由TaN组成，而让半导体基板110凹化的干蚀刻工艺气体为HBr/O2、HBr/Cl2、SF6/Cl2、SF6等离子体、或类似物。在一实施例中，穿透基板通孔124与衬垫物126凸出的部分介于次微米至数微米之间。
图3显示第一绝缘膜310形成于半导体基板110的背面(或半导体基板110背面上的原生氧化层)上。在一实施例中，第一绝缘膜310是介电材料如SiN、氧化物、SiC、SiON、高分子、或类似物。第一绝缘膜310的形成方法可为旋转涂布法、印刷法、CVD工艺、或类似方法。第一绝缘膜310可由低温工艺形成，如小于250℃的PECVD工艺，以避免劣化元件之间的结合力并确保元件的机械强度。如图3所示的实施例，第一绝缘膜310的厚度需足以覆盖凸出的穿透基板通孔124。
第一绝缘膜的形成工艺将决定是否进行后续的平坦化工艺。在特定实施例中，某些沉积方法如旋转涂布法可形成平坦化表面。但其他沉积方法如CVD工艺将形成共形层，这需要进行平坦化工艺如研磨或CMP工艺以提供图3所示的平坦表面。
在图4的实施例中，第二次露出穿透基板通孔124。薄化工艺可为机械研磨工艺、CMP工艺、蚀刻工艺、及/或上述的组合。举例来说，首先进行平坦化工艺如研磨或CMP，先露出穿透基板通孔124。接着进行在穿透基板通孔124/衬垫物126与第一绝缘膜310的材料之间具有高蚀刻选择比的湿式或干式蚀刻，让第一绝缘膜310凹化，并使保留的穿透基板通孔124凸出保留的第一绝缘膜310，如图4所示。在一实施例中，穿透基板通孔124由铜组成，第一绝缘膜310由二氧化硅组成，而让第一绝缘膜310凹化的工艺可为湿蚀刻工艺如氢氟酸，或干蚀刻工艺如CF4、CHF3、CH2F2、C4F8、Ar、O2、或上述的组合。除了上述方式以外，也可采用其他工艺或材料。在一实施例中，穿透基板通孔124凸出的部分介于次微米至数微米之间。如图4所示，上述凹化第一绝缘膜310的工艺亦移除露出的衬垫物126。移除衬垫物126的步骤与凹化第一绝缘膜310的步骤可相同或分开，端视两者的材料而定。
如图5所示，第一导电层510沉积于第一绝缘膜310与露出的穿透基板通孔124的表面上。在一实施例中，第一导电层510可由沉积法如CVD或PVD顺应性地形成导电层如铝、铝合金、钨、铜、钛、钽、氮化钛、氮化钽、或类似物于上述结构上。
在图6的实施例中，第一图案化掩模610形成于第一导电层510上。第一图案化掩模610定义第一导电层510作为导电垫与重新分布线路的部分，将详述于下。第一图案化掩模610可为图案化光致抗蚀剂掩模、硬掩模、上述的组合、或类似物。在一实施例中，沉积次微米至数微米的光致抗蚀剂材料后，以光刻工艺图案化光致抗蚀剂材料以形成第一图案化掩模610。第一图案化掩模610亦可为复合层。
接着如图7所示，进行蚀刻工艺图案化第一导电层510，以形成第一导电单元710作为导电垫与重新分布线路。本领域技术人员应了解，左侧的两个第一导电单元710覆盖穿透基板通孔124，而右侧的第一导电单元710则未直接位于穿透基板通孔上。第一导电单元710可作为第一重新分布层，其中导电单元提供电性连接至穿透基板通孔，并提供重新分布线路。综上所述，位于穿透基板通孔124上的左侧两个第一导电单元710可延伸出或延伸入纸面，以提供特定应用不同的针脚输出组态，而不受限于穿透基板通孔124的位置。右侧的第一导电单元710是重新分布线路之一，可延伸出或延伸入纸面以连接至某一穿透基板通孔，且某一穿透基板通孔可为图示或非图示的穿透基板通孔。上述型态的针脚输出组态不同于穿透基板通孔的位置，这将使半导体元件的设计更具弹性。
上述蚀刻工艺可为干蚀刻或湿蚀刻。举例来说，一实施例的第一导电层510由铝形成，且蚀刻工艺可采用Cl2与BCl3。
在蚀刻工艺后剥除光致抗蚀剂的方法可为灰化工艺，如采用氧气的等离子体灰化工艺或其他剥除步骤。接着进行洁净步骤如湿式浸润于稀氢氟酸或有机化学品(如EKC或ST250)中，移除第一导电单元710与第一绝缘膜310表面上的任何污染物。
在图8的实施例中，第二绝缘膜810形成于半导体基板110的背面上。第二绝缘膜810是介电材料如SiN、氧化物、SiC、SiON、高分子、SOG、上述的组合、或类似物。第二绝缘膜810的形成方法可为旋转涂布法、印刷法、CVD工艺、或类似方法。第二绝缘膜810可由低温工艺形成，如小于250℃的PECVD工艺，以避免劣化元件之间的结合力并确保元件的机械强度。如图8所示的实施例，第二绝缘膜810的厚度需足以覆盖第一导电单元710。
第二绝缘膜810的形成工艺将决定是否进行后续的平坦化工艺。在特定实施例中，某些沉积方法如旋转涂布法可形成平坦化表面。但其他沉积方法如CVD工艺将形成共形层，这需要进行平坦化工艺如研磨或CMP工艺以提供图8所示的平坦表面。然而必需注意的是，若采用自我平坦化工艺如旋涂法形成实质上平坦表面的第二绝缘膜810，可省略额外的平坦化工艺如CMP。
在图9的实施例中，第二图案化掩模910形成于第二绝缘膜810上。第二图案化掩模910定义穿过第二绝缘膜810至第一导电单元710的接触物，将详述于下。第二图案化掩模910可为图案化光致抗蚀剂掩模、硬掩模、上述的组合、或类似物。在一实施例中，沉积次微米至数微米的光致抗蚀剂材料后，以光刻工艺图案化光致抗蚀剂材料以形成第二图案化掩模910。
接着如图10所示，进行蚀刻工艺工艺以图案化第二绝缘膜810，形成接触开口至第一导电单元710，以形成导电垫与重新分布线路。蚀刻工艺可为干蚀刻或湿蚀刻。在一实施例中，第二绝缘膜810由二氧化硅形成。蚀刻第二绝缘膜810的步骤可为干蚀刻，采用CF4、CHF3、CH2F2、C4F8、Ar、及/或O2。除了上述实施例外，亦可采用其他工艺或材料。
在蚀刻工艺后剥除光致抗蚀剂的方法可为灰化工艺，如采用氧气的等离子体灰化工艺或其他剥除步骤。接着进行洁净步骤如湿式浸润于稀氢氟酸或有机化学品(如EKC或ST250)中，移除第一导电单元710与第二绝缘膜810表面上的任何污染物。
如图11所示，第二导电层1110沉积于第二绝缘膜810与露出的第一导电单元710的表面上。在一实施例中，第二导电层1110可由沉积法如CVD或PVD顺应性地形成导电层如铝、铝合金、钨、铜、钛、钽、氮化钛、氮化钽、或类似物于上述结构上。
本领域技术人员应理解图11中的结构仅电性连接至右侧的第一导电单元710。在一实施例中，左侧的两个第一导电单元710可延伸出或延伸入纸面以耦合至分开的重新分布线路。相同地，右侧的第一导电单元710可电性连接至未图示的穿透基板通孔。然而第一导电单元可直接形成于穿透基板通孔上。
在图12的实施例中，第三图案化掩模1210形成于第二导电层1110上。第三图案化掩模可保护部分的第二导电层1110，以作为含有导电垫与重新分布线路的第二重新分布层，将详述于下。第三图案化掩模1210可为图案化光致抗蚀剂掩模、硬掩模、上述的复合层、或类似物。在一实施例中，光致抗蚀剂材料的沉积厚度为约次微米级至约数微米级，接着图案化光致抗蚀剂材料以形成第一图案化掩模1210。
之后如图13所示，进行蚀刻工艺以图案化第二导电层1110以形成第二导电单元1310，作为第二重新分布层中的导电垫与重新分布线路。蚀刻工艺可为干蚀刻或湿蚀刻。在蚀刻工艺后剥除光致抗蚀剂的方法可为灰化工艺，如采用氧气的等离子体灰化工艺或其他剥除步骤。接着进行洁净步骤如湿式浸润于稀氢氟酸或有机化学品(如EKC或ST250)中，移除第二导电单元1310与第二绝缘膜810表面上的任何污染物。
图13的结构中含有两个第二导电单元1310。左侧的第二导电单元710可延伸出或延伸入纸面，以电性连接至分开的第一导电单元710，而分开的第一导电单元710又电性连接至分开的穿透基板通孔124。
在图14的实施例中，第三绝缘膜1410是绝缘材料如SiN、氧化物、SiC、SiON、高分子、SOG、上述的组合、或类似物。第三绝缘膜1410的形成方法可为旋转涂布法、印刷法、CVD工艺、或类似方法。在一实施例中，第三绝缘膜1310可由低温工艺形成，如小于250℃的PECVD工艺，以避免劣化元件之间的结合力并确保元件的机械强度。在一实施例中，第三绝缘膜1410的厚度需足以覆盖第二导电单元1310。
第三绝缘膜1410的形成工艺将决定是否进行后续的平坦化工艺。在特定实施例中，某些沉积方法如旋转涂布法可形成平坦化表面。但其他沉积方法如CVD工艺将形成共形层，这需要进行平坦化工艺如研磨或CMP工艺以提供图14所示的平坦表面。然而必需注意的是，若采用自我平坦化工艺如旋涂法形成实质上平坦表面的第二绝缘膜1410，可省略额外的平坦化工艺如CMP。
在图15的实施例中，第四图案化掩模1510形成于第三绝缘膜1410上。第四图案化掩模1510可定义露出的第二导电单元1310的区域，接着在露出的第二导电单元上形成导电凸块的步骤将详述于下。第四图案化掩模1510可为图案化光致抗蚀剂掩模、硬掩模、上述的组合、或类似物。在一实施例中，沉积次微米至数微米厚的光致抗蚀剂材料后，图案化光致抗蚀剂材料以形成第四图案化掩模1510。
之后进行蚀刻工艺以图案化第三绝缘膜1410，露出部分的第二导电单元1310，以利后续导电凸块形成其上。蚀刻工艺可为干蚀刻或湿蚀刻。在蚀刻工艺后剥除光致抗蚀剂的方法可为灰化工艺，接着进行洁净步骤移除第二导电单元1310与第三绝缘膜1410表面上的任何污染物。
在图16的实施例中，形成连线单元1610于第二导电单元1310的露出部分上。连线单元1610可为任何合适导电材料如Cu、Ni、Sn、Au、Ag、或类似物，其形成方法可为任何合适方法如蒸镀法、电镀法、印刷法、喷涂法、柱形凸块、直接置换法、或类似方法。
最后，可进行任何合适的后端(BEOL)工艺以适用于特定应用。举例来说，可进行其他步骤如移除承载基板130、进行切割工艺以形成分开的裸片、晶片等级或裸片等级的堆叠工艺、或类似工艺。必需注意的是，上述实施例可应用于多种情况中。举例来说，可应用于裸片-裸片的接合组态、裸片-晶片的接合组态、或晶片-晶片的接合组态。
图17-图24是本发明另一实施例中，适用于三维集成电路或堆叠裸片组态的裸片的工艺剖示图，上述裸片具有多层内连线结构及/或重新分布层。此实施例与前述的实施例类似，差别在于采用导电的籽晶层而非单一导电材料层。
首先，第二种方法的起始工艺与前述图1-图4的工艺相同。接着如图17所示，顺应性地沉积第一籽晶层1710于第一绝缘膜310与穿透基板通孔124露出部分的表面上。第一籽晶层1710为薄层的导电材料，在后续工艺中可帮助形成较厚的层。在一实施例中，第一籽晶层1710可为沉积法如CVD或PVD所形成的导电薄层如Cu、Ti、Ta、TiN、TaN、或类似物。举例来说，以PVD工艺沉积Ti层以形成阻挡层，接着以PVD工艺沉积Cu层以形成籽晶层。
在图18的实施例中，第一图案化掩模1810形成于第一籽晶层1710上。第一图案化掩模1810可作为后续形成的导电垫与重新分布线路的模具。第一图案化掩模1810可为图案化光致抗蚀剂掩模、硬掩模、上述的组合、或类似物。在一实施例中，沉积次微米至数微米的光致抗蚀剂材料后，以光刻工艺图案化光致抗蚀剂材料以形成开口，如图18所示。
值得注意的是，图18的方形开口仅为举例。在其他实施例中，可采用锥形开口，其底部比顶部宽。在另一实施例中，可采用凹形开口，其顶部比底部宽。
之后如图19所示，形成第一导电单元1910于第一图案化掩模1810的开口中。第一导电单元1910可为金属如铜、钨、或其他导电金属，其形成方法可为电镀法、无电电镀法、或类似方法。在一实施例中，电镀法是将晶片浸入电镀溶液中。晶片表面电性连接至外部直流电源的负极，使晶片作为电镀工艺的阴极。电镀法的阳极为导电固体如铜阳极，亦浸入电镀溶液并接触外部直流电源的正极。铜阳极的原子将溶解于电镀溶液中，并电镀至晶片露出的导电区域，如第一图案化掩模1810的开口所露出的第一籽晶层1710。
在图20的实施例中，移除第一图案化掩模1810(见图18-图19)。在一实施例中，第一图案化掩模1810为光致抗蚀剂掩模，因此可采用等离子体灰化或湿式剥除法移除第一图案化掩模1810。一种适合的灰化工艺为采用氧气的等离子体灰化。
如图20所示，移除露出的第一籽晶层1710，其方法可为湿式蚀刻工艺。接着可视情况需要进行洁净工艺，比如将上述结构浸润于稀氢氟酸或有机化学品(如EKC或ST250)的湿式法，以洁净晶片并移除残留的光致抗蚀剂材料与籽晶层。
在图21中，形成第二绝缘膜810于图20的结构上，并图案化第二绝缘膜810。第二绝缘膜810的材料及工艺与前述图8-图10的第二绝缘膜810类似。
在图21的实施例中，亦形成第二籽晶层2110。第二籽晶层2110的材料及工艺与图17所示的第一籽晶层1710类似。
图22的实施例中，第二图案化掩模2210形成于第二籽晶层2110上。第二图案化掩模2210可作为后续形成的导电垫与重新分布线路的模具，与图18的第一图案化掩模1810形态类似。第二图案化掩模2210可为图案化光致抗蚀剂掩模、硬掩模、上述的组合、或类似物。在一实施例中，沉积次微米至数微米的光致抗蚀剂材料后，以光刻工艺图案化光致抗蚀剂材料以形成开口，如图22所示。
之后如图23所示，形成第二导电单元2310于第二图案化掩模2210的开口中。第二导电单元2310可为任合合适的导电材料，例如金属如铜、钨、或其他导电金属，其形成方法可为电镀法、无电电镀法、或类似方法。在一实施例中，第二导电单元2310的形成方法及材料与图19所示的第一导电单元1910类似。
如图24所示，移除第二图案化掩模2210与残留的第二籽晶层2110，其移除方法与相对材料与第20图对应的内容类似。
接着可采用与图14-图16类似的工艺与材料，形成并图案化第三绝缘膜1410及连线单元1610如图25所示，且之后可再进行其他的后端工艺。
图26-图35是本发明又一实施例中，适用于三维集成电路或堆叠裸片组态的裸片的工艺剖示图，上述裸片具有多层内连线结构及/或重新分布层。此实施例的起始步骤与前述的图1-图2所示的步骤类似。接着如图26所示，形成第一绝缘膜2610。第一绝缘膜2610是共形膜，其工艺与材料与前述图3中的第一绝缘膜310类似，除了图3的第一绝缘膜310的厚度大于穿透基板通孔124的凸出高度以外(图26的第一绝缘膜2610的厚度小于穿透基板通孔124的凸出高度)。举例来说，穿透基板通孔124自半导体基板110背面凸出约2微米至约3微米，而第一绝缘膜2610的厚度为约1微米至约1.5微米。
如图27所示，接着形成第一掩模层2710于图26的结构中的第一绝缘膜2610上。第一掩模层2710可为光致抗蚀剂材料，其工艺与材料可与图6所示的第一图案化掩模610类似。
接着如图28所示，进行回蚀刻工艺以薄化第一掩模层2710，并露出位于穿透基板通孔124上的第一绝缘膜2610。在一实施例中，第一掩模层2710采用光致抗蚀剂材料，而对应的回蚀刻工艺可采用氧气等离子体的干蚀刻工艺。
当第一掩模层2710露出穿透基板通孔124后，将移除位于穿透基板通孔124上的第一绝缘膜2610，以露出衬垫物126如图29所示。在一实施例中，第一绝缘膜2610的组成为氧化硅，而使第一绝缘膜2610凹化的工艺可为湿式的氢氟酸或干式的CF4、CHF3、CH2F2、C4F8、Ar、及/或O2。除了上述工艺与材料外，亦可采用其他工艺与材料。
如图30所示，在蚀刻工艺后可剥除光致抗蚀剂，其方法可为灰化工艺如采用氧气的等离子体灰化工艺或其他合适的剥除工艺。
在剥除光致抗蚀剂后，可移除覆盖穿透基板通孔124的衬垫物126以露出穿透基板通孔124，如图31所示。在一实施例中，衬垫物126可由PECVD工艺形成，且可由采用CF4、CHF3、CH2F2、C4F8、Ar、及/或O2的干蚀刻移除，均视衬垫物的材料种类而定。除了上述工艺与材料外，亦可采用其他工艺与材料。
如图32所示，第一导电层3210沉积于第一绝缘膜2610与露出的穿透基板通孔124的表面上。在一实施例中，第一导电层3210可由沉积法如CVD或PVD顺应性地形成导电层如铝、铝合金、钨、铜、钛、钽、氮化钛、氮化钽、或类似物于上述结构上。
在图33的实施例中，第一图案化掩模3310形成于第一导电层3210上。第一图案化掩模3310将保护第一导电层3210作为导电垫与重新分布线路的部分，将详述于下。第一图案化掩模3310可为图案化光致抗蚀剂掩模、硬掩模、上述的组合、或类似物。在一实施例中，沉积次微米至数微米的光致抗蚀剂材料后，以光刻工艺图案化光致抗蚀剂材料以形成第一图案化掩模3310。第一图案化掩模3310亦可为复合层。
接着如图34所示，进行蚀刻工艺图案化第一导电层3210，以形成第一导电单元3410作为导电垫与重新分布线路。本领域技术人员应了解，左侧的两个第一导电单元3410覆盖穿透基板通孔124，而右侧的第一导电单元3410则未直接位于穿透基板通孔上。第一导电单元710可作为第一重新分布层，其中导电单元提供电性连接至穿透基板通孔，并提供重新分布线路。综上所述，位于穿透基板通孔124上的左侧两个第一导电单元3410可延伸出或延伸入纸面，以符合特定应用。右侧的第一导电单元710是重新分布线路之一，可延伸出或延伸入纸面以连接至某一穿透基板通孔。上述型态的针脚输出组态不同于穿透基板通孔的位置，这将使半导体元件的设计更具弹性。
上述蚀刻工艺可为干蚀刻或湿蚀刻。在蚀刻工艺后剥除光致抗蚀剂的方法可为灰化工艺，如采用氧气的等离子体灰化工艺或其他剥除步骤。接着进行洁净步骤如湿式浸润于稀氢氟酸或有机化学品(如EKC或ST250)中，移除第一导电单元3410与第一绝缘膜2610表面上的任何污染物。
如图35所示，在图34的结构上形成第二绝缘膜810、第二导电单元1310、第三绝缘膜1410、及连线单元1610，其形成方法可与第8-16图对应元件的形成方法类似。
最后，可进行任何合适的后端工艺以适用于特定应用。举例来说，可进行其他步骤如移除承载基板130、进行切割工艺以形成分开的裸片、晶片等级或裸片等级的堆叠工艺、或类似工艺。必需注意的是，上述实施例可应用于多种情况中。举例来说，可应用于裸片-裸片的接合组态、裸片-晶片的接合组态、或晶片-晶片的接合组态。
图36-图40是本发明又一实施例中，适用于三维集成电路或堆叠裸片组态的裸片的工艺剖示图，上述裸片具有多层内连线结构及/或重新分布层。此实施例与图26-图35所示的实施例类似，差别在于采用导电的籽晶层而非单一导电材料层。
综上所述，此实施例的起始步骤与图1-图2所示的步骤类似，接着进行图26-图31所示的步骤。接着如图36所示，顺应性地沉积第一籽晶层3610于第一绝缘膜2610与穿透基板通孔124露出部分的表面上。第一籽晶层3610为薄层的导电材料，在后续工艺中可帮助形成较厚的层。在一实施例中，第一籽晶层3610可为沉积法如CVD或PVD所形成的导电薄层如Cu、Ti、Ta、TiN、TaN、或类似物。举例来说，以PVD工艺沉积Ti层以形成阻挡层，接着以PVD工艺沉积Cu层以形成籽晶层。
在图37的实施例中，第一图案化掩模3710形成于第一籽晶层3610上。第一图案化掩模3710可作为后续形成的导电垫与重新分布线路的模具。第一图案化掩模3710可为图案化光致抗蚀剂掩模、硬掩模、上述的组合、或类似物。在一实施例中，沉积次微米至数微米的光致抗蚀剂材料后，以光刻工艺图案化光致抗蚀剂材料以形成开口，如图37所示。
必需注意的是，图37的方形开口仅为举例。在其他实施例中，可采用锥形开口，其底部比顶部宽。在另一实施例中，可采用凹形开口，其顶部比底部宽。
之后如图38所示，形成第一导电单元3810于第一图案化掩模3710的开口中。第一导电单元3810可为金属如铜、钨、或其他导电金属，其形成方法可为电镀法、无电电镀法、或类似方法。在一实施例中，电镀工艺可类似于图19所对应的内容。
在图39的实施例中，移除第一图案化掩模3710(见图37-图38)。在一实施例中，第一图案化掩模3710为光致抗蚀剂掩模，因此可采用等离子体灰化或湿式剥除法移除第一图案化掩模3710。一种适合的灰化工艺为采用氧气的等离子体灰化。
如图39所示，移除露出的第一籽晶层3610，其方法可为湿式蚀刻工艺。
如图40所示，在图39的结构上形成第二绝缘膜810、第二导电单元1310、第三绝缘膜1410、及连线单元1610，其形成方法可与第8-16图对应元件的形成方法类似。
最后，可进行任何合适的后端工艺以适用于特定应用。举例来说，可进行其他步骤如移除承载基板130、进行切割工艺以形成分开的裸片、晶片等级或裸片等级的堆叠工艺、或类似工艺。必需注意的是，上述实施例可应用于多种情况中。举例来说，可应用于裸片-裸片的接合组态、裸片-晶片的接合组态、或晶片-晶片的接合组态。
本领域技术人员应了解上述重新分布层的导电元件其形成方法为非镶嵌工艺。如此一来，在采用低温介电膜的情况下，即使不采用平坦化工艺如CMP工艺也可使介电膜具有不错的平坦性。与其他采用CMP技术的方法相较，上述方法亦可避免或减少扩散的问题。
虽然本发明已以数个优选实施例公开如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。

Claims (8)

1.一种半导体元件，包括：
一第一基板；
多个穿透基板通孔穿过该第一基板，且所述多个穿透基板通孔自该第一基板的背面凸起；
一第一绝缘膜位于该第一基板的背面上及所述多个穿透基板通孔之间，且该第一绝缘膜的上表面低于凸起的所述多个穿透基板通孔；
一第一重新分布层延伸于该第一绝缘膜上，该第一重新分布层具有多个第一导电单元，且所述多个第一导电单元分别电性接触每一穿透基板通孔并延伸于该第一绝缘膜上；
一第二绝缘膜位于该第一重新分布层上；以及
一第二重新分布层延伸于该第二绝缘膜上，该第二重新分布层具有多个第二导电单元，且所述多个第二导电单元分别电性接触每一第一导电单元并延伸于该第二绝缘膜上。
2.如权利要求1所述的半导体元件，其中该第一导电单元包括一籽晶层位于所述多个穿透基板通孔上，以及一导电层位于该籽晶层上。
3.如权利要求1所述的半导体元件，其中所述多个穿透硅通孔延伸出该第一绝缘膜。
4.一种形成半导体元件的方法，包括：
提供一第一基板，具有多个穿透基板通孔自该第一基板的第一面穿入该第一基板中；
自该第一基板的第二面露出所述多个穿透基板通孔；
沿着该第一基板的第二面形成一第一绝缘膜，且该第一绝缘膜仍露出所述多个穿透基板通孔；
形成一第一导电单元于所述多个穿透基板通孔上，且该第一导电单元延伸于该第一绝缘膜的上表面上；
形成一第二绝缘膜于该第一绝缘膜上及该第一导电单元上；以及
形成一第二导电单元电性耦合至该第一导电单元，且该第二导电单元延伸于该第二绝缘膜的上表面上，
其中自该第一基板的第二面露出所述多个穿透基板通孔的步骤，包括蚀刻比所述多个穿透基板通孔表面低的第一基板，使所述多个穿透基板通孔凸出该第一基板。
5.如权利要求4所述的形成半导体元件的方法，其中形成该第一导电单元的步骤包括：
形成一籽晶层于该第一绝缘膜上及所述多个穿透基板通孔上；
形成一图案化掩模于该籽晶层上，且该图案化掩模露出部分该籽晶层；
形成一金属垫于露出部分的该籽晶层上；
移除该图案化掩模层；以及
移除未被该金属垫覆盖的部分籽晶层。
6.如权利要求4所述的形成半导体元件的方法，其中形成该第二绝缘膜的步骤包括一自平坦技术。
7.一种形成半导体元件的方法，包括：
提供一基板，该基板具有一或多个穿透基板通孔自该基板的电路面延伸至该基板的背面；
形成一重新分布层，包括：
形成一第一绝缘膜于该基板的背面上；
露出至少部分上述一或多个穿透基板通孔；以及
形成多个第一导电单元分别电性耦合至上述一或多个穿透基板通孔，且所述多个第一导电单元延伸于该第一绝缘膜的上表面上；以及
形成一或多个额外重新分布层，包括：
形成一额外绝缘膜于该第一绝缘膜上；
露出至少部分较下层的导电单元；以及
形成额外导电单元分别电性耦合至较下层的导电单元，且所述多个额外导电单元延伸于该额外绝缘膜的上表面上，
其中露出所述多个穿透基板通孔的步骤包括让该基板的背面凹入，使所述多个穿透基板通孔自该基板的背面凸起。
8.如权利要求7所述的形成半导体元件的方法，其中形成所述多个第一导电单元的步骤包括：
形成一籽晶层于上述一或多个穿透基板通孔上；
形成一图案化掩模层于该籽晶层上，该图案化掩模层露出部分该籽晶层；
形成一导电垫于露出部分的该籽晶层上；以及
移除该图案化掩模层。
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