CN112530816B - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
- Publication number
- CN112530816B CN112530816B CN202010042238.6A CN202010042238A CN112530816B CN 112530816 B CN112530816 B CN 112530816B CN 202010042238 A CN202010042238 A CN 202010042238A CN 112530816 B CN112530816 B CN 112530816B
- Authority
- CN
- China
- Prior art keywords
- resin film
- semiconductor
- nonconductive resin
- semiconductor device
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 219
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000011347 resin Substances 0.000 claims abstract description 49
- 229920005989 resin Polymers 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000005520 cutting process Methods 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims description 17
- 230000001678 irradiating effect Effects 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 4
- 229920001169 thermoplastic Polymers 0.000 description 3
- 239000004416 thermosoftening plastic Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
- H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/278—Post-treatment of the layer connector
- H01L2224/2783—Reworking, e.g. shaping
- H01L2224/2784—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29006—Layer connector larger than the underlying bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29016—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29016—Shape in side view
- H01L2224/29018—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
- H01L2224/32058—Shape in side view being non uniform along the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
- H01L2224/32059—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83862—Heat curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Laser Beam Processing (AREA)
Abstract
根据一个实施方式,实施方式的半导体装置的制造方法具备如下工序:将具备分别具有柱状电极的多个芯片区域及切割区域的半导体晶圆沿着切割区域分割,将多个芯片区域单片化;在经单片化的多个半导体芯片上贴附非导电性树脂膜,并且将非导电性树脂膜的一部分填充到相邻的多个半导体芯片间的间隙;在填充到间隙内的非导电性树脂膜形成具有比间隙的宽度窄的宽度的槽;以及将具有非导电性树脂膜的多个半导体芯片依次拾取并安装在衬底。
Description
相关申请的引用
本申请案以2019年09月17日申请的先行的日本专利申请案第2019-168888号的优先权的利益为基础,且追求其利益,其内容整体通过引用包含于本文中。
技术领域
此处所揭示的实施方式涉及一种半导体装置的制造方法。
背景技术
作为将半导体芯片安装在电路衬底等衬底的方法,例如,已知有使用热塑性的非导电性树脂膜(Non Conductive Film:NCF)的安装方法。在使用NCF的安装方法中,首先,在将NCF贴附于经单片化的多个半导体芯片的电极形成面上之后,将NFC与经单片化的多个半导体芯片对应地切断。接着,将具有经单片化的NFC的半导体芯片隔着NFC而接合于衬底上隔着,将半导体芯片的电极与衬底的电极连接。在这种使用NCF的安装方法中,有无法获得充分的半导体芯片的接合强度的担心,例如,由于施加热时的衬底的收缩而容易产生半导体芯片的剥离。
发明内容
实施方式的半导体装置的制造方法具备如下工序:将具备分别具有柱状电极的多个芯片区域、及划分所述多个芯片区域的切割区域的半导体晶圆沿着所述切割区域分割,将所述多个芯片区域单片化而形成多个半导体芯片;在所述经单片化的多个半导体芯片上,从所述半导体晶圆的第1表面侧贴附非导电性树脂膜,并且将所述非导电性树脂膜的一部分填充到相邻的所述多个半导体芯片间的间隙;在填充到所述间隙内的所述非导电性树脂膜,使所述非导电性树脂膜残留在所述经单片化的半导体芯片的侧面,且形成具有比所述间隙的宽度窄的宽度的槽,由此根据所述多个半导体芯片分割所述非导电性树脂膜;以及依次拾取具有所述经分割的非导电性树脂膜的所述多个半导体芯片,并将所述拾取的所述半导体芯片的所述柱状电极接合于衬底的电极,且隔着所述非导电性树脂膜而将所述半导体芯片安装在所述衬底。
附图说明
图1A至图1E是表示第1实施方式的半导体装置的制造方法的剖视图。
图2A至图2C是表示第1实施方式的半导体装置的制造方法的剖视图。
图3A及图3B是表示图1A至图1E所示的半导体装置的制造方法中的非导电性膜的贴附工序及填充工序的剖视图。
图4是表示图2A至图2C所示的半导体装置的制造方法中的非导电性膜的分割工序的第1例的剖视图。
图5A及图5B是表示图2A至图2C所示的半导体装置的制造方法中的非导电性膜的分割工序的第2例的剖视图。
图6是表示图2A至图2C所示的半导体装置的制造方法中的非导电性膜的分割工序的第3例的剖视图。
图7是表示由实施方式的半导体装置的制造方法获得的半导体装置的第1例的剖视图。
图8是表示由实施方式的半导体装置的制造方法获得的半导体装置的第2例的剖视图。
图9是表示由实施方式的半导体装置的制造方法获得的半导体装置的第3例的剖视图。
图10A至图10C是表示第2实施方式的半导体装置的制造方法的剖视图。
图11A至图11D是表示第2实施方式的半导体装置的制造方法的剖视图。
图12是表示使用由实施方式的半导体装置的制造方法获得的半导体装置的半导体存储装置的剖视图。
具体实施方式
以下,参照附图对实施方式的半导体装置的制造方法进行说明。此外,在各实施方式中,存在对实质上相同的构成部位标注相同的符号,而将其说明省略一部分的情况。附图是示意性的图,存在厚度与平面尺寸的关系、各部的厚度的比率等与实物不同的情况。存在表示说明中的上下等方向的用语在无特别明记的情况下表示以下述半导体晶圆的柱状电极的形成面为上时的相对性的方向,与以重力加速度方向为基准的现实的方向不同的情况。
(第1实施方式)
图1A至图1E及图2A至图2C是表示第1实施方式的半导体装置的制造方法的图。图1A至图1E是表示从半导体晶圆的准备工序到非导电性膜的贴附及填充工序为止的剖视图,图2A至图2C是表示从非导电性膜的分割工序到半导体装置的安装工序为止的剖视图。
首先,如图1A所示,准备半导体晶圆1。半导体晶圆1具有分别具有柱状电极(凸块电极)2的多个芯片区域X、及划分这些多个芯片区域X的切割区域D。另外,未图示的半导体元件设置在形成有柱状电极2的面。在这种半导体晶圆1的具有柱状电极2的第1表面1a上贴附表面保护带3。接着,将半导体晶圆1的与第1表面1a相反侧的第2表面1b研削到与所制造的半导体芯片对应的厚度为止之后,将表面保护带3剥离(图1B)。也存在表面保护带3的剥离工序在下述所示的切割带4的贴附工序后实施的情况。
接下来,如图1C所示,在半导体晶圆1的被研削的第2表面1b贴附切割带4。虽然省略了图示,但切割带4的外周部由晶圆环支撑。接着,如图1D所示,在半导体晶圆1从第1表面1a侧沿着切割区域D形成第1槽5,而将半导体晶圆1分割。第1槽5例如利用使用像金刚石刀片一样的切割刀片6的切割工序来形成。此时,切割工序以将半导体晶圆1切断,并且仅将切割带4的厚度方向的一部分切断的半切状态的方式实施。通过利用第1槽5在相邻的多个芯片区域X间形成间隙,来将多个芯片区域X单片化而形成多个半导体芯片7。具有经单片化的半导体芯片7的半导体晶圆1的整体形状由切割带4来维持。第1槽5由多个芯片区域X分别成为所期望的半导体芯片的形状的第1宽度(间隙)形成。
接下来,如图1E所示,在经单片化的多个半导体芯片7上,从半导体晶圆1的第1表面1a侧贴附热塑性的非导电性树脂膜(NCF)8。此时,将NCF8的一部分填充到第1槽5内。NCF8向第1槽5内的填充工序能够应用各种方法。例如,能够应用图3A及图3B所示的减压下的贴附工序与大气压下的填充工序。也就是说,如图3A所示,减压下在多个半导体芯片7上以60℃左右的加热条件贴附NCF8。接着,如图3B所示,通过将减压下贴附的NCF8大气开放,来将NCF8的一部分填充到第1槽5内。
此时,除了NCF8的大气开放以外,也可一并使用NCF8的加热,例如向相当于第1槽5的部分的局部加热。局部加热例如使用热风或激光等来实施。局部加热优选为从中心朝向外侧实施以使第1槽5内不会残存孔隙等。另外,也可使用加热器或烘箱等,将NCF8整体加热。在应用整体加热的情况下,也有效的是一边加压一边加热。通过一并使用NCF8的加热,能够提高NCF8向第1槽5内的填充性。进而,也存在如下情况:根据NCF8的材质等,不应用NCF8的减压下的贴附工序,而仅利用NCF8的加热(局部加热或整体加热)将NCF8填充到第1槽5内。
接下来,如图2A所示,在填充到第1槽5内的NCF8形成第2槽9,并根据多个半导体芯片7来分割NCF8。此时,第2槽9以其宽度比第1槽5的宽度窄的方式形成。由此,在隔着第1槽5而配置的2个半导体芯片7的侧面分别残存NCF8。如下所述,残存在半导体芯片7的侧面的NCF8有助于在将半导体芯片7安装到衬底时覆盖半导体芯片7的侧面的树脂膜即内圆角(fillet)的形成,由此能够提高半导体芯片7的安装强度。第2槽9的宽度优选为以在2个半导体芯片7的侧面分别残存5μm以上的NCF8的方式调整。例如,在第1槽5的宽度为35~40μm左右的情况下,为了在2个半导体芯片7的侧面分别残存5μm以上的NCF8,第2槽9的宽度优选设为25~30μm左右,另外,当使10μm左右的NCF8残存在2个半导体芯片7的侧面时,第2槽9的宽度优选设为15~20μm左右。
第2槽9的形成工序能够应用各种方法。例如,如图4所示,使用具有比第1槽5的形成所使用的第1切割刀片6的宽度窄的宽度的第2切割刀片10,将填充到第1槽5内的NCF8切断。由此,能够在填充到第1槽5内的NCF8形成第2槽9。另外,如图5A所示,对形成在第1槽5的NCF8照射激光光11而进行切断。接下来,如图5B所示,通过将贴附有多个半导体芯片7的切割带4在其面方向扩张(延伸)来形成第2槽9。在激光切割中有可能会残存NCF8局部地固着的部分,因此优选实施切割带4的扩张工序。
如图6所示,也存在根据切割带4的材质等,省去激光切割工序,能够仅利用扩张工序形成第2槽9的情况。在该情况下,将减压下贴附的NCF8大气开放,并将NCF8的一部分填充到第1槽5内之后,切割带4在其面方向扩张(延伸),将填充到第1槽5内的NCF8分割而形成第2槽9。但是,由于仅利用扩张工序而有在第2槽9的形成位置产生不均,且残存在半导体芯片7的侧面的NCF8的厚度不均的担心,所以优选为一并使用激光切割工序。扩张工序也可在刀片切割后一并使用。
通过在填充到第1槽5内的NCF8形成第2槽9,并根据多个半导体芯片7分割NCF8,来形成具有经单片化的NCF8的半导体芯片7。如图2B所示从切割带4依次拾取这种具有NCF8的半导体芯片7。接下来,使从切割带4拾取的具有NCF8的半导体芯片7在安装工序的中途上下反转之后,如图2C所示,安装在具有电极12的衬底13而制作半导体装置15。半导体芯片7将其柱状电极2连接于衬底13的电极12,且安装在衬底13,由此制作半导体装置15。
半导体芯片7的安装例如以如下方式实施。首先,利用未图示的安装工具保持半导体芯片7的第2面1b,以半导体芯片7的柱状电极2与衬底13的电极12接触的方式,将半导体芯片7压抵到衬底13。在该状态下,通过一边加热一边加压,来将柱状电极2与电极12接合,且将半导体芯片7安装在衬底13。NCF8作为半导体芯片7向衬底13的粘着剂发挥功能,并且作为半导体芯片7与衬底13之间的底部填充材发挥功能。NCF8利用安装时的加热而软化,在之后的冷却工序中固化,作为粘着剂及底部填充材发挥功能。此时,由于在半导体芯片7的侧面也存在NCF8,所以在安装在衬底13的半导体芯片7的侧面形成由NCF8形成的内圆角14。因此,利用大型化的内圆角14能够提高半导体芯片7相对于衬底13的安装强度或应力缓和效果等。
此处,当在半导体芯片7的侧面不存在NCF8时,也存在如下情况:在安装时的加压工序中,半导体芯片7与衬底13之间多余地存在的NCF8爬上半导体芯片7的侧面,由此在半导体芯片7的侧面形成由NCF8形成的内圆角。然而,由于其量微小,所以无法形成充分的内圆角。针对该点,在实施方式的制造方法中,由于在半导体芯片7的侧面也存在NCF8,所以该侧面的NCF8促进内圆角14向半导体芯片7的侧面的形成,并且有助于内圆角14的大型化。也就是说,在安装在衬底13的半导体芯片7的侧面,能够由充分的量的NCF8形成大型的内圆角14。进而,能够利用内圆角14保护半导体芯片7的侧面。内圆角14由于提高半导体芯片7相对于衬底13的接合强度,并且提高应力缓和效果,所以,例如当施加热时在衬底13产生收缩的情况下,也能够抑制半导体芯片7的剥离。因此,能够提供可靠性或耐热性等优异的半导体装置1。
在由实施方式的制造方法获得的半导体装置15中,由于半导体芯片7的侧面的NCF8存在于第1槽5内,所以如图7所示,由NCF8形成的内圆角14的上部突出到半导体芯片7的上方。可以是具有这种形状的内圆角14,但通过对半导体芯片7的安装工具进行设计而能够获得具有各种形状的内圆角14的半导体装置15。例如,通过利用大于半导体芯片7的平面形状的安装工具保持半导体芯片7并压抵到衬底13,如图8所示,能够使由NCF8形成的内圆角14的上表面与半导体芯片7的背面为同一面。当在半导体芯片7上搭载其它半导体装置等的情况下,具有如图8所示的形状的内圆角14是有效的。
在利用小于半导体芯片7的平面形状的安装工具保持半导体芯片7并压抵到衬底13的情况下,如图9所示,能够形成为向半导体芯片7的上方突出的内圆角14的上部因安装时的加热而覆盖半导体芯片7的背面的外周侧的一部分的形状。具有如图9所示的形状的内圆角14由于使半导体芯片7相对于衬底13的接合强度更进一步提高,所以能够更加提高半导体装置1的可靠性或耐热性等。内圆角14的形状能够根据半导体装置15的使用用途或要求的特性来选择。
(第2实施方式)
图10A至图10C及图11A至图11D是表示第2实施方式的半导体装置的制造方法的图,且表示了在半导体晶圆的分割工序应用隐形切割的半导体装置的制造方法。图10A至图10C是表示从半导体晶圆的准备工序到半导体晶圆的分割工序的剖视图,图11A至图11D是表示从非导电性膜的贴附及填充工序到半导体装置的安装工序的剖视图。
首先,如图10A所示,准备半导体晶圆1。与第1实施方式同样地,半导体晶圆1具有分别具有柱状电极(凸块电极)2的多个芯片区域X、及划分这些多个芯片区域X的切割区域D。在这种半导体晶圆1的具有柱状电极2的第1表面1a上贴附表面保护带3。接着,从与第1表面1a相反侧的第2表面1b研削之前的半导体晶圆1的第2表面1b侧,沿着切割区域D,将隐形切割用的激光光21照射到半导体晶圆1。
半导体晶圆1的隐形切割具有如下工序:将激光光21聚光于半导体晶圆1的内部,形成成为半导体晶圆1的分割的起点的改质层22;以及对形成有改质层22的半导体晶圆1施加外力,将半导体晶圆1分割为包括多个芯片区域X的半导体芯片。图10A表示了利用激光光21的改质层22的形成工序。改质层22包含分割用的晶圆材质的改质区域及在半导体晶圆1的厚度方向延伸的龟裂等,通过之后的外力的施加工序以改质层22为起点将半导体晶圆1分割为多个半导体芯片。
接下来,如图10B所示,将形成有改质层22的半导体晶圆1的第2表面1b研削到与所制造的半导体芯片对应的厚度为止之后,剥离表面保护带3。接着,在半导体晶圆1的经研削的第2表面1b贴附包括树脂带的切割带4。如图10C所示,通过将贴附在形成有改质层22的半导体晶圆1的第2表面1b的切割带(树脂带)4在其面方向扩张(延伸),以改质层22为起点来分割半导体晶圆1。基于改质层22的形成与切割带4的扩张,在相邻的多个芯片区域X间形成间隙G,由此将多个芯片区域X单片化而形成多个半导体芯片7。具有经单片化的半导体芯片7的半导体晶圆1的整体形状由切割带4来维持。
接下来,如图11A所示,在经单片化的多个半导体芯片7上,从半导体晶圆1的第1表面1a侧贴附热塑性的非导电性树脂膜(NCF)8。此时,将NCF8的一部分填充到相邻的多个半导体芯片7间的间隙G内。NCF8向间隙G内的填充工序与第1实施方式同样地实施。例如,如图3A及图3B所示,能够应用减压下的贴附工序与大气压下的填充工序。此时,除了NCF8的大气开放以外,也可一并使用NCF8的加热,例如向相当于间隙G的部分的局部加热。另外,也可使用加热器或烘箱等,将NCF8整体加热。NCF8向间隙G内的填充工序能够与第1实施方式同样地实施。
接下来,如图11B所示,在填充到间隙G内的NCF8形成槽23,根据多个半导体芯片7分割NCF8。此时,槽23以其宽度比间隙G的宽度窄的方式形成。由此,在隔着间隙G配置的2个半导体芯片7的侧面分别残存NCF8。如下所述,残存在半导体芯片7的侧面的NCF8有助于将半导体芯片7安装在衬底时内圆角的形成,由此能够提高半导体芯片7的安装强度。槽23的宽度与第1实施方式的第2槽9同样地,优选为以在2个半导体芯片7的侧面分别残存5μm以上的NCF8的方式调整。
槽23的形成工序与第1实施方式的第2槽9的形成工序同样地实施。例如,如图4所示,使用具有比间隙G的宽度窄的宽度的切割刀片10,来切断填充到间隙G内的NCF8。由此,能够在填充到间隙G内的NCF8形成槽23。另外,如图5A及图5B所示,对形成在间隙G内的NCF8照射激光光11而切断之后,通过将切割带4在其面方向扩张来形成槽23。如图6所示,也存在根据切割带4的材质等,而省去激光切割工序,仅利用扩张工序形成槽23的情况。
通过在填充到间隙G内的NCF8形成槽23,并根据多个半导体芯片7分割NCF8,来形成具有经单片化的NCF8的半导体芯片7。如图11C所示,从切割带4依次拾取这种具有NCF8的半导体芯片7。接下来,使从切割带4拾取的具有NCF8的半导体芯片7在安装工序的中途上下反转之后,如图11D所示,安装在具有电极12的衬底13制作半导体装置15。半导体芯片7将其柱状电极2连接于衬底13的电极12,且安装于衬底13,由此制作半导体装置15。根据应用隐形切割而形成的半导体芯片7,如图11C及图11D所示,能够抑制NCF8从半导体衬底1的侧面突出。因此,能够抑制拾取具有NCF8的半导体芯片7时的吸附错误等。
(半导体装置)
利用上述第1及第2实施方式的制造方法制作的半导体装置15既可直接利用,另外也可用作其它半导体装置的一部分。图12是表示使半导体装置15进一步功能化的半导体装置,例如用作半导体存储装置的一部分的例的图。图12所示的半导体存储装置31具有设置在衬底32上的半导体装置15。在半导体装置15中,半导体芯片7的电极2与衬底32的电极33连接,在该状态下安装在衬底32。半导体芯片7例如作为控制器芯片发挥功能。在半导体装置15的周围配置着间隔件34,例如硅间隔件。间隔件34利用DAF(Die Attach Film,芯片粘结膜)35粘着在衬底32。
在半导体芯片7及间隔件34上,配置有第1存储器芯片36及第2存储器芯片37。第1存储器芯片36利用DAF35粘着在半导体芯片7及间隔件34。第2存储器芯片37利用DAF35粘着在第1存储器芯片36。第2存储器芯片37以第1存储器芯片36的电极38露出的方式,阶梯状地积层在第1存储器芯片36上。第2存储器芯片37的电极39与第1存储器芯片36的电极38利用接合线40电连接,第1存储器芯片36的电极38与衬底32的电极41利用接合线40电连接。在衬底31上,以将各构成要素密封的方式形成着模具树脂42。这种半导体存储装置31中的控制器芯片(7)的安装中有效地利用实施方式的半导体装置的制造方法。
此外,对本发明的几个实施方式进行了说明,但这些实施方式是作为示例而提出的,并不意图限定发明的范围。这些实施方式能以其它各种方式实施,在不脱离发明的主旨的范围内,能够进行各种省略、置换、变更。这些实施方式或其变化包含在发明的范围或主旨中,同时包含在权利要求书所记载的发明及其均等的范围中。
Claims (12)
1.一种半导体装置的制造方法,具备如下工序:
将具备分别具有柱状电极的多个芯片区域、及划分所述多个芯片区域的切割区域的半导体晶圆沿着所述切割区域分割,将所述多个芯片区域单片化而形成多个半导体芯片;
在所述经单片化的多个半导体芯片上,从所述半导体晶圆的具有所述柱状电极的第1表面侧贴附非导电性树脂膜,并且将所述非导电性树脂膜的一部分填充到相邻的所述多个半导体芯片间的间隙;
在填充到所述间隙内的所述非导电性树脂膜,使所述非导电性树脂膜残留在所述经单片化的半导体芯片的侧面,且形成具有比所述间隙的宽度窄的宽度的槽,由此根据所述多个半导体芯片分割所述非导电性树脂膜;以及
以残留在所述半导体芯片的侧面的所述非导电性树脂膜的上部突出到所述半导体芯片的与具有所述柱状电极的表面相对的表面的上方的状态,依次拾取具有所述经分割的非导电性树脂膜的所述多个半导体芯片,将所述拾取的所述半导体芯片的所述柱状电极接合于衬底的电极,且隔着所述非导电性树脂膜而将所述半导体芯片安装在所述衬底。
2.根据权利要求1所述的半导体装置的制造方法,其中所述非导电性树脂膜的贴附及填充工序具备如下工序:减压下将所述非导电性树脂膜贴附在所述多个半导体芯片;以及将贴附有所述非导电性树脂膜的所述多个半导体芯片大气开放,并将所述非导电性树脂膜的一部分填充到所述间隙内。
3.根据权利要求2所述的半导体装置的制造方法,其中所述非导电性树脂膜的贴附及填充工序进而具备将所述大气开放的所述非导电性树脂膜的至少相当于所述间隙的部分加热的工序。
4.根据权利要求1所述的半导体装置的制造方法,其中所述非导电性树脂膜的贴附及填充工序具备如下工序:将所述非导电性树脂膜贴附在所述多个半导体芯片;以及
将贴附在所述多个半导体芯片的所述非导电性树脂膜的至少相当于所述间隙的部分加热,并将所述非导电性树脂膜的一部分填充到所述间隙内。
5.根据权利要求1所述的半导体装置的制造方法,其中所述非导电性树脂膜的分割工序具备利用具有比所述间隙的宽度窄的宽度的刀片将填充到所述间隙内的所述非导电性树脂膜切断的工序。
6.根据权利要求5所述的半导体装置的制造方法,其中所述非导电性树脂膜的分割工序进而具备将利用所述刀片切断的所述非导电性树脂膜在其面方向延伸的工序。
7.根据权利要求1所述的半导体装置的制造方法,其中所述非导电性树脂膜的分割工序具备对填充到所述间隙内的所述非导电性树脂膜照射激光光而熔融断开的工序。
8.根据权利要求7所述的半导体装置的制造方法,其中所述非导电性树脂膜的分割工序进而具备将利用所述激光熔融断开的所述非导电性树脂膜在其面方向延伸的工序。
9.根据权利要求1所述的半导体装置的制造方法,其中所述非导电性树脂膜的分割工序具备将所述非导电性树脂膜在其面方向延伸而分割所述非导电性树脂膜的工序。
10.根据权利要求1所述的半导体装置的制造方法,其中所述多个芯片区域的单片化工序具备如下工序:在所述半导体晶圆的与具有所述柱状电极的第1表面相反侧的第2表面贴附切割带;以及利用所述切割带维持所述半导体晶圆的晶圆形状,且从所述半导体晶圆的所述第1表面侧沿着所述切割区域形成第1槽。
11.根据权利要求1所述的半导体装置的制造方法,其中所述多个芯片区域的单片化工序具备如下工序:对所述半导体晶圆的具有所述柱状电极的第1表面,沿着所述切割区域照射激光光而形成改质层;在所述半导体晶圆的与所述第1表面相反侧的第2表面贴附树脂带;以及将所述树脂带在其面方向延伸,而分割所述半导体晶圆。
12.根据权利要求1所述的半导体装置的制造方法,其中在安装在所述衬底的所述半导体芯片的侧面,利用所述非导电性树脂膜形成内圆角。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019168888A JP2021048205A (ja) | 2019-09-17 | 2019-09-17 | 半導体装置の製造方法 |
JP2019-168888 | 2019-09-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112530816A CN112530816A (zh) | 2021-03-19 |
CN112530816B true CN112530816B (zh) | 2024-03-08 |
Family
ID=74869778
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010042238.6A Active CN112530816B (zh) | 2019-09-17 | 2020-01-15 | 半导体装置的制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US11309219B2 (zh) |
JP (1) | JP2021048205A (zh) |
CN (1) | CN112530816B (zh) |
TW (1) | TWI740350B (zh) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002033343A (ja) * | 2000-07-18 | 2002-01-31 | Sanyu Rec Co Ltd | 電子部品の製造方法 |
CN1337065A (zh) * | 1999-11-11 | 2002-02-20 | 卡西欧计算机株式会社 | 半导体器件及其制造方法 |
JP2007053325A (ja) * | 2005-07-20 | 2007-03-01 | Furukawa Electric Co Ltd:The | ダイシングダイボンドテープおよびダイシングテープ |
JP2009260213A (ja) * | 2008-03-24 | 2009-11-05 | Hitachi Chem Co Ltd | 半導体装置の製造方法 |
CN109563218A (zh) * | 2016-08-10 | 2019-04-02 | 松下知识产权经营株式会社 | 密封用丙烯酸类组合物、片材、层叠片、固化物、半导体装置及半导体装置的制造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0395639U (zh) | 1990-01-17 | 1991-09-30 | ||
JP5084829B2 (ja) | 2007-06-28 | 2012-11-28 | パナソニック株式会社 | 半導体素子の実装構造体の製造方法、半導体素子の実装方法、及び加圧ツール |
JP2011129779A (ja) | 2009-12-18 | 2011-06-30 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP5474630B2 (ja) | 2010-03-30 | 2014-04-16 | トッパン・フォームズ株式会社 | 電子部品およびその製造方法、部品実装基板 |
US9064881B2 (en) * | 2010-11-11 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protecting flip-chip package using pre-applied fillet |
US20130157414A1 (en) * | 2011-12-20 | 2013-06-20 | Nxp B. V. | Stacked-die package and method therefor |
US9196537B2 (en) * | 2012-10-23 | 2015-11-24 | Nxp B.V. | Protection of a wafer-level chip scale package (WLCSP) |
US8816500B2 (en) * | 2012-12-14 | 2014-08-26 | Infineon Technologies Ag | Semiconductor device having peripheral polymer structures |
JP2015008210A (ja) * | 2013-06-25 | 2015-01-15 | マイクロン テクノロジー, インク. | 半導体装置の製造方法 |
US9343433B2 (en) * | 2014-01-28 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with stacked dies and methods of forming the same |
JP2016058655A (ja) * | 2014-09-11 | 2016-04-21 | 株式会社ジェイデバイス | 半導体装置の製造方法 |
US9484227B1 (en) * | 2015-06-22 | 2016-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dicing in wafer level package |
DE102015120755A1 (de) * | 2015-11-30 | 2017-06-01 | Infineon Technologies Ag | Verfahren zum Vereinzeln von einer Vielzahl von Chips |
JP7046585B2 (ja) * | 2017-12-14 | 2022-04-04 | 日東電工株式会社 | 接着フィルムおよびダイシングテープ付き接着フィルム |
TWI675441B (zh) * | 2018-05-14 | 2019-10-21 | 欣興電子股份有限公司 | 封裝載板結構及其製造方法 |
-
2019
- 2019-09-17 JP JP2019168888A patent/JP2021048205A/ja active Pending
-
2020
- 2020-01-15 CN CN202010042238.6A patent/CN112530816B/zh active Active
- 2020-01-15 TW TW109101376A patent/TWI740350B/zh active
- 2020-03-05 US US16/809,649 patent/US11309219B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1337065A (zh) * | 1999-11-11 | 2002-02-20 | 卡西欧计算机株式会社 | 半导体器件及其制造方法 |
JP2002033343A (ja) * | 2000-07-18 | 2002-01-31 | Sanyu Rec Co Ltd | 電子部品の製造方法 |
JP2007053325A (ja) * | 2005-07-20 | 2007-03-01 | Furukawa Electric Co Ltd:The | ダイシングダイボンドテープおよびダイシングテープ |
JP2009260213A (ja) * | 2008-03-24 | 2009-11-05 | Hitachi Chem Co Ltd | 半導体装置の製造方法 |
CN109563218A (zh) * | 2016-08-10 | 2019-04-02 | 松下知识产权经营株式会社 | 密封用丙烯酸类组合物、片材、层叠片、固化物、半导体装置及半导体装置的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI740350B (zh) | 2021-09-21 |
US20210082761A1 (en) | 2021-03-18 |
US11309219B2 (en) | 2022-04-19 |
JP2021048205A (ja) | 2021-03-25 |
CN112530816A (zh) | 2021-03-19 |
TW202113937A (zh) | 2021-04-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9269873B2 (en) | Semiconductor light emitting device and method for manufacturing same | |
JP4719042B2 (ja) | 半導体装置の製造方法 | |
US7615413B2 (en) | Method of manufacturing stack-type semiconductor device and method of manufacturing stack-type electronic component | |
KR102287698B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP6649308B2 (ja) | 半導体装置およびその製造方法 | |
CN102844859A (zh) | 用于将ic晶粒或晶片接合到tsv晶片的双载体 | |
KR20050121432A (ko) | 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법 | |
US10490470B2 (en) | Semiconductor package and method for fabricating a semiconductor package | |
US20160027766A1 (en) | Fan-out pop stacking process | |
JP2015177062A (ja) | 半導体装置の製造方法および半導体装置 | |
WO2014054451A1 (ja) | 半導体装置及びその製造方法 | |
TWI798519B (zh) | 半導體裝置及其製造方法 | |
WO2014128796A1 (ja) | 半導体装置 | |
US20110147905A1 (en) | Semiconductor device and method of manufacturing the same | |
CN109524358B (zh) | 半导体装置及其制造方法 | |
JP2015225933A (ja) | 半導体装置及びその製造方法 | |
CN112530816B (zh) | 半导体装置的制造方法 | |
JP2007242684A (ja) | 積層型半導体装置及びデバイスの積層方法 | |
CN110797334B (zh) | 半导体装置及其制造方法 | |
JP3573048B2 (ja) | 半導体装置の製造方法 | |
US11551973B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
KR101750206B1 (ko) | 반도체 실장 장치의 가열 헤더 및 반도체의 접합 방법 | |
JP2008108782A (ja) | 電子装置およびその製造方法 | |
JP6422296B2 (ja) | 電子部品およびその製造方法 | |
JP2009246079A (ja) | 半導体パッケージおよびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |