TWI836302B - 電子結構以及製造電子結構的方法 - Google Patents
電子結構以及製造電子結構的方法 Download PDFInfo
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- TWI836302B TWI836302B TW110145711A TW110145711A TWI836302B TW I836302 B TWI836302 B TW I836302B TW 110145711 A TW110145711 A TW 110145711A TW 110145711 A TW110145711 A TW 110145711A TW I836302 B TWI836302 B TW I836302B
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- semiconductor
- semiconductor wafer
- insulating
- resin layer
- insulating resin
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Abstract
提供一種半導體裝置之製造方法以抑制晶片破裂及凸狀電極連接不良且提升良率及信賴性,包含以下步驟。經由凸狀電極電性連接半導體晶片及半導體晶圓。連接前或後,於二者間隙形成第一絕緣樹脂層。於半導體晶圓上形成第二絕緣樹脂層以掩埋半導體晶片。研磨第二絕緣樹脂層及半導體晶片至半導體晶片成為指定厚度。第二絕緣樹脂層上及半導體晶片上形成第一絕緣層,且於第一絕緣層及第二絕緣樹脂層形成露出電極之開口部。導電性材料埋設於開口部。於第一絕緣層上形成配線連接導電性材料。形成第一端子電性連接配線。研磨半導體晶圓達到完成厚度。
Description
本發明關於半導體裝置之製造方法。特別是關於包含薄型半導體堆疊構造之半導體模組之製造方法。
從前,為了實現電子設備之小型化,製作出包含多個半導體晶片之半導體模組。如此內藏於半導體模組內之半導體晶片之間的連接,為了高頻寬化及降低消耗電力,不僅採用從前的打線接合(wire bonding),也還採用凸狀電極(bump)連接,即是使用形成於半導體晶片表面上之凸狀電極(例如專利文獻1:日本專利案第4809957號)。
近年來,因半導體裝置之薄型化或穿矽導孔(Through Silicon Via,TSV)之導孔的形成,要求半導體晶片的薄型化,而提出了薄型半導體晶圓的各種加工方法(例如專利文獻2:日本專利公開案第2010-267653號公報,專利文獻3:日本專利公開案第2012-084780號公報)。然而,製作由凸狀電極連接薄型半導體晶片之間之半導體模組的場合中,背側研磨膠帶(Back Side Grinding tape,BSG tape)之使用或切割(dicing),有發生因揀取(pick up)所造成之晶片破裂(chip crack)以及凸狀電極連接時起因於薄型晶片彎曲之凸狀電極連接不良之虞等問題。而且,也有為了處理薄型晶圓而使用晶圓載體(wafer support)時增加此部分成本之問題。
本發明以提供一種能夠製造半導體裝置之半導體裝置之製造方法為目的,此半導體裝置能夠抑制晶片破裂及凸狀電極連接不良,且提升良率及信賴性。而且,還藉由不使用晶圓載體改以晶圓等級製造半導體裝置,而以提供能夠降低製造成本之半導體裝置之製造方法為目的。
關於本發明之一實施型態之半導體裝置之製造方法,包含以下步驟。準備形成有電極之半導體晶圓,且經由凸狀電極電性連接形成於半導體晶片之第一半導體元件及前述半導體晶圓之前述電極。於前述半導體晶圓與前述半導體晶片之連接前或連接後,於前述半導體晶圓與前述半導體晶片相互面對之間隙形成第一絕緣樹脂層。於前述半導體晶圓上形成第二絕緣樹脂層至掩埋前述半導體晶片之厚度。研磨前述第二絕緣樹脂層及前述半導體晶片至前述半導體晶片成為指定厚度。於前述第二絕緣樹脂層上及前述半導體晶片上形成第一絕緣層,且於前述第一絕緣層及前述第二絕緣樹脂層形成露出前述電極之開口部。以導電性材料埋設於前述開口部。於前述第一絕緣層上形成配線,配線與埋設於前述開口部之導電性材料連接。形成第一端子電性連接於前述配線。研磨前述半導體晶圓為指定厚度。其中,研磨前述半導體晶圓為指定厚度之步驟,為研磨前述半導體晶圓達到完成厚度之步驟。
根據本發明之一實施型態,前述半導體晶圓亦可具有多個元件區域,各元件區域形成有第二半導體元件。
根據本發明之一實施型態,對應前述多個元件區域之其中一者亦可連接有多個前述半導體晶片。
根據本發明之一實施型態,亦可更包含以下步驟。於前述半導體晶圓形成嵌入電極,嵌入電極之一端部電性連接於前述第二半導體元件。於
形成前述第一端子之後,研磨前述半導體晶圓至前述嵌入電極之另一端部之前。露出前述嵌入電極之前述另一端部。形成第二端子,第二端子電性連接至前述嵌入電極之露出的前述另一端部。
根據本發明之一實施型態,亦可更包含以下步驟。前述電極及前述第一半導體元件進行凸狀電極連接之前,沿著前述元件區域之邊界線,於前述半導體晶圓上形成溝槽,溝槽間距寬於切割幅寬,溝槽之深度大於或等於前述完成厚度。於研磨前述半導體晶圓達到前述完成厚度之後,單片化前述半導體晶圓。前述單片化之步驟,為沿著形成於前述半導體晶圓之前述溝槽,以窄於前述溝槽之切割幅寬單片化前述半導體晶圓。
關於本發明之一實施型態之半導體裝置之製造方法,包含以下步驟。準備形成有電極之半導體晶圓,且準備第一半導體晶片,係形成有第一半導體元件,且具有第一嵌入電極,第一嵌入電極電性連接於前述第一半導體元件。經由第一凸狀電極電性連接前述第一半導體晶片之前述第一嵌入電極之一端部及前述半導體晶圓之前述電極。於前述半導體晶圓與前述第一半導體晶片之連接前或連接後,於前述半導體晶圓與前述第一半導體晶片相互面對之間隙形成第一絕緣樹脂層。於前述半導體晶圓上形成第二絕緣樹脂層至掩埋前述第一半導體晶片之厚度。研磨前述第二絕緣樹脂層及前述第一半導體晶片至前述第一嵌入電極之另一端部之前。露出前述第一嵌入電極之前述另一端部。於前述第一半導體晶片上形成第一絕緣層,第一絕緣層覆蓋前述第一嵌入電極之前述另一端部。於前述第一絕緣層上形成第一端子,第一端子經由接觸孔與前述第一嵌入電極之前述另一端部連接。經由第二凸狀電極電性連接前述第一端子及形成於第二半導體晶片之第二半導體元件。於前述第一端子與前述第二半導體晶片之連接前或連接後,於前述第一端子及前述第一絕緣層與前述第二半導體晶片相互面對之間隙形成第三絕緣樹脂層。於前述第一絕緣層上形成第四
絕緣樹脂層至掩埋前述第二半導體晶片之厚度。研磨前述第四絕緣樹脂層及前述第二半導體晶片至前述第二半導體晶片成為指定厚度。於前述第四絕緣樹脂層上及前述第二半導體晶片上形成第二絕緣層。於前述第二絕緣層、前述第四絕緣樹脂層、前述第一絕緣層及前述第二絕緣樹脂層形成開口部,開口部露出前述電極,電極形成於前述半導體晶圓。以導電性材料埋設於前述開口部。於前述第二絕緣層上形成配線,配線與埋設於前述開口部之導電性材料連接。形成第二端子電性連接於前述配線。研磨前述半導體晶圓為指定厚度。其中,研磨前述半導體晶圓為指定厚度之步驟,為研磨前述半導體晶圓達到完成厚度之步驟。
根據本發明之一實施型態,前述半導體晶圓亦可具有多個元件區域,各元件區域形成有第三半導體元件。
根據本發明之一實施型態,對應前述多個元件區域之其中一者亦可連接有多個前述第一半導體晶片。
根據本發明之一實施型態之半導體裝置之製造方法,亦可更包含經由前述第一凸狀電極電性連接前述電極及形成於至少一第三半導體晶片之第四半導體元件。
根據本發明之一實施型態,亦可更包含以下步驟。於前述半導體晶圓形成第二嵌入電極,第二嵌入電極之一端部電性連接於前述第三半導體元件。於形成前述第二端子之後,研磨前述半導體晶圓至前述第二嵌入電極之另一端部之前。露出前述第二嵌入電極之前述另一端部。形成第三端子,第三端子電性連接至前述第二嵌入電極之露出的前述另一端部。
根據本發明之一實施型態,亦可更包含以下步驟。前述電極及前述第一嵌入電極之前述端部進行凸狀電極連接之前,沿著前述元件區域之邊界線,於前述半導體晶圓上形成溝槽,溝槽間距寬於切割幅寬,溝槽之深度大
於或等於前述完成厚度。於研磨前述半導體晶圓達到前述完成厚度之後,單片化前述半導體晶圓。其中,前述單片化之步驟,為沿著形成於前述半導體晶圓之前述溝槽,以窄於前述溝槽之前述切割幅寬單片化前述半導體晶圓。
藉由本發明,能夠提供半導體裝置之製造方法,其能夠以抑制晶片破裂及凸狀電極連接不良且提升良率及信賴性之方式製造半導體裝置。而且,還能夠提供半導體裝置之製造方法,其能夠降低製造成本。
10、20、30、40、40’:半導體裝置
101:半導體晶圓
103:第一半導體元件
104:電極
105、105a、105b:半導體晶片
106:第二半導體元件
107:電極
109:凸狀電極
111:第一絕緣樹脂層
113:第二絕緣樹脂層
114:第一絕緣層
115:開口部
117:配線
119:配線
120:絕緣膜
121:端子
122:抗焊層
123:外部端子
201:溝槽
401:嵌入電極
402:第二半導體元件
403:第一半導體晶片
405:電極
409:第一凸狀電極
411:第一絕緣樹脂層
413:第二絕緣樹脂層
415:第一絕緣層
417:端子
419:第二半導體晶片
420:第三半導體元件
421:電極
423:第二凸狀電極
425:第三絕緣樹脂層
427:第四絕緣樹脂層
429:第二絕緣層
431:配線
433:配線
434:絕緣膜
435:端子
436:抗焊層
437:外部端子
439:第三半導體晶片
441:第四半導體元件
50:封裝
501:半導體晶圓
503:嵌入電極
505:第一半導體元件
506:電極
507:配線
508:絕緣膜
509:端子
510:抗焊層
511:端子
512:第二絕緣層
513:抗焊層
515:開口
517:外部端子
519:外部端子
[圖1A]及[圖1B]繪示用以說明關於本發明之實施型態一之半導體裝置之製造方法之圖面。
[圖2A]及[圖2B]繪示用以說明關於本發明之實施型態一之半導體裝置之製造方法之圖面。
[圖3]繪示用以說明關於本發明之實施型態一之半導體裝置之製造方法之圖面。
[圖4]繪示用以說明關於本發明之實施型態一之半導體裝置之製造方法之圖面。
[圖5]繪示用以說明關於本發明之實施型態一之半導體裝置之製造方法之圖面。
[圖6]繪示用以說明關於本發明之實施型態一之半導體裝置之製造方法之圖面。
[圖7]繪示用以說明關於本發明之實施型態一之半導體裝置之製造方法之圖面。
[圖8]繪示用以說明關於本發明之實施型態一之半導體裝置之製造方法之圖
面。
[圖9A]及[圖9B]繪示用以說明關於本發明之實施型態二之半導體裝置之製造方法之圖面。
[圖10]繪示用以說明關於本發明之實施型態二之半導體裝置之製造方法之圖面。
[圖11]繪示用以說明關於本發明之實施型態二之半導體裝置之製造方法之圖面。
[圖12]繪示用以說明關於本發明之實施型態二之半導體裝置之製造方法之圖面。
[圖13]繪示用以說明關於本發明之實施型態二之半導體裝置之製造方法之圖面。
[圖14]繪示用以說明關於本發明之實施型態二之半導體裝置之製造方法之圖面。
[圖15]繪示用以說明關於本發明之實施型態三之半導體裝置之製造方法之圖面。
[圖16]繪示用以說明關於本發明之實施型態三之半導體裝置之製造方法之圖面。
[圖17]繪示用以說明關於本發明之實施型態三之半導體裝置之製造方法之圖面。
[圖18]繪示用以說明關於本發明之實施型態三之半導體裝置之製造方法之圖面。
[圖19]繪示用以說明關於本發明之實施型態四之半導體裝置之製造方法之圖面。
[圖20]繪示用以說明關於本發明之實施型態四之半導體裝置之製造方法之
圖面。
[圖21]繪示用以說明關於本發明之實施型態四之半導體裝置之製造方法之圖面。
[圖22]繪示用以說明關於本發明之實施型態四之半導體裝置之製造方法之圖面。
[圖23]繪示用以說明關於本發明之實施型態四之半導體裝置之製造方法之圖面。
[圖24]繪示用以說明關於本發明之實施型態四之半導體裝置之製造方法之圖面。
[圖25]繪示用以說明關於本發明之實施型態四之半導體裝置之製造方法之圖面。
[圖26]繪示用以說明關於本發明之實施型態四之變形例之半導體裝置之製造方法之圖面。
[圖27]繪示用以說明關於本發明之實施型態五之半導體裝置之製造方法之圖面。
[圖28]繪示用以說明關於本發明之實施型態五之半導體裝置之製造方法之圖面。
[圖29]繪示用以說明關於本發明之實施型態五之半導體裝置之製造方法之圖面。
[圖30]繪示用以說明關於本發明之實施型態五之半導體裝置之製造方法之圖面。
[圖31]繪示用以說明關於本發明之實施型態五之半導體裝置之製造方法之圖面。
[圖32]繪示用以說明關於本發明之實施型態五之半導體裝置之製造方法之
圖面。
[圖33]繪示用以說明關於本發明之實施型態五之半導體裝置之製造方法之圖面。
以下,將參照圖式說明關於本發明之半導體裝置之製造方法。然而,本發明之半導體裝置之製造方法能夠以多種不同的態樣實施,而並非限定解釋成以下所示之實施型態之記載內容。而且,以本實施型態所參照之圖式中,同一部分或具有同樣功能之部分將附上相同符號,且將省略如此反覆的說明。再者,以下之說明中,層、模、區域等之要件在其他要件之「上」時,並非限定為在其他要件之「正上方」之場合,亦包含二者中間更有另外的要件之場合。
關於本發明之第一實施型態之半導體裝置之製造方法之概要,將一邊參照圖1A至圖8一邊說明。
首先,如圖1A及圖1B所示,準備形成有多個元件區域之半導體晶圓101。於此,所謂元件區域表示於切割半導體晶圓以單片化之後而具有做為一個半導體晶片之功能的區域。圖1A為半導體晶圓101之俯視圖,圖1B為圖1A之區域A中沿B-B線之剖面圖。半導體晶圓101中亦可於每個元件區域形成有半導體元件(以下稱為第一半導體元件)103。於此,第一半導體元件103亦可包含電晶體(transistor)之元件。另外,於半導體晶圓101上於每個元件區域經過絕緣膜而形成有電極104,電極104電性連接於第一半導體元件103且由鋁(Al)等金屬材料製成。此外,於半導體晶圓101上,亦可形成第一半導體元件103及電極104之配線層。圖1B為半導體晶圓101之部分剖面圖。圖1B顯示形
成於半導體晶圓101之二個元件區域。然而,半導體晶圓101亦可不形成有第一半導體元件103,而可為形成有配線層之內埋式基板(interposer substrate)。
接下來,準備於半導體基板形成有半導體元件(以下稱為第二半導體元件)106之半導體晶片105。於此,第二半導體元件106可包含電晶體等元件。為了於晶圓等級進行半導體裝置之組裝,故準備數量對應形成於半導體晶圓101之元件區域的半導體晶片105。於半導體晶片105上經過絕緣膜而形成有電極107,電極107經由配線電性連接至第二半導體元件106。
如圖2A及圖2B所示,形成於半導體晶圓101之每個元件區域之第一半導體元件103以及形成於半導體晶片105之第二半導體元件106經由凸狀電極109相互面對地接合,而電性連接第一半導體元件103及第二半導體元件106。圖2A為顯示將半導體晶片105以凸狀電極接合於半導體晶圓101上之狀態之俯視圖,圖2B為圖2A之區域A中沿B-B線之剖面圖。具體而言,電極104電性連接於第一半導體元件103且面對半導體晶片105,電極107電性連接於第二半導體元件106,於電極104上及/或電極107上形成凸狀電極109,且藉由熱處理而相互面對地接合電極104及電極107。凸狀電極109亦可例如使用金、焊料或銅柱藉由半加成處理(semi-additive process)等方式製成。於圖2A及圖2B中,雖然顯示著使用於第一半導體元件103及第二半導體元件106之連接為僅於電極104上及/或電極107上形成凸狀電極109之態樣,但本發明並非限定於此,亦可於未面對半導體晶片105之電極104上形成凸狀電極109。另外,半導體晶圓101為內埋式基板之場合中,亦可對形成於內埋式基板上且與形成於內埋式基板之配線電性連接之電極以及電性連接於第二半導體元件106之電極107進行凸狀電極連接。
如圖2B所示,經由凸狀電極109接合半導體晶圓101及半導體晶片105之後,於半導體晶圓101及半導體晶片105之間隙填充底膠(underfill,以
下稱為第一絕緣樹脂層)111。第一絕緣樹脂層111若為底膠用之絕緣性樹脂的話則並未特別受限,舉例而言,亦可使用於環氧系樹脂中添加二氧化矽、氧化鋁之填充物及胺系硬化劑等之物質。此外,第一絕緣樹脂層111亦可形成於半導體晶圓101及半導體晶片105進行凸狀電極接合之前。
以下將描述經由凸狀電極109接合半導體晶圓101及半導體晶片105之後,於半導體晶圓101及半導體晶片105之間隙填充底膠而進行底膠密封(毛細底膠,capillary underfill,CUF)之方法之一範例。
舉例而言,於半導體晶圓101及半導體晶片105之凸狀電極接合之後,由於為了按照需求而提升底膠之流動性,而對半導體晶圓101及半導體晶片105進行電漿(plasma)處理,故亦可使用分配器(dispenser)從各個半導體晶片105之一端的一邊距離數百微米(μm)程度之位置以線條形狀將液態之底膠材料塗布於半導體晶圓101上。分配時,亦可為了降低之液料之黏性而對晶片及底膠材料加熱,亦可以指定的時間間隔進行多次塗布。經塗布之底膠材料藉由毛細現象而進入半導體晶圓101及半導體晶片105之間隙內。
另外,以下將描述經由凸狀電極109接合半導體晶圓101及半導體晶片105之前,以液態之底膠材料(非導電貼合,non-conductive paste,NCP)進行密封之方法之一範例。
舉例而言,於半導體晶圓101及半導體晶片105之凸狀電極接合之前,預先於凸狀電極連接用之裝置(覆晶接合件,flip chip bonder)裝設分配器。半導體晶圓101對應於裝設有半導體晶片105之區域的一部分或全部,於此處之半導體晶圓101上,沿著難以產生氣泡之塗布軌跡塗布底膠材料。朝向半導體晶圓101裝設半導體晶片105。換言之,半導體晶圓101及半導體晶片105進行凸狀電極連接的同時,亦可於半導體晶圓101及半導體晶片105之間隙將底膠材料全面地推開。
另外,舉例而言,於半導體晶圓101、半導體晶片105之切割前之晶圓或二者,藉由底膠液料之旋轉塗敷(spin coat)或薄膜形狀之底膠材料之積層(laminate)等方式以晶圓單位預先貼附底膠。於貼附有底膠材料之狀態的半導體晶圓101及單片化後之半導體晶片105進行凸狀電極連接的同時,亦可以底膠材料密封半導體晶圓101及半導體晶片105之間隙。
藉由以上描述之方法,於半導體晶圓101及半導體晶片105之間隙填充了底膠之後,藉由以烤爐等加熱使底膠硬化,而形成第一絕緣樹脂層111。
接下來,如圖2B所示,於半導體晶圓101上形成具有掩埋半導體晶片105之厚度之絕緣樹脂層(以下稱為第二絕緣樹脂層)113。用做為第二絕緣樹脂層113之樹脂,雖並未特別受限,但必須具有於再次配線工程中之耐藥性及焊料耐熱性,且為了抑制晶圓的彎曲,以使用具有低熱膨脹率之樹脂為佳。舉例而言,亦可使用薄膜成形材料,此薄膜成形材料可由扇出封裝晶片(Fan-out package chip)嵌入用途之壓縮成形用之環氧混合(hybrid)材料或真空積層用之矽氧烷(silicone)混合材料製成。此外,圖2A中省略了第二絕緣樹脂層113之記載。
接下來,如圖3所示,固化第二絕緣樹脂層113之後,藉由背側研磨處理研磨並未形成有第二半導體元件106之各個半導體晶片105之背面連帶第二絕緣樹脂層113達到所希望的厚度(完成厚度,即薄化工程結束後之最終的半導體晶片之厚度)。研磨各個半導體晶片105及第二絕緣樹脂層113時,並未形成有第一半導體元件103之半導體晶圓101之背面貼附著背側研磨膠帶(表面保護膠帶),以藉由背側研磨處理工程薄化半導體晶片105。各個半導體晶片105之薄化結束後,從半導體晶圓101之背面剝離背側研磨膠帶。
於半導體晶片105之背面形成配線之前形成第一絕緣層114。於
半導體晶片105及第二絕緣樹脂層113之研磨表面,第一絕緣層114例如可使用塗布環氧系之組成配線板用之樹脂塗敷材料,或者從處理性的觀點可為薄膜型層間絕緣材料,或者亦可為了輔助後述配線形成工程之附帶有樹脂的銅箔。再者,如圖4所示,對第二絕緣樹脂層113及第一絕緣層114使用二氧化碳雷射或紫外光釔鋁石榴石(UV-YAG)雷射等雷射而形成開口部115,開口部115露出形成於半導體晶圓101上且並未面對半導體晶片105之電極104。從成本的觀點,開口部115雖以雷射方式形成為佳,但亦可藉由光蝕刻(photo etching)方式形成。使用於開口部115之形成之雷射強度,設定成不會對半導體晶圓101上之電極104進行加工之條件。於可能不幸發生電極104損傷之場合中,如前述於並未面對半導體晶片105之電極104上,形成銅柱等凸狀電極109做為凸狀電極。由於為了保護電極104免於雷射傷害而使用凸狀電極109,故能夠防止電極104之損傷。使用二氧化碳雷射之場合中,因會發生樹脂汙染(smear),故於形成開口部115之後將繼續進行去污處理。以銅柱等物保護電極104之場合中,亦可將使用鹼性過錳酸鹽之去汙液之處理做為去污處理。露出電極104之場合中,亦可將藉由電漿去汙之處理做為去汙處理。
接下來,如圖5所示,於半導體晶圓101之上表面整面,也就是第一絕緣層114上、藉由開口部115而被露出之電極104上以及開口部115之側面,形成導電層。藉由圖案化導電層,形成埋設於開口部115之配線117及與配線117連接之配線119。舉例而言,亦可藉由半加成法形成配線117、119。藉由半加成法形成配線117、119之場合中,半導體晶圓101之上表面整面實施無電解鍍銅之後,以抗鍍材料形成圖案,藉由電解鍍銅基於此圖案形成配線之後,去除抗鍍材料,且藉由蝕刻方式去除無電解鍍銅露出部分。藉由此工程,能夠形成埋設於開口部115之配線117及與配線117連接之配線119。藉由反覆進行前述絕緣層之形成工程及前述配線工程,亦可形成二層以上之配線層。
形成配線117、119之後,如圖6所示,於配線119上形成絕緣膜120,且於絕緣膜120上形成連接至配線119之端子121。形成絕緣膜120時可使用與第一絕緣層114同樣為組成配線板用之熱硬化性環氧系絕緣膜,或者亦可使用附帶有樹脂的銅箔。再者,於端子121上塗布抗焊層122之後,開設開口以露出端子121。於所露出之端子121之表面亦可進行預焊劑(pre-flux,有機保焊劑,Organic Solderability Preservative,OSP)處理等之抗氧化處理。於端子121上,亦可按照需求於每個元件區域以晶圓等級形成外部端子123。外部端子123亦可藉由球體裝設機裝設焊料球體,而做為球柵陣列(Ball Grid Array,BGA)。
接下來,如圖7所示,藉由背側研磨處理研磨並未形成有第一半導體元件103之半導體晶圓101之背面而達到所希望的厚度(完成厚度,即薄化工程結束後之最終的半導體晶圓之厚度),薄化半導體晶圓101。研磨半導體晶圓101時,於靠近形成有端子121或外部端子123之位置貼附背側研磨膠帶。半導體晶圓101之薄化結束後,剝離背側研磨膠帶。
之後,如圖8所示,沿著形成於半導體晶圓101之元件區域之邊界線,藉由切割抗焊層122、絕緣膜120、第一絕緣層114及第二絕緣樹脂層113以單片化半導體晶圓101,而製作半導體裝置10。於單片化半導體晶圓101之前,亦可按照需求,於半導體晶圓101之背面藉由絕緣樹脂等物形成絕緣膜並加以固化。於半導體晶圓101之背面形成絕緣膜之場合中,隨著半導體晶圓101亦切割絕緣膜而進行單片化。
根據關於本發明之第一實施型態之半導體裝置之製造方法,因於進行半導體晶圓101及半導體晶片105之薄化之前(半導體晶圓101及半導體晶片105之厚度為較厚的狀態下)進行半導體晶圓101及半導體晶片105之凸狀電極連接,而能夠抑制起因於凸狀電極連接時之晶片彎曲而造成之凸狀電極連
接不良及短路,進而能夠提升半導體裝置之良率及信賴性。而且,因藉由第二絕緣樹脂層113補強後再研磨半導體晶片105,而能夠於半導體晶片105之研磨時抑制晶片破裂。再者,因於進行半導體晶圓101之薄化之前(半導體晶圓101之厚度為較厚的狀態下)進行配線119之形成,藉由半導體晶圓101之剛性,能夠在不使用晶圓載體時也能夠安定地進行配線119之形成,進而能夠降低製造成本。
關於本發明之第二實施型態之半導體裝置之製造方法之概要,將一邊參照圖9A至圖14一邊說明。關於第二實施型態之半導體裝置之製造方法與關於第一實施型態之半導體裝置之製造方法相異,而包含以下工程。形成於半導體晶圓之每個元件區域之第一半導體元件以及形成於半導體晶片之第二半導體元件相互面對,且於經由凸狀電極進行接合之前,沿著形成於半導體晶圓之多個元件區域之各個邊界線,於並未形成有第一半導體元件之半導體晶圓之背面,形成間距寬於切割幅寬之溝槽。其中,以下所說明之關於第二實施型態之半導體裝置之製造方法中,將省略或簡略化與關於第一實施型態之半導體裝置之製造方法重覆之說明。
圖9A為半導體晶圓101之俯視圖,圖9B為圖9A之區域A中沿B-B線之剖面圖。首先,與第一實施型態同樣地,準備形成有多個元件區域之半導體晶圓101。然後,如圖9A及圖9B所示,沿著元件區域之邊界線,於半導體晶圓101之靠近形成有第一半導體元件103之位置之表面,形成間距寬於切割幅寬之溝槽201。溝槽201亦可藉由刀片(blade)、雷射等方式半切割(half dicing)而形成。溝槽201之深度,可形成為比半導體晶圓101之完成厚度還深。此外,半導體晶圓101亦可省略第一半導體元件103,而可為形成有配線層之內埋式基板。
關於本發明之第二實施型態之半導體裝置之製造方法,除了沿著元件區域之邊界線於半導體晶圓101形成溝槽201以外,其餘與關於第一實施型態之半導體裝置之製造方法大致相同。也就是說,如圖10所示,以晶圓等級對半導體晶圓101及半導體晶片105進行凸狀電極接合,於半導體晶圓101及半導體晶片105之間隙填充第一絕緣樹脂層111,且於半導體晶圓101上形成掩埋半導體晶片105之厚度之第二絕緣樹脂層113。第二絕緣樹脂層113亦填充至形成於半導體晶圓101之溝槽201。
之後,如圖11所示,藉由背側研磨處理研磨各個半導體晶片105之背面連帶第二絕緣樹脂層113達到完成厚度,以薄化半導體晶片105。後續,於各個半導體晶片105及第二絕緣樹脂層113之研磨表面形成第一絕緣層114。
之後,如圖12所示,對第二絕緣樹脂層113及第一絕緣層114使用二氧化碳雷射或紫外光釔鋁石榴石雷射等雷射而形成開口部115,開口部115露出形成於半導體晶圓101上之電極104。於半導體晶圓101之上表面整面,也就是第一絕緣層114上、藉由開口部115而被露出之電極104上以及開口部115之側面,藉由半加成法等方式形成導電層。再藉由圖案化,形成埋設於開口部115之配線117及與配線117連接之配線119。形成配線117、119之後,於配線119上形成絕緣膜120,且於絕緣膜120上形成連接至配線119之端子121。再者,於端子121上塗布抗焊層122之後,開設開口以露出端子121。於所露出之端子121之表面亦可進行有機保焊劑處理等之抗氧化處理。於端子121上,亦可按照需求於每個元件區域以晶圓等級形成外部端子123。
之後,如圖13所示,因藉由背側研磨處理研磨並未形成有第一半導體元件103之半導體晶圓101之背面而達到完成厚度,故如圖14所示,沿著形成於半導體晶圓101之元件區域之邊界線,藉由切割抗焊層122、絕緣膜120、第一絕緣層114及第二絕緣樹脂層113以單片化半導體晶圓101,而製作半
導體裝置20。切割幅寬亦比形成於半導體晶圓101之背面之溝槽201之間距要窄。
關於本發明之第二實施型態之半導體裝置之製造方法中,因予以形成於半導體晶圓101之溝槽201之深度大於或等於半導體晶圓101之完成厚度,故於半導體晶圓101之薄化結束時,靠近並未形成有第一半導體元件103之半導體晶圓101之背面之位置,會露出形成於溝槽201之區域中之第二絕緣樹脂層113,且對應於各個元件區域之半導體晶圓101之側面會受到第二絕緣樹脂層113覆蓋。也就是說,於半導體晶圓101之研磨工程結束時,半導體晶圓101會分離至每個元件區域之狀態。因此,為了單片化半導體晶圓101之切割,將會對抗焊層122、絕緣膜120、第一絕緣層114及第二絕緣樹脂層113進行。
根據關於本發明之第二實施型態之半導體裝置之製造方法,與關於第一實施型態之半導體裝置之製造方法同樣地,能夠抑制起因於凸狀電極連接時之晶片彎曲而造成之凸狀電極連接不良及短路,進而能夠提升半導體裝置之良率及信賴性,且有能夠降低製造成本之可能。再者,根據關於本發明之第二實施型態之半導體裝置之製造方法,藉由予以形成於半導體晶圓101之溝槽201具有間距寬於切割幅寬且具有深度大於或等於完成厚度,而能夠於切割工程之前令半導體晶圓101分離至每個元件區域,以對抗焊層122、絕緣膜120、第一絕緣層114及第二絕緣樹脂層113進行切割。因此,能夠抑制因切割而造成之半導體晶圓101之晶片破裂。再者,因對應於各個元件區域之半導體晶圓101之側面受到第二絕緣樹脂層113覆蓋,故不僅能夠抑制因切割而造成之半導體晶圓101之晶片破裂,還能夠抑制形成於靠近半導體晶圓101之側面之位置之配線層等之剝離,且能夠更提升半導體裝置之良率及信賴性。
如上所述,關於本發明之第二實施型態之半導體裝置之製造方法中,於半導體晶圓101及半導體晶片105進行凸狀電極接合之前,沿著元件區
域之邊界線於半導體晶圓101之形成有第一半導體元件103之表面予以形成溝槽201,溝槽201雖然具有間距寬於切割幅寬且具有深度大於或等於半導體晶圓101之完成厚度之特徵,但此溝槽201之深度亦可具有深度未滿半導體晶圓101之完成厚度。
關於本發明之第三實施型態之半導體裝置之製造方法之概要,將一邊參照圖15至圖18一邊說明。關於第三實施型態之半導體裝置之製造方法與關於第一及第二實施型態之半導體裝置之製造方法相異。於半導體晶圓之每個元件區域中,經由凸狀電極電性連接形成於半導體晶圓之每個元件區域之第一半導體元件以及形成於半導體晶片之第二半導體元件時,對應半導體晶圓之一個元件區域凸狀電極接合多個半導體晶片。其中,以下所說明之關於第三實施型態之半導體裝置之製造方法中,將省略或簡略化與關於第一及第二實施型態之半導體裝置之製造方法重覆之說明。
首先,如圖15所示,準備形成有多個元件區域之半導體晶圓101,且與關於本發明之第二實施型態之半導體裝置之製造方法同樣地,沿著元件區域之邊界線,於半導體晶圓101之靠近形成有第一半導體元件103之位置之表面形成溝槽201。半導體晶圓101亦可省略第一半導體元件103,而可為形成有配線層之內埋式基板。而且,亦可省略沿著半導體晶圓101之邊界線於半導體晶圓101形成溝槽201之工程。
接下來,如圖16所示,形成於半導體晶圓101之每個元件區域之第一半導體元件103以及形成於半導體晶片105a、105b之第二半導體元件(未繪示)相互面對,經由凸狀電極109電性連接電極104及電極107。其中,電極104形成於半導體晶圓101,電性連接於第一半導體元件103,且面對半導體晶片105a、105b。其中,電極107分別形成於半導體晶片105a、105b,且電性連接
於第二半導體元件。而且,半導體晶圓101為內埋式基板之場合中,亦可對形成於內埋式基板上且與形成於內埋式基板之配線電性連接之電極以及分別形成於半導體晶片105a、105b之電極107進行凸狀電極連接。之後,於半導體晶圓101及半導體晶片105a、105b之間隙填充第一絕緣樹脂層111,且於半導體晶圓101上形成掩埋半導體晶片105a、105b之厚度之第二絕緣樹脂層113。第二絕緣樹脂層113亦填充至形成於半導體晶圓101之溝槽201。關於本實施型態之半導體裝置之製造方法中,第一半導體元件103及多個第二半導體元件進行凸狀電極連接。其中,第一半導體元件103形成於半導體晶圓101之多個元件區域中之一個元件區域。其中,多個第二半導體元件分別形成於多個半導體晶片105a、105b。
接下來,如圖17所示,藉由背側研磨處理研磨各個半導體晶片105a、105b之背面連帶第二絕緣樹脂層113達到完成厚度,以薄化半導體晶片105a、105b。之後,與關於第一及第二實施型態之半導體裝置之製造方法同樣地,於各個半導體晶片105a、105b及第二絕緣樹脂層113之研磨表面形成第一絕緣層114。於第一絕緣層114及第二絕緣樹脂層113形成開口部115,開口部115露出形成於半導體晶圓101上之電極104。於半導體晶圓101之上表面整面,也就是第一絕緣層114上、藉由開口部115而被露出之電極104上以及開口部115之側面,藉由半加成法等方式形成導電層。再藉由圖案化,形成埋設於開口部115之配線117及與配線117連接之配線119。之後,於配線119上形成絕緣膜120,且於絕緣膜120上形成連接至配線119之端子121。再者,於端子121上塗布抗焊層122之後,開設開口以露出端子121。於端子121上按照需求形成外部端子123之後,藉由背側研磨處理研磨並未形成有第一半導體元件103之半導體晶圓101之背面而達到完成厚度。於半導體晶圓101之薄化結束時,靠近並未形成有第一半導體元件103之半導體晶圓101之背面之位置,會露出形成於溝槽201之區域
中之第二絕緣樹脂層113。之後,如圖18所示,沿著形成於半導體晶圓101之元件區域之邊界線,藉由切割抗焊層122、絕緣膜120、第一絕緣層114及第二絕緣樹脂層113以單片化半導體晶圓101,而製作半導體裝置30。
如圖18所示,半導體裝置30中,雖然經由凸狀電極連接形成於半導體晶圓101之一個元件區域之第一半導體元件103以及分別形成於二個半導體晶片105a、105b之第二半導體元件(未繪示),但並非限定於此。亦可經由凸狀電極連接形成於半導體晶圓101之一個元件區域之第一半導體元件103以及分別形成於三個以上半導體晶片105之第二半導體元件。
根據關於本發明之第三實施型態之半導體裝置之製造方法,即使在對應半導體晶圓101之一個元件區域平放且接合多個半導體晶片105a、105b以製造半導體裝置之場合中,與關於本發明之第一及第二實施型態之半導體裝置之製造方法同樣地,能夠抑制起因於凸狀電極連接時之晶片彎曲而造成之凸狀電極連接不良及短路,進而能夠提升半導體裝置之良率及信賴性,且有能夠降低製造成本之可能。
關於本發明之第四實施型態之半導體裝置之製造方法之概要,將一邊參照圖19至圖25一邊說明。關於第四實施型態之半導體裝置之製造方法與關於第一及第二實施型態之半導體裝置之製造方法相異。是經由形成有穿矽導孔(穿矽電極)之其他半導體晶片,接合形成於半導體晶圓之每個元件區域之第一半導體元件以及形成於半導體晶片之第二半導體元件。以下所說明之關於第四實施型態之半導體裝置之製造方法中,將省略或簡略化與關於第一及第二實施型態之半導體裝置之製造方法重覆之說明。
首先,準備形成有多個元件區域之半導體晶圓101,且與關於本發明之第二實施型態之半導體裝置之製造方法同樣地,沿著元件區域之邊界
線,於半導體晶圓101之靠近形成有第一半導體元件103之位置之表面形成溝槽201。半導體晶圓101亦可省略第一半導體元件103,而可為形成有配線層之內埋式基板。而且,亦可省略沿著半導體晶圓101之邊界線於半導體晶圓101形成溝槽201之工程。
接下來,準備形成有嵌入電極401之半導體基板403(以下稱為第一半導體晶片403)。嵌入電極401形成於第一半導體晶片403之內部,且嵌入電極401之一端部經由配線層連接至形成於第一半導體晶片403之第二半導體元件402。嵌入電極401可藉由下列方式形成。藉由反應性離子蝕刻等方式於第一半導體晶片403形成導孔,並使用化學氣相沉積(Chemical Vapor Deposition,CVD)而於側壁形成二氧化矽或氮化矽等之絕緣膜,再藉由電鍍而將例如銅等之金屬之導電性材料埋設於導孔。於第一半導體晶片403上形成外部連接用之電極405,電極405電性連接於第二半導體元件402及嵌入電極401。
接下來,如圖19所示,經由第一凸狀電極409電性連接電極104及嵌入電極401。其中,電極104連接至形成於半導體晶圓101之每個元件區域之第一半導體元件103,且面對第一半導體晶片403。嵌入電極401形成於第一半導體晶片403。具體而言,電極104形成於半導體晶圓101上,於電極104上及/或於電極405上形成第一凸狀電極409,且藉由熱處理而相互面對地接合電極104及電極405。另外,半導體晶圓101為內埋式基板之場合中,亦可對形成於內埋式基板上且與形成於內埋式基板之配線電性連接之電極以及電性連接於第二半導體元件402之電極405進行凸狀電極連接。
經由第一凸狀電極409接合半導體晶圓101及第一半導體晶片403之後,於半導體晶圓101及第一半導體晶片403之間隙填充第一絕緣樹脂層411。第一絕緣樹脂層411亦可於半導體晶圓101及第一半導體晶片403進行凸狀
電極接合之前形成。
接下來,於半導體晶圓101上形成掩埋第一半導體晶片403之厚度之第二絕緣樹脂層413。身為第二絕緣樹脂層413之材料,可使用與本發明之第一實施型態中所述之第二絕緣樹脂層113相同之材料。固化第二絕緣樹脂層413之後,如圖20所示,於並未形成有第一半導體元件103之半導體晶圓101之背面貼附背側研磨膠帶,且從靠近並未形成有嵌入電極401之第一半導體晶片403之背面之位置,藉由背側研磨處理研磨第一半導體晶片403連帶第二絕緣樹脂層413至嵌入電極401之另一端部之前,以薄化第一半導體晶片403。
從半導體晶圓101之背面剝離背側研磨膠帶之後,藉由化學機械平坦化(Chemical-Mechanical Planarization,CMP)等方法研磨第一半導體晶片403,以露出嵌入電極401之另一端部。藉此,嵌入電極401具有做為貫通第一半導體晶片403之穿矽導孔之功能。接下來,如圖21所示,形成第一絕緣層415,以覆蓋於第一半導體晶片403上露出之嵌入電極401之另一端部。第一絕緣層415例如可使用塗布環氧系之組成配線板用之樹脂塗敷材料,或者從處理性的觀點可為薄膜型層間絕緣材料,或者亦可為了輔助後述配線形成工程之附帶有樹脂的銅箔。後續,蝕刻第一絕緣層415以形成露出嵌入電極401之另一端部之接觸孔,且於第一絕緣層415上形成經由接觸孔而與嵌入電極401連接之端子417。亦可藉由銅等材料形成端子417。端子417為銅端子之場合中,為了防止與後續連接之焊料合金化,亦可於銅上形成鎳、金等之阻障層(barrier layer)。
接下來,準備形成有第三半導體元件420之第二半導體晶片419,如圖22所示,經由第二凸狀電極423電性連接電極421及端子417,以接合第一半導體晶片403及第二半導體晶片419。其中,電極421電性連接至形成於第二半導體晶片419之第三半導體元件420,端子417連接至嵌入電極401之另一
端部。具體而言,端子417形成於第一絕緣層415上且與之嵌入電極401之另一端部連接,電極421形成於第二半導體晶片419上,於端子417上及/或於電極421上形成第二凸狀電極423,且藉由熱處理而相互面對地接合端子417及電極421。
經由第二凸狀電極423接合嵌入電極401之另一端部及第二半導體晶片419之後,於第一絕緣層415及第二半導體晶片419之間隙填充底膠(以下稱為第三絕緣樹脂層)425。第三絕緣樹脂層425若為底膠用之絕緣性樹脂的話則並未特別受限。此外,第三絕緣樹脂層425亦可形成於嵌入電極401之另一端部及第二半導體晶片419之進行凸狀電極接合之前。
接下來,於第一絕緣層415上形成具有掩埋第二半導體晶片419之厚度之絕緣樹脂層(以下稱為第四絕緣樹脂層)427。用做為第四絕緣樹脂層427之樹脂,與第二絕緣樹脂層413同樣地,可使用與本發明之第一實施型態中所述之第二絕緣樹脂層113相同之材料。
固化第四絕緣樹脂層427之後,如圖23所示,藉由背側研磨處理研磨並未形成有第三半導體元件420之第二半導體晶圓419之背面連帶第四絕緣樹脂層427達到所希望的厚度(完成厚度)。研磨第二半導體晶片419及第四絕緣樹脂層427時,並未形成有第一半導體元件103之半導體晶圓101之背面貼附著背側研磨膠帶,以藉由背側研磨處理工程薄化第二半導體晶片419。第二半導體晶片419之薄化結束後,從半導體晶圓101之背面剝離背側研磨膠帶。
接下來,於第二半導體晶片419及第四絕緣樹脂層427之研磨表面形成第二絕緣層429。第二絕緣層429亦可使用與第一絕緣層415相同之材料。如圖24所示,於第二絕緣層429、第四絕緣樹脂層427、第一絕緣層415及第二絕緣樹脂層413形成開口部,開口部露出形成於半導體晶圓101上之電極104。於半導體晶圓101之上表面整面,也就是第二絕緣層429上、藉由開口部
而被露出之電極104上以及開口部之側面,藉由半加成法等方式形成導電層。再藉由圖案化,形成埋設於開口部之配線431及與配線431連接之配線433。之後,於配線433上形成絕緣膜434,且於絕緣膜434上形成連接至配線433之端子435。於端子435上塗布抗焊層436之後,開設開口以露出端子435。於端子435上,按照需求形成外部端子437。外部端子437亦可為球柵陣列球體。
之後,藉由背側研磨處理研磨並未形成有第一半導體元件103之半導體晶圓101之背面而達到完成厚度。於半導體晶圓101之薄化結束時,靠近並未形成有第一半導體元件103之半導體晶圓101之背面之位置,會露出形成於溝槽201之區域中之第二絕緣樹脂層413。如圖25所示,沿著形成於半導體晶圓101之元件區域之邊界線,藉由切割抗焊層436、絕緣膜434、第二絕緣層429、第四絕緣樹脂層427、第一絕緣層415及第二絕緣樹脂層413以單片化半導體晶圓101,而製作半導體裝置40。
於單片化半導體晶圓101之前,亦可按照需求,於半導體晶圓101之背面藉由絕緣樹脂等物形成絕緣膜並加以固化。於半導體晶圓101之背面形成絕緣膜之場合中,隨著抗焊層436、絕緣膜434、第二絕緣層429、第四絕緣樹脂層427、第一絕緣層415及第二絕緣樹脂層413亦切割半導體晶圓101之背面之絕緣膜,而對半導體晶圓101進行單片化。於半導體晶圓101並未予以形成溝槽201之場合中,於切割時,隨著抗焊層436、絕緣膜434、第二絕緣層429、第四絕緣樹脂層427、第一絕緣層415及第二絕緣樹脂層413亦切割半導體晶圓101。
根據關於本發明之第四實施型態之半導體裝置之製造方法,能夠抑制起因於凸狀電極連接時之晶片彎曲而造成之凸狀電極連接不良及短路,還能夠製造提升良率及信賴性之半導體裝置,此半導體裝置含有三層以上之堆疊晶片,其中含有附帶穿矽導孔之半導體晶片。而且,與關於本發明之實施型
態一及實施型態二之半導體裝置之製造方法同樣地,具有能夠降低製造成本之可能。
其中,參照圖19至圖25,雖然說明關於半導體裝置40之製造方法,此製造方法是於半導體晶圓101之一個元件區域上分別逐一堆疊形成有穿矽導孔之第一半導體晶片403以及形成有第三半導體元件420之第二半導體晶片419,但與上述之關於本發明之實施型態三之半導體裝置之製造方法同樣地,亦可於半導體晶圓101之一個元件區域上,堆疊分別形成有穿矽導孔之多個第一半導體晶片403以及分別形成有第三半導體元件之多個第二半導體晶片419。也就是說,對應半導體晶圓101之一個元件區域,亦可平放並接合多個第一半導體晶片403,且於此些第一半導體晶片上403,亦可分別接合有第二半導體晶片419。
再者,多個半導體晶片包含形成有穿矽導孔之半導體晶片,於半導體晶圓之元件區域上平放並堆疊此些半導體晶片之場合中,一個半導體裝置內中半導體晶片之堆疊數量亦可加以變化。舉例而言,半導體晶圓之一個元件區域上平放二個半導體晶片且經由凸狀電極與半導體晶圓接合之場合中,如圖26所示之關於本發明之一實施型態之半導體裝置40’所示,平放於半導體晶圓101之元件區域上之二個半導體晶片中,其中一個亦可為形成有穿矽導孔之第一半導體晶片403,另一個亦可為形成有第四半導體元件441之第三半導體晶片439。二者亦可經由第一凸狀電極409與半導體晶圓101進行凸狀電極接合。此場合中,形成有穿矽導孔之第一半導體晶片403上,亦可經由第二凸狀電極23接合形成有第三半導體元件420之第二半導體晶片419。
關於本發明之第五實施型態之半導體裝置之製造方法之概要,將一邊參照圖27至圖33一邊說明。關於第五實施型態之半導體裝置之製造方法
與關於第一至第四實施型態之半導體裝置之製造方法相異。半導體晶圓為使用如下之半導體晶圓,此半導體晶圓於各個元件區域形成有第一半導體元件及一端部與第一半導體元件連接之穿矽導孔。以下所說明之關於本發明之第五實施型態之半導體裝置之製造方法中,說明適用一種半導體晶圓之一範例,此半導體晶圓是於上述關於第二實施型態之半導體裝置之製造方法中所使用之半導體晶圓中形成有穿矽導孔。於此,將省略或簡略化與關於第二實施型態之半導體裝置之製造方法重覆之說明。
首先,準備形成有多個元件區域之半導體晶圓501。於此,如圖27所示,於半導體晶圓501形成有露出一端部之嵌入電極503。其中,於半導體晶圓501上形成有第一半導體元件505,此第一半導體元件505電性連接於嵌入電極503所露出之一端部。與關於本發明第二實施型態之半導體裝置之製造方法同樣地,沿著元件區域之邊界線,於半導體晶圓501之形成有第一半導體元件505之表面形成溝槽201。
與關於本發明第二實施型態之半導體裝置之製造方法同樣地,如圖28所示,電極506連接至形成於半導體晶圓501之第一半導體元件且面對半導體晶片105,電極107經由配線而連接至形成於半導體晶片105之第二半導體元件106。經由凸狀電極109電性連接電極506及電極107以接合半導體晶圓501及半導體晶片105。以第一絕緣樹脂層111埋設半導體晶圓501及半導體晶片105之間隙。於半導體晶圓501上形成具有掩埋半導體晶片105之厚度之第二絕緣樹脂層113。
接下來,如圖29所示,藉由背側研磨處理薄化半導體晶片105連帶第二絕緣樹脂層113達到完成厚度。之後,如圖30所示,於半導體晶片105及第二絕緣樹脂層113之研磨表面形成第一絕緣層114。於第一絕緣層114及第二絕緣樹脂層113形成開口部,開口部露出形成於半導體晶圓501上之電極506。於
半導體晶圓501之上表面整面,也就是第一絕緣層114上、藉由開口部而被露出之電極506上以及開口部之側面,藉由半加成法等方式形成導電層。再藉由圖案化,形成埋設於開口部之配線117及與配線117連接之配線507。之後,於配線507上形成絕緣膜508,且於絕緣膜508上形成連接至配線507之端子509。再者,於端子509上塗布抗焊層510之後,開設開口以露出端子509。
接下來,將晶圓載體安裝於靠近形成於半導體晶片105上之端子509之位置,研磨半導體晶圓501至嵌入電極503之另一端部之前,以薄化半導體晶圓501。之後,藉由化學機械平坦化等方法研磨半導體晶圓501,以露出嵌入電極503之另一端部。藉此,嵌入電極503具有做為貫通半導體晶圓501之穿矽導孔之功能。於露出嵌入電極503之另一端部時,靠近並未形成有第一半導體元件505之半導體晶圓501之背面之位置,會露出形成於溝槽201之區域中之第二絕緣樹脂層113,且對應於各個元件區域之半導體晶圓501之側面會受到第二絕緣樹脂層113覆蓋。
接下來,如圖31所示,於半導體晶圓501上形成第二絕緣層512。第二絕緣層512亦可以與第一絕緣層114相同之材料形成。於第二絕緣層512形成露出嵌入電極503之開口後,於第二絕緣層512上形成導電層,此導電層包含連接至嵌入電極503之另一端部之端子511。於導電層亦可形成端子511以外之配線(未繪示),亦可按照需求於半導體晶圓501及導電層之間形成其他用途之配線層。端子511亦可藉由於第二絕緣層512整面塗布導電性材料再加以圖案化之方式形成。再者,於端子511及第二絕緣層512之整面塗布抗焊層513並加以圖案化,以形成露出端子511之開口515。
接下來,如圖32所示,因對於所露出之端子511施加預焊劑處理(有機保焊劑),而亦可按照需求於開口515上形成外部端子517。外部端子517亦可使用焊料做為球柵陣列球體。而且,於半導體晶圓501上形成外部端子
517之後,從靠近半導體晶片105之位置剝離晶圓載體,亦可按照需求於連接至配線507之端子509上形成外部端子519。外部端子519亦可使用焊料做為球柵陣列球體。
之後,如圖33所示,沿著形成於半導體晶圓501之元件區域之邊界線,切割抗焊層510、絕緣膜508、第一絕緣層114、第二絕緣樹脂層113、第二絕緣層512及抗焊層513以單片化半導體晶圓501,而製造堆疊了薄型半導體晶片之封裝上封裝(package on package,POP)型之封裝50。
根據關於本發明之第五實施型態之半導體裝置之製造方法,能夠抑制起因於半導體晶片之間之凸狀電極連接時之晶片彎曲而造成之凸狀電極連接不良及短路,還能夠製造提升良率及信賴性之封裝上封裝型之封裝。
如上說明之關於本發明之第五實施型態之半導體裝置之製造方法中,雖然說明適用一種半導體晶圓之一範例,此半導體晶圓是於關於第二實施型態之半導體裝置之製造方法中所使用之半導體晶圓中形成有穿矽導孔,但亦能夠適用其他種半導體晶圓來製造封裝上封裝型之封裝,此其他種半導體晶圓可為於關於第一實施型態、第三實施型態及第四實施型態之半導體裝置之製造方法中所使用之半導體晶圓中形成有穿矽導孔。
以上,一邊參照圖1A至圖33一邊說明了本發明之實施型態一至五。其中,本發明並非限定於上述之實施型態,在不脫離要旨的範圍中能夠予以適當變更。
10:半導體裝置
101:半導體晶圓
103:第一半導體元件
104:電極
105:半導體晶片
107:電極
111:第一絕緣樹脂層
113:第二絕緣樹脂層
114:第一絕緣層
117:配線
119:配線
120:絕緣膜
121:端子
122:抗焊層
123:外部端子
Claims (20)
- 一種電子結構,包括:第一半導體晶片(403);第二半導體晶片(419);絕緣結構(434,429),具有絕緣結構第一側和與所述絕緣結構第一側相對的絕緣結構第二側,其中所述第二半導體晶片是在所述絕緣結構第二側上;第一端子(435),在所述絕緣結構第一側處;第一配線(433),在所述絕緣結構內並且耦接至所述第一端子;絕緣樹脂層(427),囊封所述第二半導體晶片,所述絕緣樹脂層具有相鄰所述絕緣結構第二側的絕緣樹脂層第一側和與所述絕緣樹脂層第一側相對的絕緣樹脂層第二側,其中所述第一半導體晶片(403)是在所述絕緣樹脂層第二側上且耦接至所述第二半導體晶片(419);第一半導體元件(103),作為半導體晶圓(101)的一部分形成且耦接至所述第一配線(433);以及第二絕緣樹脂層(413),囊封所述第一半導體晶片和所述半導體晶圓的至少部分。
- 如請求項1的電子結構,其中:所述第一半導體元件(103)通過第二配線(431)與所述第一配線(433)耦接,所述第二配線延伸穿過所述絕緣樹脂層(427)。
- 如請求項1的電子結構,其中:所述絕緣結構包括絕緣膜(434)和第二絕緣層(429),所述第二絕緣層(429)插入於所述絕緣樹脂層(427)和所述絕緣膜(434)之間。
- 如請求項1的電子結構,更包括:第一絕緣層(415),插入於所述絕緣樹脂層(427)和所述第二絕緣樹脂層 (413)之間,所述第一絕緣層包括導體路徑,所述第一半導體晶片和所述第二半導體晶片通過所述導體路徑耦接。
- 如請求項1的電子結構,其中:被所述第二絕緣樹脂層(413)所囊封的所述第一半導體晶片(403)和所述半導體晶圓(101)的所述至少部分包括所述第一半導體晶片的側表面和所述半導體晶圓的側表面。
- 如請求項1的電子結構,其中:所述第一半導體晶片(403)和所述第一半導體元件(103)重疊。
- 如請求項1的電子結構,其中:所述第一半導體元件(103)通過第二配線(431)與所述第一配線(433)耦接,所述第二配線延伸穿過所述絕緣樹脂層(427)和所述第二絕緣樹脂層(413)。
- 如請求項1的電子結構,其中:所述第一半導體元件(103)耦接至所述第一半導體晶片(403)。
- 如請求項1的電子結構,其中:所述第一半導體晶片(403)與所述第二半導體晶片(419)和所述第一半導體元件(103)耦接。
- 如請求項1的電子結構,其中:所述半導體晶圓包括第一側和與所述半導體晶圓的所述第一側相對的第二側;所述第一半導體元件(103)設置成靠近所述半導體晶圓的所述第一側;以及所述半導體晶圓的所述第二側從所述第二絕緣樹脂層(413)露出。
- 如請求項1的電子結構,更包括:外部端子(437),耦接至所述第一端子(435)。
- 如請求項11的電子結構,更包括: 抗焊層(436),覆蓋所述第一端子(435)和所述外部端子(437)的部分。
- 一種電子結構,包括:第一半導體晶片(403);第二半導體晶片(419);絕緣結構(434,429),包括:絕緣結構第一側和與所述絕緣結構第一側相對的絕緣結構第二側;第一端子(435),在所述絕緣結構第一側處;以及第一配線(433),在所述絕緣結構內並且耦接至所述第一端子,其中所述第二半導體晶片(419)是在所述絕緣結構第二側上;絕緣樹脂層(427),囊封所述第二半導體晶片,所述絕緣樹脂層具有相鄰所述絕緣結構第二側的絕緣樹脂層第一側和與所述絕緣樹脂層第一側相對的絕緣樹脂層第二側,其中所述第一半導體晶片(403)是在所述絕緣樹脂層第二側上且耦接至所述第二半導體晶片(419);第一半導體元件(103),作為半導體晶圓(101)的一部分形成且通過第二配線(431)與所述第一配線(433)耦接,所述第二配線(431)延伸穿過囊封所述第二半導體晶片的所述絕緣樹脂層(427);以及第二絕緣樹脂層(413),囊封所述第一半導體晶片和所述半導體晶圓的至少部分。
- 如請求項13的電子結構,其中:所述絕緣結構包括絕緣膜(434)和第二絕緣層(429),所述第二絕緣層(429)插入於所述絕緣樹脂層(427)和所述絕緣膜(434)之間。
- 如請求項13的電子結構,更包括:第一絕緣層(415),插入於囊封所述第二半導體晶片的所述絕緣樹脂層(427)和囊封所述第一半導體晶片的所述第二絕緣樹脂層(413)之間,所述第一絕緣層 包括導體路徑,所述第一半導體晶片和所述第二半導體晶片通過所述導體路徑耦接。
- 如請求項13的電子結構,其中:被所述第二絕緣樹脂層(413)所囊封的所述第一半導體晶片(403)和所述半導體晶圓(101)的所述至少部分包括所述第一半導體晶片的側表面和所述半導體晶圓的側表面。
- 如請求項13的電子結構,其中:所述第一半導體晶片(403)與所述第二半導體晶片(419)和所述第一半導體元件(103)耦接。
- 如請求項13的電子結構,其中:所述第一半導體元件(403)的半導體表面自所述第二絕緣樹脂層(413)露出。
- 如請求項13的電子結構,更包括:外部端子(437),耦接至所述第一端子(435)。
- 一種製造電子結構的方法,包括:提供第一半導體晶片(403);提供第二半導體晶片(419);提供絕緣結構(434,429),包括:絕緣結構第一側和與所述絕緣結構第一側相對的絕緣結構第二側;第一端子(435),在所述絕緣結構第一側處;以及第一配線(433),嵌入在所述絕緣結構內並且耦接至所述第一端子;提供所述第二半導體晶片(419)於所述絕緣結構第二側上;提供絕緣樹脂層(427),囊封所述第二半導體晶片(419),所述絕緣樹脂層包括相鄰所述絕緣結構第二側的絕緣樹脂層第一側和與所述絕緣樹脂層第一側相對的絕緣樹脂層第二側; 提供所述第一半導體晶片(403),在所述第一絕緣樹脂層第二側上並且耦接至所述第二半導體晶片;提供第一半導體元件(103),作為半導體晶圓(101)的一部份且與所述第一配線(433)耦接;以及提供第二絕緣樹脂層(413),囊封所述第一半導體晶片和所述半導體晶圓的至少部分。
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Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9349670B2 (en) * | 2014-08-04 | 2016-05-24 | Micron Technology, Inc. | Semiconductor die assemblies with heat sink and associated systems and methods |
US10141368B2 (en) | 2015-03-31 | 2018-11-27 | Hamamatsu Photonics K.K. | Semiconductor device |
JP6421083B2 (ja) | 2015-06-15 | 2018-11-07 | 株式会社東芝 | 半導体装置の製造方法 |
TWI694569B (zh) * | 2016-04-13 | 2020-05-21 | 日商濱松赫德尼古斯股份有限公司 | 半導體裝置 |
WO2017195517A1 (ja) * | 2016-05-09 | 2017-11-16 | 日立化成株式会社 | 半導体装置の製造方法 |
US10504827B2 (en) * | 2016-06-03 | 2019-12-10 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
CN106024657A (zh) * | 2016-06-24 | 2016-10-12 | 南通富士通微电子股份有限公司 | 一种嵌入式封装结构 |
KR20190092399A (ko) * | 2016-12-29 | 2019-08-07 | 인텔 코포레이션 | 웨이퍼-레벨 액티브 다이 및 외부 다이 마운트를 갖는 반도체 패키지 |
US20180374798A1 (en) * | 2017-06-24 | 2018-12-27 | Amkor Technology, Inc. | Semiconductor device having emi shielding structure and related methods |
TWI616999B (zh) * | 2017-07-20 | 2018-03-01 | 華騰國際科技股份有限公司 | 具有堆疊式積體電路晶片之記憶體製作方法 |
US10535591B2 (en) * | 2017-08-10 | 2020-01-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and method of manufacturing the same |
US10665582B2 (en) * | 2017-11-01 | 2020-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor package structure |
TWI825178B (zh) * | 2018-10-29 | 2023-12-11 | 日商索尼半導體解決方案公司 | 攝像裝置 |
TWI670779B (zh) * | 2018-11-16 | 2019-09-01 | 典琦科技股份有限公司 | 晶片封裝體的製造方法 |
JP7270373B2 (ja) | 2018-12-20 | 2023-05-10 | 株式会社岡本工作機械製作所 | 樹脂を含む複合基板の研削方法及び研削装置 |
JP2021048205A (ja) * | 2019-09-17 | 2021-03-25 | キオクシア株式会社 | 半導体装置の製造方法 |
KR20210142465A (ko) * | 2020-05-18 | 2021-11-25 | 삼성전자주식회사 | 반도체 패키지 |
JP7501133B2 (ja) | 2020-06-12 | 2024-06-18 | 株式会社レゾナック | 半導体装置の製造方法 |
US11764164B2 (en) * | 2020-06-15 | 2023-09-19 | Micron Technology, Inc. | Semiconductor device and method of forming the same |
CN113937019A (zh) * | 2020-07-14 | 2022-01-14 | 中芯集成电路(宁波)有限公司上海分公司 | 晶圆级封装方法以及封装结构 |
US11769736B2 (en) | 2021-04-14 | 2023-09-26 | Micron Technology, Inc. | Scribe structure for memory device |
US11715704B2 (en) | 2021-04-14 | 2023-08-01 | Micron Technology, Inc. | Scribe structure for memory device |
US11600578B2 (en) | 2021-04-22 | 2023-03-07 | Micron Technology, Inc. | Scribe structure for memory device |
WO2023007629A1 (ja) * | 2021-07-28 | 2023-02-02 | 昭和電工マテリアルズ株式会社 | 半導体装置の製造方法、及び、半導体装置 |
WO2024052968A1 (ja) * | 2022-09-05 | 2024-03-14 | 株式会社レゾナック | 半導体装置の製造方法、及び構造体 |
WO2024052967A1 (ja) * | 2022-09-05 | 2024-03-14 | 株式会社レゾナック | 半導体装置の製造方法、構造体及び半導体装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004158537A (ja) * | 2002-11-05 | 2004-06-03 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2008235401A (ja) * | 2007-03-19 | 2008-10-02 | Spansion Llc | 半導体装置及びその製造方法 |
JP2010219477A (ja) * | 2009-03-19 | 2010-09-30 | Shinko Electric Ind Co Ltd | 電子部品内蔵配線基板の製造方法 |
US20110186977A1 (en) * | 2010-01-29 | 2011-08-04 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Thin Profile WLCSP with Vertical Interconnect over Package Footprint |
JP2011187800A (ja) * | 2010-03-10 | 2011-09-22 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
TW201308568A (zh) * | 2011-08-10 | 2013-02-16 | Taiwan Semiconductor Mfg | 半導體裝置與半導體裝置的形成方法 |
US20140038353A1 (en) * | 2012-08-03 | 2014-02-06 | Samsung Electronics Co., Ltd. | Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5191405A (en) * | 1988-12-23 | 1993-03-02 | Matsushita Electric Industrial Co., Ltd. | Three-dimensional stacked lsi |
JP3516592B2 (ja) * | 1998-08-18 | 2004-04-05 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
JP4809957B2 (ja) | 1999-02-24 | 2011-11-09 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置の製造方法 |
JP3792954B2 (ja) * | 1999-08-10 | 2006-07-05 | 株式会社東芝 | 半導体装置の製造方法 |
JP2002025948A (ja) * | 2000-07-10 | 2002-01-25 | Canon Inc | ウエハーの分割方法、半導体デバイス、および半導体デバイスの製造方法 |
JP2003188134A (ja) * | 2001-12-17 | 2003-07-04 | Disco Abrasive Syst Ltd | 半導体ウェーハの加工方法 |
CN100461391C (zh) * | 2002-02-04 | 2009-02-11 | 卡西欧计算机株式会社 | 半导体装置 |
TWI234253B (en) * | 2002-05-31 | 2005-06-11 | Fujitsu Ltd | Semiconductor device and manufacturing method thereof |
CN1463038A (zh) * | 2002-05-31 | 2003-12-24 | 富士通株式会社 | 半导体器件及其制造方法 |
JP4441328B2 (ja) * | 2004-05-25 | 2010-03-31 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
TWI427700B (zh) * | 2004-08-20 | 2014-02-21 | Kamiyacho Ip Holdings | 三維積層構造之半導體裝置之製造方法 |
JP2007123524A (ja) * | 2005-10-27 | 2007-05-17 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板 |
US8072059B2 (en) * | 2006-04-19 | 2011-12-06 | Stats Chippac, Ltd. | Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die |
US8193034B2 (en) * | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
JP2008130704A (ja) * | 2006-11-20 | 2008-06-05 | Sony Corp | 半導体装置の製造方法 |
JP2008218926A (ja) * | 2007-03-07 | 2008-09-18 | Spansion Llc | 半導体装置及びその製造方法 |
US7858441B2 (en) * | 2008-12-08 | 2010-12-28 | Stats Chippac, Ltd. | Semiconductor package with semiconductor core structure and method of forming same |
JP2010267653A (ja) | 2009-05-12 | 2010-11-25 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
US8115260B2 (en) * | 2010-01-06 | 2012-02-14 | Fairchild Semiconductor Corporation | Wafer level stack die package |
JP2011243668A (ja) * | 2010-05-17 | 2011-12-01 | Panasonic Corp | 半導体パッケージの製造方法 |
JP2012084780A (ja) | 2010-10-14 | 2012-04-26 | Renesas Electronics Corp | 半導体装置の製造方法 |
US8941222B2 (en) * | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US8648470B2 (en) * | 2011-01-21 | 2014-02-11 | Stats Chippac, Ltd. | Semiconductor device and method of forming FO-WLCSP with multiple encapsulants |
US9748203B2 (en) * | 2011-12-15 | 2017-08-29 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with conductive pillars and method of manufacture thereof |
US9040346B2 (en) * | 2012-05-03 | 2015-05-26 | Infineon Technologies Ag | Semiconductor package and methods of formation thereof |
-
2014
- 2014-09-11 JP JP2014185708A patent/JP2016058655A/ja not_active Withdrawn
-
2015
- 2015-09-02 CN CN201510558038.5A patent/CN105428265B/zh active Active
- 2015-09-02 CN CN201910715828.8A patent/CN110517964B/zh active Active
- 2015-09-04 TW TW109112648A patent/TWI751530B/zh active
- 2015-09-04 TW TW113107537A patent/TW202425105A/zh unknown
- 2015-09-04 TW TW104129281A patent/TWI694548B/zh active
- 2015-09-04 TW TW110145711A patent/TWI836302B/zh active
- 2015-09-09 KR KR1020150127740A patent/KR102450822B1/ko active IP Right Grant
- 2015-09-10 US US14/850,589 patent/US9368474B2/en active Active
-
2022
- 2022-09-28 KR KR1020220123330A patent/KR102620629B1/ko active IP Right Grant
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004158537A (ja) * | 2002-11-05 | 2004-06-03 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2008235401A (ja) * | 2007-03-19 | 2008-10-02 | Spansion Llc | 半導体装置及びその製造方法 |
JP2010219477A (ja) * | 2009-03-19 | 2010-09-30 | Shinko Electric Ind Co Ltd | 電子部品内蔵配線基板の製造方法 |
US20110186977A1 (en) * | 2010-01-29 | 2011-08-04 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Thin Profile WLCSP with Vertical Interconnect over Package Footprint |
TW201140792A (en) * | 2010-01-29 | 2011-11-16 | Stats Chippac Ltd | Semiconductor device and method of forming thin profile WLCSP with vertical interconnect over package footprint |
JP2011187800A (ja) * | 2010-03-10 | 2011-09-22 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
TW201308568A (zh) * | 2011-08-10 | 2013-02-16 | Taiwan Semiconductor Mfg | 半導體裝置與半導體裝置的形成方法 |
US20140038353A1 (en) * | 2012-08-03 | 2014-02-06 | Samsung Electronics Co., Ltd. | Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same |
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KR102450822B1 (ko) | 2022-10-05 |
US20160079204A1 (en) | 2016-03-17 |
TW202213677A (zh) | 2022-04-01 |
KR20160030861A (ko) | 2016-03-21 |
CN105428265B (zh) | 2019-09-06 |
KR102620629B1 (ko) | 2024-01-02 |
JP2016058655A (ja) | 2016-04-21 |
CN105428265A (zh) | 2016-03-23 |
TW201611186A (zh) | 2016-03-16 |
TWI751530B (zh) | 2022-01-01 |
CN110517964A (zh) | 2019-11-29 |
TW202425105A (zh) | 2024-06-16 |
US9368474B2 (en) | 2016-06-14 |
CN110517964B (zh) | 2024-04-30 |
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