TWI616999B - 具有堆疊式積體電路晶片之記憶體製作方法 - Google Patents

具有堆疊式積體電路晶片之記憶體製作方法 Download PDF

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Publication number
TWI616999B
TWI616999B TW106124397A TW106124397A TWI616999B TW I616999 B TWI616999 B TW I616999B TW 106124397 A TW106124397 A TW 106124397A TW 106124397 A TW106124397 A TW 106124397A TW I616999 B TWI616999 B TW I616999B
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Taiwan
Prior art keywords
integrated circuit
metal
wafer
memory
conductive
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TW106124397A
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English (en)
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TW201909363A (zh
Inventor
謝鐵琴
郭豫音
黃錫洋
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華騰國際科技股份有限公司
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Priority to TW106124397A priority Critical patent/TWI616999B/zh
Priority to US15/703,144 priority patent/US9978736B1/en
Application granted granted Critical
Publication of TWI616999B publication Critical patent/TWI616999B/zh
Priority to DE102018112828.2A priority patent/DE102018112828B4/de
Publication of TW201909363A publication Critical patent/TW201909363A/zh

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Abstract

一種具有堆疊式積體電路晶片之記憶體製作方法。首先，將複數個第一焊接結構自第一積體電路晶片上移除。接著，在第一積體電路晶片上形成變異絕緣層。接下來，藉由雷射光束使變異絕緣層形成複數個金屬設置部。之後，在金屬設置部形成複數個晶片導電結構。之後，在晶片導電結構形成複數個焊接結構，並提供一設有複數個焊接結構之第二積體電路晶片。使第二積體電路晶片之焊接結構連結於晶片導電結構，藉以形成一堆疊式積體電路晶片。最後，將堆疊式積體電路晶片連結於一記憶體基板組件，藉以形成一具有堆疊式積體電路晶片之記憶體。

Description

具有堆疊式積體電路晶片之記憶體製作方法
本發明係有關於一種記憶體製作方法，尤其是指一種藉由雷射光束形成金屬設置部之具有堆疊式積體電路晶片之記憶體製作方法。
自八零年代資訊革命開始，大幅地增加傳遞資訊的速度與將低了傳遞資訊的成本。人們只需要藉由個人電腦，並經由網際網路即可與世界上任何一個角落的人傳遞資訊。藉此，顯著地改變人們的生活型態。
其中，個人電腦除了可透過網際網路傳遞資訊以外，還可以進行文書處理、遊戲娛樂與運行程式。為了達到上述功能，必須在電腦主機板裝設記憶體，藉此暫存電腦在運行過程中所產生的資料。因此，記憶體對於電腦來說是不可或缺的電子組件。
為了製作記憶體，人們會將複數個記憶體晶片設置在記憶體電路板上。以現行技術而言，為了增加記憶體容量，雙晶片封裝(Dual Die Package；DDP) 之技術是最廣泛地被實施的技術。其中，為了進行雙晶片封裝，人們會藉由線路重佈(Re-Distribution Layer；RDL)與晶片尺寸構裝(Chip Scale Package；CSP)中之覆晶技術(Flip-Chip)來實現雙晶片封裝。然而，由於線路重佈與覆晶技術之精密度較高且工序較為複雜，因此會支出額外的成本。
有鑒於在先前技術中，以雙晶片封裝之方式製作記憶體時，需藉由線路重佈與覆晶技術，因此增加了製作的難度，而需額外投入較多的成本之問題。
本發明為解決先前技術之問題，所採用之必要技術手段為提供一種具有堆疊式積體電路晶片之記憶體製作方法。首先，提供一第一積體電路晶片，第一積體電路晶片包含有一第一設置面與一設有複數個第一晶片焊接墊之第二設置面，且第二設置面設有複數個連接於第一晶片焊接墊之焊接結構。接著，移除第二設置面之焊接結構。之後，在第一設置面和第二設置面分別形成一第一變異絕緣層和一避開該些第一晶片焊接墊之第二變異絕緣層。
然後，將一雷射光束分別投射在第一變異絕緣層與第二變異絕緣層，藉以使第一變異絕緣層形成複數個易於鍍上金屬之第一金屬設置部，且在第二變異絕緣層鄰近於第一晶片焊接墊處形成複數個電性連接於第一晶片焊接墊，且易於鍍上金屬之第二金屬設置部， 並透過複數個跨接金屬設置部分別連接第一金屬設置部和第二金屬設置部。接著，在第一金屬設置部、第二金屬設置部、第一晶片焊接墊與跨接金屬設置部形成複數個藉由複數個導電材料所構成之晶片導電結構。
之後，在第二金屬設置部與第一晶片焊接墊之晶片導電結構上形成複數個焊接結構。然後，提供一設有複數個焊接結構之第二積體電路晶片，並將第二積體電路晶片之焊接結構連結於第一積體電路晶片之第一金屬設置部之晶片導電結構，藉以形成一堆疊式積體電路晶片。最後，藉由堆疊式積體電路晶片之焊接結構使堆疊式積體電路晶片連結於一記憶體基板組件，藉以形成一具有堆疊式積體電路晶片之記憶體。
在上述必要技術手段的基礎下，上述具有堆疊式積體電路晶片之記憶體製作方法所衍生之一附屬技術手段為在上述步驟中，焊接結構為球柵陣列球狀結構(Ball Grid Array ball；BGA Ball)。
在上述必要技術手段的基礎下，上述具有堆疊式積體電路晶片之記憶體製作方法所衍生之一附屬技術手段為上述步驟中，使各第二金屬設置部包含一連結於各跨接金屬設置部與各第一晶片焊接墊之設置部斜壁，並使晶片導電結構各包含一連接引線、一斜向接觸片與一焊接墊。
連接引線設置於各跨接金屬設置部。斜向接觸片連結於連接引線，並設置於設置部斜壁，用以接觸於第二金屬設置部之晶片導電結構上之各焊接結構。 焊接墊連結於斜向接觸片，並設置於第一晶片焊接墊，用以連結第二金屬設置部與第一晶片焊接墊之晶片導電結構上之各焊接結構。
在上述必要技術手段的基礎下，上述具有堆疊式積體電路晶片之記憶體製作方法所衍生之一附屬技術手段為上述步驟中，晶片導電結構電鍍於第一金屬設置部、第二金屬設置部、第一晶片焊接墊與跨接金屬設置部。
在上述必要技術手段的基礎下，上述具有堆疊式積體電路晶片之記憶體製作方法所衍生之一附屬技術手段為上述步驟中，使導電材料包含一第一導電材料、一第二導電材料與一第三導電材料，且在形成晶片導電結構時，是先在第一金屬設置部、第二金屬設置部、第一晶片焊接墊與跨接金屬設置部形成一藉由第一導電材料所構成之第一導電層。
接著，在第一導電層形成一藉由第二導電材料所構成之第二導電層。最後，在第二導電層形成一藉由第三導電材料所構成之第三導電層，藉以形成些晶片導電結構。其中，第一導電材料為銅，第二導電材料為鎳，第三導電材料為金。
在上述必要技術手段的基礎下，上述具有堆疊式積體電路晶片之記憶體製作方法所衍生之一附屬技術手段為在上述步驟中，第一變異絕緣層與第二變異絕緣層係藉由一難以鍍上金屬之變異絕緣材料所構成，藉以使第一變異絕緣層與第二變異絕緣層受該雷射光束 照射後分別形成第一金屬設置部與第二金屬設置部。
在上述必要技術手段的基礎下，上述具有堆疊式積體電路晶片之記憶體製作方法所衍生之一附屬技術手段為在上述步驟中，變異絕緣材料至少一參雜有至少一種導電金屬之熱塑性聚合物，藉以在第一變異絕緣層與第二變異絕緣層受雷射光束照射時，將熱塑性聚合物加熱至一熱塑溫度而使導電金屬分別匯聚成第一金屬設置部與第二金屬設置部。
在上述必要技術手段的基礎下，上述具有堆疊式積體電路晶片之記憶體製作方法所衍生之一附屬技術手段為在上述步驟中，熱塑性聚合物是由聚碳酸酯(Polycarbonate；PC)、丙烯腈-丁二烯-苯乙烯共聚物(Acrylonitrile Butadiene Styrene；ABS)、聚醯胺(Polyamide；PA)、聚鄰苯二甲醯胺(Polyphthalamide；PPA)、聚對苯二甲酸丁二醇酯(polybutylene terephthalate；PBT)、環烯烴聚合物(Cyclo olefin polymer；COP)、聚苯醚(polyphenylene ether；PPE)、液晶聚合物(Liquid Crystal Polymer；LCP)、聚醚酰亞胺(Polyetherimide；PEI)、聚醚醚酮(polyetheretherketone；PEEK)或聚苯硫醚(Polyphenylene sulfide；PPS)所組成。
在上述必要技術手段的基礎下，上述具有堆疊式積體電路晶片之記憶體製作方法所衍生之一附屬技術手段為在上述步驟中，變異絕緣材料為一觸媒絕緣材料，藉以在第一變異絕緣層與第二變異絕緣層受雷射 光束照射後，並受一催化作業而分別形成第一金屬設置部與第二金屬設置部。其中，觸媒絕緣材料為一光觸媒材料或一熱觸媒材料。
在上述必要技術手段的基礎下，上述具有堆疊式積體電路晶片之記憶體製作方法所衍生之一附屬技術手段為第一積體電路晶片更包含一連結於第一設置面與第二設置面之側邊連結面。在側邊連結面形成一側邊變異絕緣層。將雷射光束投射在側邊變異絕緣層，藉以使第一變異絕緣層、第二變異絕緣層與側邊變異絕緣層形成易於鍍上金屬且連結第一金屬設置部與第二金屬設置部之跨接金屬設置部。
承上所述，在本發明所提供之具有堆疊式積體電路晶片之記憶體製作方法中，會藉由雷射光束在第一積體電路晶片形成第一金屬設置部、第二金屬設置部與跨接金屬設置部，藉此使晶片導電結構連結於第一金屬設置部、第二金屬設置部、第一晶片焊接墊與跨接金屬設置部。另外，藉由焊接結構使第一積體電路晶片連結於第二積體電路晶片，且藉由焊接結構使第一積體電路晶片連結於記憶體基板組件。
相較於先前技術，本發明所提供之具有堆疊式積體電路晶片之記憶體製作方法是藉由雷射光束照射第一變異絕緣層與第二變異絕緣層而形成第一金屬設置部與第二金屬設置部，藉以鍍上晶片導電結構。藉此，取代了先前技術中，需藉由高精密度與高複雜度之線路重佈與覆晶技術來進行晶片封裝，因而降低了製作成本。
100‧‧‧具有堆疊式積體電路晶片之記憶體
1、1a‧‧‧堆疊式積體電路晶片
11、11a‧‧‧第一積體電路晶片
111‧‧‧第一設置面
112‧‧‧第二設置面
1121‧‧‧第一晶片焊接墊
113‧‧‧側邊連結面
114‧‧‧晶片凸塊
12、17、18‧‧‧焊接結構
13‧‧‧第一變異絕緣層
131‧‧‧第一金屬設置部
14‧‧‧第二變異絕緣層
141‧‧‧第二金屬設置部
1411‧‧‧設置部斜壁
15‧‧‧側邊變異絕緣層
151‧‧‧跨接金屬設置部
16‧‧‧晶片導電結構
161‧‧‧連接引線
162‧‧‧斜向接觸片
163‧‧‧焊接墊
19、19a‧‧‧第二積體電路晶片
191‧‧‧第二晶片焊接墊
2‧‧‧記憶體基板組件
3‧‧‧記憶體晶片
L‧‧‧雷射光束
M1‧‧‧第一導電層
M2‧‧‧第二導電層
M3‧‧‧第三導電層
第一圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之具有第一焊接結構之第一積體電路晶片之示意圖；第二圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之移除第一焊接結構之第一積體電路晶片之示意圖；第三圖係顯示第二圖之A-A剖面示意圖；第四圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之鍍有變異絕緣材料之第一積體電路晶片之剖面示意圖；第五圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之鍍有變異絕緣材料之第一積體電路晶片受雷射光束照射之剖面示意圖；第六圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之鍍有變異絕緣材料之第一積體電路晶片受雷射光束照射後之示意圖；第七圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之設有晶片導電結構之第一積體電路晶片之剖面示意圖；第八圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之設有焊接結構之第一積體電路晶片之剖面示意圖； 第九圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之堆疊式積體電路晶片之剖面示意圖；第十圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之堆疊式積體電路晶片設置於基板之剖面示意圖；第十一圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之具有堆疊式積體電路晶片之記憶體之剖面示意圖；第十二圖係顯示本發明第二較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之具有第一焊接結構之第一積體電路晶片之示意圖；以及第十三圖係顯示本發明第二較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之堆疊式積體電路晶片設置於基板之剖面示意圖。
請一併參閱第一圖至第三圖，第一圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之具有第一焊接結構之第一積體電路晶片之示意圖；第二圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之移除第一焊接結構之第一積體電路晶片之示意圖；第三圖係顯示第二圖之A-A剖面示意圖。
如圖所示，本發明第一較佳實施例提供了 一種具有堆疊式積體電路晶片之記憶體之製作方法。首先，提供一包含有一第一設置面111、一相對於第一設置面111且設有複數個焊接結構12之第二設置面112與一連結第一設置面111與第二設置面112之側邊連結面113以及一連結且一體成型於第二設置面112之晶片凸塊114之第一積體電路晶片11。其中，第二設置面112設有複數個第一晶片焊接墊1121，焊接結構12設置於第一晶片焊接墊1121而電性連接於第一積體電路晶片11。接著，將焊接結構12自第二設置面112移除。
在本實施例當中，第一積體電路晶片11為單晶片封裝(Single Die Package；SDP)式晶片，因此設有晶片凸塊114，但在其他實施例當中並不以此為限。此外，在本實施例當中，焊接結構12為球柵陣列球狀結構(Ball Grid Array ball；BGA Ball)，但在其他實施例當中並不以此為限。
請一併參閱第三圖至第五圖，第四圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之鍍有變異絕緣材料之第一積體電路晶片之剖面示意圖；第五圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之鍍有變異絕緣材料之第一積體電路晶片受雷射光束照射之剖面示意圖。
如圖所示，在第一設置面111形成一第一變異絕緣層13。在至少局部之第二設置面112形成一第二變異絕緣層14。其中，第一晶片焊接墊1121外露於第二 變異絕緣層14。在側邊連結面113形成一側邊變異絕緣層15。其中，第一變異絕緣層13、第二變異絕緣層14與側邊變異絕緣層15係由一變異絕緣材料所構成。
在本實施例當中，變異絕緣材料可為至少一參雜至少一種導電金屬之熱塑性聚合物，藉以在第一變異絕緣層13、第二變異絕緣層14與側邊變異絕緣層15分別受一雷射光束L照射時，將熱塑性聚合物加熱至一熱塑溫度而使導電金屬分別匯聚成易於鍍上金屬複數個第一金屬設置部131、複數個鄰近於第一晶片焊接墊1121之第二金屬設置部141與複數個跨接金屬設置部151。
簡單說，變異絕緣材料為配合LDS(Laser Direct Structuring)技術所使用之材料。其中，熱塑性聚合物是由聚碳酸酯(Polycarbonate；PC)、丙烯腈-丁二烯-苯乙烯共聚物(Acrylonitrile Butadiene Styrene；ABS)、聚醯胺(Polyamide；PA)、聚鄰苯二甲醯胺(Polyphthalamide；PPA)、聚對苯二甲酸丁二醇酯(polybutylene terephthalate；PBT)、環烯烴聚合物(Cyclo olefin polymer；COP)、聚苯醚(polyphenylene ether；PPE)、液晶聚合物(Liquid Crystal Polymer；LCP)、聚醚酰亞胺(Polyetherimide；PEI)、聚醚醚酮(polyetheretherketone；PEEK)與聚苯硫醚(Polyphenylene sulfide；PPS)中之至少一者所組成。由於熱塑溫度是根據不同的熱塑性聚合物而有所不同，因此不在此逐一贅述。
在其他實施例當中，變異絕緣材料可為觸 媒絕緣材料，觸媒絕緣材料可為光觸媒材料或熱觸媒材料，藉以在第一變異絕緣層13、第二變異絕緣層14與側邊變異絕緣層15分別受雷射光束L照射後，並受一催化作業，而分別形成第一金屬設置部131、第二金屬設置部141與跨接金屬設置部151。其中，催化作業可為光催化作業、熱催化作業、浸泡式催化作業或濕製程催化作業。
請一併參閱第五圖與第六圖，第六圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之鍍有變異絕緣材料之第一積體電路晶片受雷射光束照射後之示意圖。
如圖所示，將雷射光束L投射在第一變異絕緣層13、第二變異絕緣層14與側邊變異絕緣層15，藉以使第一變異絕緣層13形成第一金屬設置部131，且使第二變異絕緣層14形成電性連接於第一晶片焊接墊1121之第二金屬設置部141，且在第一變異絕緣層13、第二變異絕緣層14與側邊變異絕緣層15形成複數個連結第一金屬設置部131與第二金屬設置部141之跨接金屬設置部151。簡單說，第一金屬設置部131、第二金屬設置部141與跨接金屬設置部151是藉由LDS技術所形成。
此外，第二金屬設置部141包含一連結於跨接金屬設置部151之設置部斜壁1411。簡而言之，第二金屬設置部141為水滴型設置部，但在其他實施例當中，焊接凹槽1411可為圓型設置部或橢圓型設置部。另外，第一金屬設置部131可為水滴型設置部，但在其他實施例 當中，第一金屬設置部131可為圓型設置部或橢圓型設置部。。順帶一提，在跨接金屬設置部151鄰近於第二設置面112與側邊連結面113之接壤處以及在跨接金屬設置部151鄰近於第二設置面112與側邊連結面113之接壤處為圓角，但在其他實施例中並不以此為限。
請參閱第七圖，第七圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之設有晶片導電結構之第一積體電路晶片之剖面示意圖。如圖所示，在第一金屬設置部131、第二金屬設置部141、第一晶片焊接墊1121與跨接金屬設置部151形成複數個藉由三個導電材料所電鍍而成之晶片導電結構16，並使晶片導電結構16包含一連接引線161、一斜向接觸片162與一焊接墊163。
連接引線161設置於跨接金屬設置部151。斜向接觸片162連結於連接引線161，並設置於凹槽斜壁14111。焊接墊163連結於斜向接觸片162，並設置於第一晶片焊接墊1121。由於在跨接金屬設置部151鄰近於第二設置面112與側邊連結面113之接壤處以及在跨接金屬設置部151鄰近於第二設置面112與側邊連結面113之接壤處為圓角，因而可以減少連接引線161斷裂的機率。
其中，導電材料包含一第一導電材料、一第二導電材料與一第三導電材料，且是先在第一金屬設置部131、第二金屬設置部141、第一晶片焊接墊1121與跨接金屬設置部151形成一藉由第一導電材料所構成之第一導電層M1。在本實施例中，第一導電材料為銅。接 著，在第一導電層M1形成一藉由第二導電材料所構成之第二導電層M2。在本實施例中，第二導電材料為鎳。接著，在第二導電層M2形成一藉由第三導電材料所構成之第三導電層M3，藉以形成晶片導電結構16。在本實施例中，第三導電材料為金。
請參閱第八圖，第八圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之設有焊接結構之第一積體電路晶片之剖面示意圖。如圖所示，在晶片導電結構16形成複數個鄰近於第二金屬設置部141與第一晶片焊接墊1121而設置之焊接結構17。其中，焊接結構17是接觸於斜向接觸片162與焊接墊163。在本實施例當中，焊接結構17為球柵陣列球狀結構，但在其他實施例當中並不以此為限。由於第二金屬設置部141為水滴型設置部，因而增加了晶片導電結構16與焊接結構17接觸面積，進而防止晶片導電結構16與焊接結構17接觸不良或分離。
請參閱第九圖，第九圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之堆疊式積體電路晶片之剖面示意圖。如圖所示，提供一設有複數個焊接結構18之第二積體電路晶片19，並使焊接結構18鄰近於第一金屬設置部131而連結於晶片導電結構16，藉以形成一堆疊式積體電路晶片1。
其中，第二積體電路晶片19設有複數個第二晶片焊接墊191，焊接結構18電性連接於第二晶片焊接墊191。在本實施例當中，第二積體電路晶片19為單晶片 封裝式晶片，但在其他實施例當中並不以此為限。此外，在本實施例當中，焊接結構18為球柵陣列球狀結構，但在其他實施例當中並不以此為限。
請一併參閱第十圖與第十一圖，第十圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之堆疊式積體電路晶片設置於基板之剖面示意圖；第十一圖係顯示本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之具有堆疊式積體電路晶片之記憶體之剖面示意圖。如圖所示，重複上述步驟，藉以形成複數個堆疊式積體電路晶片1。
接著，藉由堆疊式積體電路晶片1之焊接結構17將各堆疊式積體電路晶片1連結於一設有一記憶體晶片3之記憶體基板組件2，藉以形成一具有堆疊式積體電路晶片之記憶體100。在本實施例當中，記憶體晶片3可為先進記憶體緩衝器晶片(Advanced Memory Buffer；AMB)，具有堆疊式積體電路晶片之記憶體100可為動態隨機存取記憶體(Dynamic Random Access Memory；DRAM)，但在其他實施例當中，並不以此為限。
請一併參閱第十二圖與第十三圖，第十二圖係顯示本發明第二較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法之具有第一焊接結構之第一積體電路晶片之示意圖；第十三圖係顯示本發明第二較佳實施例所提供之具有堆疊式積體電路晶片之記憶體 製作方法之堆疊式積體電路晶片設置於基板之剖面示意圖。
如圖所示，本發明第二較佳實施例提供了一種具有堆疊式積體電路晶片之記憶體之製作方法。本發明第二較佳實施例所提供之具有堆疊式積體電路晶片之記憶體之製作方法與本發明第一較佳實施例所提供之具有堆疊式積體電路晶片之記憶體之製作方法大致相同。不同之處在於本發明第二較佳實施例之堆疊式積體電路晶片1a中之第一積體電路晶片11a與第二積體電路晶片19a為雙晶片封裝(Dual Die Package；DDP)式晶片，因此不具有本發明第一較佳實施例之晶片凸塊114(顯示於第一圖至第十一圖)。
綜上所述，在本發明較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法中，是先在第一積體電路晶片形成一由變異絕緣材料所構成之第一變異絕緣層、第二變異絕緣層與側邊變異絕緣層。接著，將雷射光束照射在第一變異絕緣層、第二變異絕緣層與側邊變異絕緣層而形成第一金屬設置部、第二金屬設置部與跨接金屬設置部。接著，依序將銅、鎳與金鍍在第一金屬設置部、第二金屬設置部、第一晶片焊接墊與跨接金屬設置部，進而形成晶片導電結構。
接著，將焊接結構焊接於第二金屬設置部與第一晶片焊接墊上之晶片導電結構，並在第一金屬設置部上藉由焊接結構連結第二積體電路晶片，藉以形成堆疊式積體電路晶片。最後，藉由位於第二金屬設置部 之晶片導電結構之焊接結構將複數個堆疊式積體電路晶片連結於記憶體基板組件，藉以形成具有堆疊式積體電路晶片之記憶體。
相較於先前技術，本發明較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法取代先前技術中，雙晶片封裝需藉由高精密度與高複雜度之線路重佈與覆晶技術來進行。藉此，藉由本發明較佳實施例所提供之具有堆疊式積體電路晶片之記憶體製作方法進行記憶體製作可避免高額的成本。
藉由以上較佳具體實施例之詳述，係希望能更加清楚描述本發明之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。
11‧‧‧第一積體電路晶片
111‧‧‧第一設置面
1121‧‧‧第一晶片焊接墊
113‧‧‧側邊連結面
114‧‧‧晶片凸塊
13‧‧‧第一變異絕緣層
131‧‧‧第一金屬設置部
141‧‧‧第二金屬設置部
1411‧‧‧設置部斜壁
15‧‧‧側邊變異絕緣層
151‧‧‧跨接金屬設置部
L‧‧‧雷射光束

Claims (14)

  1. 一種具有堆疊式積體電路晶片之記憶體製作方法，包含以下步驟：(a)提供一第一積體電路晶片，該第一積體電路晶片包含有一第一設置面與一設有複數個第一晶片焊接墊之第二設置面，且該第二設置面設有複數個電性連接於該些第一晶片焊接墊之焊接結構；(b)移除該第二設置面之該些焊接結構；(c)在該第一設置面和該第二設置面分別形成一第一變異絕緣層和一避開該些第一晶片焊接墊之第二變異絕緣層；(d)將一雷射光束分別投射在該第一變異絕緣層與該第二變異絕緣層，藉以使該第一變異絕緣層形成複數個易於鍍上金屬之第一金屬設置部，且在該第二變異絕緣層鄰近於該些第一晶片焊接墊處形成複數個電性連接於該些第一晶片焊接墊且易於鍍上金屬之第二金屬設置部，並透過複數個跨接金屬設置部分別連接該些第一金屬設置部和該些第二金屬設置部；(e)在該些第一晶片焊接墊、該些第一金屬設置部、該些第二金屬設置部與該些跨接金屬設置部形成複數個藉由複數個導電材料所構成之晶片導電結構；(f)在該些第二金屬設置部與該些第一晶片焊接墊之該些晶片導電結構上形成複數個焊接結構；(g)提供一電性連接複數個焊接結構之第二積體電路晶片，並將該第二積體電路晶片之該些焊接結構連結於 該第一積體電路晶片之該些第一金屬設置部之該些晶片導電結構，藉以形成一堆疊式積體電路晶片；以及(h)藉由該堆疊式積體電路晶片之該些第二金屬設置部與該些第一晶片焊接墊之該些晶片導電結構上之該些焊接結構使該堆疊式積體電路晶片連結於一記憶體基板組件，藉以形成一具有堆疊式積體電路晶片之記憶體。
  2. 如申請專利範圍第1項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，在該步驟(a)、步驟(b)、步驟(f)與步驟(g)中，各該些焊接結構中之至少一者係一球柵陣列球狀結構(Ball Grid Array ball；BGA Ball)。
  3. 如申請專利範圍第1項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，在該步驟(d)中，使各該些第二金屬設置部包含一一連結於各該些跨接金屬設置部與各該些第一晶片焊接墊之設置部斜壁，在該步驟(e)中，使該些晶片導電結構各包含：一連接引線，係設置於各該些跨接金屬設置部；一斜向接觸片，係連結於該連接引線，並設置於該設置部凹槽斜壁，用以接觸於該些第二金屬設置部之該些晶片導電結構上之各該些焊接結構；以及一焊接墊，係連結於該斜向接觸片，並電性連接於各該 些第一晶片焊接墊，用以連結各該些第二金屬設置部與各該些第一晶片焊接墊之各該些晶片導電結構上之各該些焊接結構。
  4. 如申請專利範圍第1項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，在該步驟(e)中，該些晶片導電結構係電鍍於該些第一金屬設置部、該些第二金屬設置部、該些第一晶片焊接墊與該些跨接金屬設置部。
  5. 如申請專利範圍第1項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，在該步驟(e)中，使該些導電材料包含一第一導電材料、一第二導電材料與一第三導電材料，且在該步驟(e)中更包含以下步驟：(e1)在該些第一金屬設置部、該些第二金屬設置部、該些第一晶片焊接墊與該些跨接金屬設置部形成一藉由該第一導電材料所構成之第一導電層；(e2)在該第一導電層形成一藉由該第二導電材料所構成之第二導電層；以及(e3)在該第二導電層形成一藉由該第三導電材料所構成之第三導電層，藉以形成各該些晶片導電結構。
  6. 如申請專利範圍第5項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，在該步驟(e1)中，該第一導電材料為銅。
  7. 如申請專利範圍第5項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，在該步驟(e2)中，該第二導電材料為鎳。
  8. 如申請專利範圍第5項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，在該步驟(e3)中，該第三導電材料為金。
  9. 如申請專利範圍第1項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，在該步驟(c)中，該第一變異絕緣層與該第二變異絕緣層係藉由一難以鍍上金屬之變異絕緣材料所構成，藉以使該第一變異絕緣層與該第二變異絕緣層受該雷射光束照射後分別形成該些第一金屬設置部與該些第二金屬設置部。
  10. 如申請專利範圍第9項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，在該步驟(c)中，該變異絕緣材料係至少一參雜有至少一種導電金屬之熱塑性聚合物，藉以在該第一變異絕緣層與該第二變異絕緣層受該雷射光束照射時，將該熱塑性聚合物加熱至一熱塑溫度而使該至少一種導電金屬分別匯聚成該些第一金屬設置部與該些第二金屬設置部。
  11. 如申請專利範圍第10項所述之具有堆疊式 積體電路晶片之記憶體製作方法，其中，該熱塑性聚合物係由聚碳酸酯(Polycarbonate；PC)、丙烯腈-丁二烯-苯乙烯共聚物(Acrylonitrile Butadiene Styrene；ABS)、聚醯胺(Polyamide；PA)、聚鄰苯二甲醯胺(Polyphthalamide；PPA)、聚對苯二甲酸丁二醇酯(polybutylene terephthalate；PBT)、環烯烴聚合物(Cyclo olefin polymer；COP)、聚苯醚(polyphenylene ether；PPE)、液晶聚合物(Liquid Crystal Polymer；LCP)、聚醚酰亞胺(Polyetherimide；PEI)、聚醚醚酮(polyetheretherketone；PEEK)與聚苯硫醚(Polyphenylene sulfide；PPS)中之至少一者所組成。
  12. 如申請專利範圍第9項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，在該步驟(b)中，該變異絕緣材料係一觸媒絕緣材料，藉以在該第一變異絕緣層與該第二變異絕緣層受該雷射光束照射後，並受一催化作業而分別形成該些第一金屬設置部與該些第二金屬設置部。
  13. 如申請專利範圍第12項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，該觸媒絕緣材料係一光觸媒材料與一熱觸媒材料中之至少一者。
  14. 如申請專利範圍第1項所述之具有堆疊式積體電路晶片之記憶體製作方法，其中，在該步驟(a)中， 該第一積體電路晶片更包含一連結於該第一設置面與該第二設置面之側邊連結面，該步驟(c)之中包含一步驟(c1)，該步驟(d)之中包含一步驟(d1)：(c1)在該側邊連結面形成一側邊變異絕緣層；以及(d1)將該雷射光束投射在該側邊變異絕緣層，藉以使該第一變異絕緣層、該第二變異絕緣層與該側邊變異絕緣層形成該些易於鍍上金屬且連結該些第一金屬設置部與該些第二金屬設置部之跨接金屬設置部。
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