CN106206520A - 集成电路元件、其形成方法及封装组件 - Google Patents

集成电路元件、其形成方法及封装组件 Download PDF

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Publication number
CN106206520A
CN106206520A CN201610674177.9A CN201610674177A CN106206520A CN 106206520 A CN106206520 A CN 106206520A CN 201610674177 A CN201610674177 A CN 201610674177A CN 106206520 A CN106206520 A CN 106206520A
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China
Prior art keywords
layer
projection cube
cube structure
substrate
sidewall
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CN201610674177.9A
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English (en)
Inventor
黄见翎
吴逸文
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN106206520A publication Critical patent/CN106206520A/zh
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Abstract

本发明提供用于铜柱凸块技术的L型侧壁保护工艺，L型侧壁保护结构由至少一非金属材料层形成。本发明还提供一种集成电路元件、其形成方法及封装组件，该集成电路元件包括：一凸块下金属层和一凸块结构，设置于一半导体基底上，其中该凸块结构包括一顶部表面及一侧壁表面，且凸块结构包括一导电柱以及一焊锡层在该导电柱之上，该半导体基底包括一表面区邻接凸块结构的侧壁表面，凸块下金属层设置于凸块结构与半导体基底之间，且凸块下金属层的侧壁和凸块结构的侧壁组成一垂直于半导体基底的表面的平面；以及一L型保护结构，覆盖凸块结构的侧壁表面，且延伸至半导体基底的表面区。本发明可以应用在微细间距的凸块架构。

Description

集成电路元件、其形成方法及封装组件
本申请是申请号为201010529468.1、申请日为2010年10月29日、发明名称为“集成电路元件、其形成方法及封装组件”的发明专利申请的分案申请。
技术领域
本发明涉及集成电路的制造，特别涉及在集成电路元件中的凸块结构。
背景技术
现代的集成电路是由数百万计的有源元件形成，例如晶体管与电容器，这些元件最初是互相隔绝的，但是之后会互相连接在一起，形成功能性的电路。典型的内连线结构包含横向的内连线，例如金属线(导线)，以及垂直的内连线，例如导孔与接点，内连线对于现代集成电路的密度与效能的限制越来越具有决定性。在内连线结构的顶端上会形成接合垫(bond pad)，并且接合垫在个别芯片的表面上会暴露出来，经由接合垫可形成连接芯片至封装基底或其他晶粒的电性连接，接合垫可用在导线接合或倒装芯片接合。
倒装芯片封装技术使用凸块建立在芯片的输入/输出垫片(I/O pad)与基底或封装体的导线架(lead frame)之间的电性接触。在结构上，凸块实际上含有凸块本身，以及位于凸块与输入/输出垫片之间所谓的凸块下金属层(under bump metallurgy；UBM)。凸块下金属层一般含有粘着层、阻挡层以及润湿层(wetting layer)，依序排列在输入/输出垫片上。凸块本身基于其使用的材料可分类为焊锡凸块、金凸块、铜柱凸块以及具有混合金属的凸块。近年来，铜柱凸块技术已经被提出，其取代焊锡凸块的使用，使得电子元件通过铜柱凸块连接至基底，其可具有最小机率的凸块架桥，因而达到较细微的间距，降低电路的电容负载，并且让电子元件可在较高的频率下执行。
铜柱凸块倒装芯片组件具有以下优点：(1)较佳的热/电子效能，(2)较高的电流承载容积，(3)对于电子迁移具有较佳的阻抗，因此可延长凸块的寿命，(4)在铜柱凸块之间具有较小的铸造空隙，较一致的间隙。此外，通过使用铜柱控制的焊锡散布，消除无铅珠状物的设计，可达到较低成本的基底。然而，铜在制造过程中容易氧化，氧化的铜柱会导致电子元件对基底的粘着性变差，较差的粘着性会导致较高的漏电流而造成严重的可靠度问题。氧化的铜柱也会导致底部填胶沿着底部填胶与铜柱之间的界面裂开，此裂缝可能会蔓延至底下的低介电常数介电层，或者蔓延至用于接合铜柱至基底的焊锡。因此，需要侧壁保护层来避免铜氧化，但是传统处理铜柱侧壁的方法会遭受较高制造成本以及界面脱层问题。目前使用化学浸锡工艺(immersion tin process)在铜柱侧壁上提供锡层，但是仍然有制造成本、锡与底部填胶之间的粘着力，以及焊锡润湿至侧壁上的问题产生，其对于新世代芯片的微细间距封装技术是一种挑战。
发明内容
为克服现有技术中的缺陷，在一实施例中，提供集成电路元件，包括：一凸块下金属层和一凸块结构，设置于一半导体基底上，其中该凸块结构包括一顶部表面及一侧壁表面，且该凸块结构包括一导电柱以及一焊锡层在该导电柱之上，该半导体基底包括一表面区邻接该凸块结构的该侧壁表面，该凸块下金属层设置于该凸块结构与该半导体基底之间，且该凸块下金属层的侧壁和该凸块结构的侧壁组成一垂直于该半导体基底的表面的平面；以及一L型保护结构，覆盖该凸块结构的该侧壁表面，且延伸至该半导体基底的该表面区，其中该L型保护结构由一非金属材料层形成，且该L型保护结构的一上表面高于回焊后的该焊锡层的顶部表面。
在一实施例中，提供集成电路元件，包括凸块结构设置于半导体基底上，其中凸块结构包括顶部表面及侧壁表面，且半导体基底包括表面区邻接凸块结构的侧壁表面，以及L型保护结构覆盖凸块结构的侧壁表面，且延伸至半导体基底的表面区，其中L型保护结构由非金属材料层形成。
在一实施例中，提供封装组件，包括：一第一基底；一凸块下金属层和一凸块结构，设置于该第一基底上，其中该凸块结构包括一凸块下金属层设置于该第一基底上，铜柱设置于该凸块下金属层上，以及一焊锡层设置于该铜柱之上，且该凸块结构具有一顶部表面以及一侧壁表面邻接该第一基底的一表面区，该凸块下金属层设置于该凸块结构与该第一基底之间，且该凸块下金属层的侧壁和该凸块结构的侧壁组成一垂直于该第一基底的表面的平面；一L型保护结构，覆盖该凸块结构的该侧壁表面，且延伸至该第一基底的该表面区，其中该L型保护结构由一非金属材料层形成，且该L型保护结构的一上表面高于回焊后的该焊锡层的顶部表面；一第二基底；以及一接合焊锡层，设置于该第二基底与该凸块结构之间。
在一实施例中，提供封装组件，包括第一基底，凸块结构设置于第一基底上，其中凸块结构包括凸块下金属层设置于第一基底上，以及铜柱设置于凸块下金属层上，且凸块结构具有侧壁表面邻接第一基底的表面区，L型保护结构覆盖凸块结构的侧壁表面，且延伸至第一基底的表面区，其中L型保护结构由非金属材料层形成，此外，还包括第二基底，以及接合焊锡层设置在第二基底与凸块结构之间。
在一实施例中，提供形成集成电路元件的方法，包括：形成一凸块下金属层和一凸块结构在一半导体基底上，其中该凸块结构具有一顶部表面及一侧壁表面，且该凸块结构包括一导电柱以及一焊锡层在该导电柱之上，该半导体基底具有一表面区未被该凸块结构覆盖，该凸块下金属层形成于该凸块结构与该半导体基底之间，且该凸块下金属层的侧壁和该凸块结构的侧壁组成一垂直于该半导体基底的表面的平面；形成一非金属保护层在该凸块结构的该顶部表面与该侧壁表面上，以及该半导体基底的该表面区上；以及从该凸块结构的该顶部表面移除该非金属保护层，使得该非金属保护层的一残余部分形成一L型保护结构，并在该焊锡层上进行回焊工艺，其中该L型保护结构的一上表面高于该焊锡层的顶部表面。
在一实施例中，提供形成集成电路元件的方法，包括在半导体基底上形成凸块结构，其中凸块结构具有顶部表面及侧壁表面，且半导体基底具有未被凸块结构覆盖的表面区，在凸块结构的顶部表面与侧壁表面上，以及半导体基底的表面区上形成非金属保护层，以及从凸块结构的顶部表面移除非金属保护层，使得非金属保护层的残余部分形成L型保护结构。
本发明可以应用在微细间距的凸块架构。
为了让本发明的上述目的、特征、及优点能更明显易懂，以下配合附图，进行详细说明。
附图说明
图1A至图1F显示依据一示范性实施例，在铜柱凸块工艺的各阶段中，半导体元件的一部分的剖面示意图。
图2A至图2E显示依据一示范性实施例，在铜柱凸块工艺的各阶段中，半导体元件的一部分的剖面示意图。
图3A至图3G显示依据一示范性实施例，在铜柱凸块工艺的各阶段中，半导体元件的一部分的剖面示意图。
图4A至图4E显示依据一示范性实施例，在铜柱凸块工艺的各阶段中，半导体元件的一部分的剖面示意图。
其中，附图标记说明如下：
10～基底； 10a～基底的表面区； 12～UBM层；
12”～图案化UBM层； 12b～UBM层的侧壁表面；
14～第一UBM层； 14”～图案化第一UBM层；
14b～第一UBM层的侧壁表面； 16～第二UBM层；
16”～图案化第二UBM层； 16b～第二UBM层的侧壁表面；
18～掩模层； 19～掩模层的开口；
20～铜柱； 20a～铜柱的顶部表面；
20b～铜柱的侧壁表面； 22～保护层；
22”～瘦长的侧壁保护结构；22a～L型侧壁间隙壁；
22a1～L型侧壁间隙壁的第一部分；
22a2～L型侧壁间隙壁的第二部分；22b～保护层的开口；
22c～侧壁保护结构的突出部；24、28、42、52～凸块结构；
26～光致抗蚀剂层；27～光致抗蚀剂层的开口；
30～覆盖层； 30b～覆盖层的侧壁表面； 40～焊锡层；
40”～回焊的焊锡层； 40a～焊锡层的顶部表面；
40b～焊锡层的侧壁表面； 100～基底；
102～接合焊锡层； 104～接合结构；
201、202、203、204～封装组件。
具体实施方式
在此所揭示的实施例提供用于铜柱凸块技术的侧壁保护工艺，其中在铜柱凸块侧壁上的L型保护结构是由至少一非金属材料层所形成，例如介电材料层、高分子材料层或前述的组合。在整篇揭示中所使用的名词“铜柱凸块”是关于凸块结构，包括由铜或铜合金形成的导电柱，铜柱凸块可以直接应用在倒装芯片组件或其他类似的应用的电性垫片上或半导体芯片的重分布层上。
在本发明实施例中使用参考资料详细说明本发明，如附图所示，在图式及说明书描述中尽可能地使用相同的标号来表示相同或相似的部分。在图式中，实施例的形状及厚度可能被扩大，以达到方便说明及清楚显示的目的。说明书的描述直接关于依据此揭示所形成的装置的部分元件，或更直接关于与此装置共同操作的元件。可以理解的是，这些元件没有特定的形式，或者可使用各种形式来描绘。再者，当一层被称为在另一层上或在基底上时，这一层可以是直接在其他层上或在基底上，或者也可存在介于中间的其他层。在整篇说明书中所提及的“一实施例”表示与此实施例有关的特定特征、结构或特性是被包含在至少一实施例中。因此，在整篇说明书中所提及的“在一实施例中”不需要都是相同的实施例。另外，在一个或更多实施例中的特定特征、结构或特性可以用任何适合的方式结合。可以理解的是，以下配合的图式并非按尺寸绘制，这些图式仅用于说明本发明。
图1A至图1F显示依据一示范性实施例，在铜柱凸块工艺的各阶段中，半导体元件的一部分的剖面示意图。
参阅图1A，其显示在半导体集成电路制造上用于凸块制造的半导体基底10的一例，并且集成电路可以在基底内以及/或基底上形成。半导体基底被定义成包括半导体材料的任何结构，其包含但不限定于：巨块硅(bulk silicon)、半导体晶片、硅覆盖绝缘层(silicon-on-insulator；SOI)基底或硅锗基底，其他包含第三族(group III)、第四族(group IV)以及第五族(group V)元素的半导体材料也可以使用。基底10可进一步包括多个隔绝特征(未绘出)，例如浅沟槽隔绝(shallow trench isolation：STI)特征或硅的局部氧化(local oxidation of silicon：LOCOS)特征，隔绝特征可以被定义并隔绝各种微电子元件(未绘出)。各种微电子元件可以在基底10内形成，基底10包含晶体管晶体管例如为金属氧化物半导体场效晶体管(metal oxide semiconductor field effect transistor；MOSFET)、互补式金属氧化物半导体(complementary metal oxide semiconductor；CMOS)晶体管、双载子接面晶体管(bipolar junction transistor：BJT)、高电压晶体管、高频晶体管、p沟道以及/或n沟道场效晶体管(PFETs/NFETs)等。此外，基底10还可包含电阻器、二极管、电容器、电感器、熔线以及其他合适的元件。可实施各种工艺形成各种微电子元件，包含沉积、蚀刻、离子注入、光刻、退火以及其他合适的工艺。这些微电子元件互相连接形成集成电路元件，例如逻辑元件、存储器元件(如静态随机存取存储器(SRAM))、射频(radiofrequency；RF)元件、输入/输出(input/output；I/O)元件、系统单芯片(system-on-chip；SOC)元件、前述的组合以及其他合适类型的元件。
基底10更包含在集成电路之上的层间介电层以及金属结构，在金属结构内的层间介电层包含低介电常数介电材料、未掺杂硅玻璃(undoped silicate glass；USG)、氮化硅、氮氧化硅或其他常用的材料，低介电常数介电材料的介电常数值(k值)可低于约3.9或低于约2.8。在金属结构中的金属线可由铜或铜合金形成，在此技术领域中的普通技术人员当可了解金属层的详细形成方式。垫片区(未绘出)是形成在顶端层间介电层内的顶端金属层，其为导电路线的一部分，并且如果需要，其具有经由平坦化工艺，例如化学机械研磨工艺(chemical mechanical polishing；CMP)处理过的暴露表面。适用于垫片区的材料可包含但不限定于例如铜(Cu)、铝(Al)、铝铜(AlCu)、铜合金、或其他可动(mobile)的导电材料。垫片区用在接合工艺中，连接个别芯片中的集成电路至外部特征。
基底10更包含钝化层(passivation layer)(未绘出)形成在垫片区之上，且暴露出一部分的垫片区，用于后续的铜柱凸块工艺。钝化层由非有机材料形成，其选自于未掺杂硅玻璃(USG)、氮化硅、氮氧化硅、氧化硅以及前述的组合。另外，钝化层可由高分子层形成，例如环氧化物(epoxy)、聚酰亚胺(polyimide)、苯环丁烯(benzocyclobutene；BCB)、聚苯恶唑(polybenzoxazole；PBO)以及类似的材料。另外，也可以使用其他相对软性，通常是有机的介电材料。
参阅图1A，其显示凸块下金属层(under-bump-metallurgy；UBM)12的形成，包含在基底10上形成的第一UBM层14以及第二UBM层16。例如，在垫片区暴露出来的部分上形成UBM层12，且延伸至一部分的钝化层。第一UBM层14也称为扩散阻挡层或胶层(glue layer)，由钛(titanium)、钽(tantalum)、氮化钛、氮化钽或类似的材料制成，可通过物理气相沉积(PVD)或溅镀的方式形成。第一UBM层14沉积的厚度介于约至之间，例如厚度约为第二UBM层16是通过物理气相沉积(PVD)或溅镀方式形成在第一UBM层14上的铜晶种层(seed layer)，第二UBM层16可由铜合金形成，其包含银、铬、镍、锡、金以及前述的组合。第二UBM层16沉积的厚度介于约至之间，例如厚度约为在一实施例中，UBM层12包含由Ti形成的第一UBM层14以及由Cu形成的第二UBM层16。
接着，在UBM层12上提供掩模层18，并且将掩模层18图案化，形成开口19，暴露出一部分的UBM层12，用于铜柱凸块(Cu pillar bump)的形成，掩模层18可以是干膜或光致抗蚀剂膜。然后，在开口19内利用焊锡湿润性(solder wettability)部分地或完全地填充导电材料。在一实施例中，于开口19内形成铜层20接触底下的UBM层12，在此揭示整篇中所使用的“铜层”是一层大抵上包含纯元素铜、含有不可避免的杂质的铜以及含有少量元素的铜合金，例如含有钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆的铜合金。铜层的形成方法可包含溅镀、印刷、电镀、无电电镀以及常用的化学气相沉积(CVD)法，例如利用电化学电镀(electro-chemical plating；ECP)形成铜层20。在一示范性实施例中，铜层20的厚度大于25μm。在另一示范性实施例中，铜层20的厚度大于40μm，例如铜层20的厚度可介于约40-50μm之间，约为45μm，或者介于约40-70μm之间，虽然其厚度也可以更大或更小。
参阅图1B，将掩模层18移除，暴露出铜层20的顶部表面20a与侧壁表面20b，以及在铜层20外的UBM层12的一部分，之后铜层20称为铜柱20。在此例中，掩模层18是干膜，可以使用碱性溶液移除。如果掩模层20是由光致抗蚀剂形成，则可以使用丙酮(acetone)、N-甲基吡咯烷酮(n-methyl pyrrolidone；NMP)、二甲基亚砜(dimethyl sulfoxide；DMSO)、二甘醇胺(aminoethoxy ethanol)以及类似的溶剂移除。
然后，如图1C所示，使用铜柱20作为掩模，UBM层12露出来的部分被蚀刻，暴露出下方基底10的表面区10a。在一示范性实施例中，蚀刻UBM层12的步骤为干蚀刻或湿蚀刻，例如使用氨酸(ammonia-based acid)进行的等向性湿蚀刻(通常称为快速蚀刻(flashetching)，因为其时间短暂)，或者干蚀刻工艺，例如标准的反应式离子蚀刻法(RIE)程序。因此，铜柱20底下的图案化UBM层12”具有暴露出来的侧壁表面12b，详细地，图案化的第二UBM层16”具有侧壁表面16b，且图案化的第一UBM层14”具有侧壁表面14b。
参阅图1D，在产生的结构上形成保护层22，例如通过全面性沉积(blanketdeposition)方式形成。详细地，沉积保护层22覆盖铜柱20的顶部表面20a与侧壁表面20b，以及图案化UBM层12”的侧壁表面12b。保护层22是非金属材料层，例如介电材料层、高分子材料层或前述的组合。保护层22可以是单一材料层或多层结构，保护层22的厚度介于约至之间。在一实施例中，保护层22是介电材料层，由氮化硅、氧化硅、氮氧化硅、碳化硅、氧化硅与氮化硅的交错层或前述的组合形成，通过各种沉积技术，包含热氧化法、低压化学气相沉积法(low-pressure chemical vapor deposition；LPCVD)、常压化学气相沉积法(atmospheric-pressure chemical vapor deposition；APCVD)、等离子体增强型化学气相沉积法(plasma-enhanced chemical vapor deposition；PECVD)以及更进步的沉积程序形成。在另一实施例中，保护层22是高分子材料层，由高分子形成，例如环氧化物(epoxy)、聚酰亚胺(polyimide)、苯环丁烯(BCB)、聚苯恶唑(PBO)以及类似的材料，此外也可以使用其他相对软性，通常是有机的介电材料。高分子材料层是软性的，因此具有降低在个别基底上的固有应力的功能。此外，高分子层很容易以数十微米的厚度形成。
接着，参阅图1E，经由化学机械研磨(CMP)工艺，从铜柱20的顶部表面20a移除保护层22的一区域，因而留下所产生的L型侧壁间隙壁22a。L型侧壁间隙壁22a榇垫在侧壁表面20b与12b，且延伸至基底10的邻接表面区10a，L型侧壁间隙壁22a包含沿着侧壁表面20b与12b的第一部分22a1，以及沿着表面区10a的第二部分22a2。L型侧壁间隙壁22a的较上方表面大抵上与铜柱20的顶部表面20a共平面，L型侧壁间隙壁22a之后也称为侧壁保护结构22a。在光刻与掩模技术以及干蚀刻工艺上的进步，例如反应式离子蚀刻法(reactive ionetch；RIE)及其他等离子体蚀刻工艺，可让侧壁保护结构产生。完成的凸块结构24包含铜柱20以及图案化的UBM层12”，L型侧壁间隙壁22a覆盖侧壁表面20b与12b以及邻接的表面区10a。
然后，基底10被切割并封装在封装基底或另一晶粒上，并利用锡球或铜凸块固定在封装基底或其他晶粒的垫片上。图1F显示倒装芯片组件(flip-chip assembly)的一示范性实施例的剖面示意图，在图1E中显示的结构被颠倒翻转并贴附至在底部的另一基底100上。基底100可以是封装基底、电路板(例如印刷电路板(PCB))或其他合适的基底。凸块结构24接触基底100的各种导电附着点，例如在接触垫以及/或导线上的接合焊锡层102，形成接合结构104耦接两个基底10与100。接合焊锡层102可以是共晶焊料(eutectic solder)材料，包含锡、铅、银、铜、镍、铋或前述的组合的合金。示范性的耦接工艺包含助焊剂应用(flux application)、芯片放置(chip placement)、熔融焊锡接点回焊(reflow ofmelting solder joint)以及助焊剂残余物清洁。集成电路基底10、接合结构104以及其他基底100可称为封装组件201，或者在此实施例中，称为倒装芯片封装组件。
此揭示在铜柱侧壁上提供由非金属材料形成的L型侧壁保护结构，避免铜柱侧壁被氧化，以及增加在铜柱侧壁与后续形成的底部填胶材料之间的粘着力。与传统上使用化学浸锡方法并接着进行退火的工艺相比，非金属侧壁保护结构可调整基底应力，避免在回焊工艺期间，焊锡湿润至铜柱而围绕UBM层的周边，并且消除蓝色胶带残留(blue taperesidue)，因此其可以应用在微细间距的凸块架构。
图2A至图2E显示依据另一示范性实施例，在铜柱凸块工艺的各阶段中，半导体元件的一部分的剖面示意图，其中与图1A至图1F的描述相同或相似部分的说明将会省略。
参阅图2A，于沉积保护层22在铜柱20、图案化的UBM层12”以及基底10的邻接表面区10a上之后，在保护层22上涂布光致抗蚀剂层26。然后，如图2B所示，通过激光曝光、烘烤、显影以及/或其他熟知的光刻工艺将光致抗蚀剂层26图案化，提供开口27暴露出保护层22的一部分，其位置在铜柱20的顶部表面20a之上。然后，使用图案化的光致抗蚀剂层作为遮蔽元件，通过湿蚀刻或干蚀刻工艺将保护层22暴露出来的部分蚀刻，在保护层22内提供开口22b，因而暴露出铜柱20的顶部表面20a，如图2C所示。
参阅图2D，移除光致抗蚀剂层26，留下所产生的瘦长侧壁保护结构22”，其包含L型侧壁间隙壁22a以及由L型侧壁间隙壁22a的较上方表面延伸的突出部22c，即瘦长的侧壁保护结构22”具有上表面高于铜柱20的顶部表面20a。完成的凸块结构28包含铜柱20以及图案化的UBM层12”，瘦长的侧壁保护结构22”覆盖侧壁表面20b与12b以及邻接表面区10a。
参阅图2E，基底10被颠倒翻转并贴附至在底部的另一基底100上。凸块结构28接触基底100的各种导电附着点，例如在接触垫以及/或导线上的接合焊锡层102，形成接合结构104耦接两个基底10与100。集成电路基底10、接合结构104以及其他基底100可称为封装组件202，或者在此实施例中，称为倒装芯片封装组件。
图3A至图3G显示依据另一示范性实施例，在铜柱凸块工艺的各阶段中，半导体元件的一部分的剖面示意图，其中与图1A至图1F的描述相同或相似部分的说明将会省略。
参阅图3A，在掩模层18的开口19内形成铜层20之后，在铜柱20的顶部表面20a上形成覆盖层30。覆盖层30可作为阻挡层，避免铜柱内的铜扩散至接合材料，例如焊锡合金中，接合材料是用于接合基底10至外部特征。避免铜的扩散可增加封装体的可靠度与接合强度。覆盖层30可包含镍(Ni)、锡(Sn)、锡铅(SnPb)、金(Au)、银(Ag)、钯(Pd)、铟(In)、镍-钯-金(NiPdAu)、镍金(NiAu)、其他相似的材料，或通过电镀法沉积的合金。覆盖层30的厚度约为1至10μm，在一些实施例中，覆盖层30为多层结构，包含Ni、Au、Pd、Ni基合金、Au基合金或Pd基合金。
然后，在覆盖层30上形成焊锡层40，焊锡层40可由Sn、SnAg、Sn-Pb、SnAgCu(具有Cu重量百分比小于0.3％)、SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、SnZnIn或SnAgSb等制成，通过电镀工艺形成。在一实施例中，焊锡层40是无铅焊锡层，对于无铅焊锡系统而言，焊锡层是具有Ag含量控制在低于3.0重量百分比的SnAg，例如，无铅焊锡层是具有Ag含量控制在约2.5重量百分比的SnAg。
接着，如图3B所示，将掩模层18剥除，暴露出焊锡层的顶部表面40a与侧壁表面40b，以及覆盖层30的侧壁表面30b。然后，如图3C所示，UBM层12暴露出来的部分被蚀刻，暴露出其底下在铜柱20外的表面区10a。之后，如图3D所示，形成保护层22覆盖所产生的结构。于化学机械研磨(CMP)工艺之后，产生如图3E所示的L型侧壁间隙壁22a，因此暴露出焊锡层40的顶部表面40a，L型侧壁间隙壁22a的较上方表面大抵上与焊锡层40的顶部表面40a共平面。
参阅图3F，在焊锡层40上进行回焊工艺，形成回焊的焊锡层40”在覆盖层30上。完成的凸块结构42包含铜柱20、在铜柱20上的覆盖层30、在覆盖层30上的回焊的焊锡层40”，以及在铜柱20底下的图案化UBM层12”，L型侧壁间隙壁22a覆盖侧壁表面40b、30b、20b与12b，以及表面区10a。
然后，基底10被切割并封装至封装基底或另一晶粒上，并利用锡球或铜凸块固定在封装基底或其他晶粒的垫片上。参阅图3G，基底10被颠倒翻转并贴附至在底部的另一基底100上。凸块结构42接触基底100的各种导电附着点，例如在接触垫以及/或导线上的接合焊锡层102，形成接合结构104耦接两个基底10与100。集成电路基底10、接合结构104以及其他基底100可称为封装组件203，或者在此实施例中，称为倒装芯片封装组件。
图4A至图4E显示依据另一示范性实施例，在铜柱凸块工艺的各阶段中，半导体元件的一部分的剖面示意图，其中与图3A至图3G的描述相同或相似部分的说明将会省略。
参阅图4A，在产生的结构上沉积保护层22之后，接着在保护层22上涂布光致抗蚀剂层26。然后，如图4B所示，通过激光曝光、烘烤、显影以及/或其他熟知的光刻工艺将光致抗蚀剂层26图案化，提供开口27暴露出保护层22的一部分，其位置在焊锡层40的顶部表面40a之上。然后，使用图案化的光致抗蚀剂层作为遮蔽元件，通过湿蚀刻或干蚀刻工艺将保护层22暴露出来的部分蚀刻，在保护层22内提供开口22b，因而暴露出焊锡层40的顶部表面40a，如图4C所示。然后，移除光致抗蚀剂层26，产生瘦长的侧壁保护结构22”，其包含L型侧壁间隙壁22a以及从L型侧壁间隙壁22a的较上方表面延伸的突出部22c，即瘦长的侧壁保护结构22”具有上表面高于焊锡层40的顶部表面40a。
参阅图4D，在焊锡层40上进行回焊工艺，形成回焊的焊锡层40”在覆盖层30上。完成的凸块结构52包含铜柱20、在铜柱20上的覆盖层30、在覆盖层30上的回焊的焊锡层40”，以及在铜柱20底下的图案化UBM层12”。瘦长的侧壁保护结构22”覆盖侧壁表面40b、30b、20b与12b，以及表面区10a。瘦长的侧壁保护结构22”的较上方表面不仅高于铜柱20的顶部表面20a，也高于覆盖层30的顶部表面30a，瘦长的侧壁保护结构22”的较上方表面可能等高或高于焊锡层40的顶部表面40a，由焊锡层40的体积与回焊工艺的控制决定。
参阅图4E，基底10被颠倒翻转并贴附至在底部的另一基底100上。凸块结构52接触基底100的各种导电附着点，例如在接触垫以及/或导线上的接合焊锡层102，形成接合结构104耦接两个基底10与100。集成电路基底10、接合结构104以及其他基底100可称为封装组件204，或者在此实施例中，称为倒装芯片封装组件。
虽然本发明已公开优选实施例如上，然其并非用以限定本发明，在此技术领域中的普通技术人员当可了解，在不脱离本发明的精神和范围内，当可做些许更动与润饰。因此，本发明的保护范围当视随附的权利要求所界定的保护范围为准。

Claims (10)

1.一种集成电路元件，包括：
一凸块下金属层和一凸块结构，设置于一半导体基底上，其中该凸块结构包括一顶部表面及一侧壁表面，且该凸块结构包括一导电柱以及一焊锡层在该导电柱之上，该半导体基底包括一表面区邻接该凸块结构的该侧壁表面，该凸块下金属层设置于该凸块结构与该半导体基底之间，且该凸块下金属层的侧壁和该凸块结构的侧壁组成一垂直于该半导体基底的表面的平面；以及
一L型保护结构，覆盖该凸块结构的该侧壁表面，且延伸至该半导体基底的该表面区，
其中该L型保护结构由一非金属材料层形成，且该L型保护结构的一上表面高于回焊后的该焊锡层的顶部表面。
2.如权利要求1所述的集成电路元件，其中该L型保护结构包括一介电层、一高分子层或前述的组合的其中至少一个。
3.如权利要求2所述的集成电路元件，其中该L型保护结构包括氮化硅层、聚酰亚胺层或前述的组合的其中至少一个。
4.如权利要求1所述的集成电路元件，其中该导电柱包含铜。
5.如权利要求4所述的集成电路元件，其中该凸块结构包括一覆盖层在该导电柱上，并且该焊锡层在该覆盖层上，其中该覆盖层包括Ni层。
6.一种封装组件，包括：
一第一基底；
一凸块下金属层和一凸块结构，设置于该第一基底上，其中该凸块结构包括一凸块下金属层设置于该第一基底上，铜柱设置于该凸块下金属层上，以及一焊锡层设置于该铜柱之上，且该凸块结构具有一顶部表面以及一侧壁表面邻接该第一基底的一表面区，该凸块下金属层设置于该凸块结构与该第一基底之间，且该凸块下金属层的侧壁和该凸块结构的侧壁组成一垂直于该第一基底的表面的平面；
一L型保护结构，覆盖该凸块结构的该侧壁表面，且延伸至该第一基底的该表面区，其中该L型保护结构由一非金属材料层形成，且该L型保护结构的一上表面高于回焊后的该焊锡层的顶部表面；
一第二基底；以及
一接合焊锡层，设置于该第二基底与该凸块结构之间。
7.如权利要求6所述的封装组件，其中该L型保护结构包括氮化硅层、聚酰亚胺层或前述的组合的其中至少一个。
8.一种形成集成电路元件的方法，包括：
形成一凸块下金属层和一凸块结构在一半导体基底上，其中该凸块结构具有一顶部表面及一侧壁表面，且该凸块结构包括一导电柱以及一焊锡层在该导电柱之上，该半导体基底具有一表面区未被该凸块结构覆盖，该凸块下金属层形成于该凸块结构与该半导体基底之间，且该凸块下金属层的侧壁和该凸块结构的侧壁组成一垂直于该半导体基底的表面的平面；
形成一非金属保护层在该凸块结构的该顶部表面与该侧壁表面上，以及该半导体基底的该表面区上；以及
从该凸块结构的该顶部表面移除该非金属保护层，使得该非金属保护层的一残余部分形成一L型保护结构，并在该焊锡层上进行回焊工艺，其中该L型保护结构的一上表面高于该焊锡层的顶部表面。
9.如权利要求8所述的形成集成电路元件的方法，其中移除该非金属保护层的步骤包括：
形成一光致抗蚀剂层在该非金属保护层上；
形成一第一开口在该光致抗蚀剂层内；
形成一第二开口在非金属保护层内，其位置对应至该第一开口，暴露出该凸块结构的该顶部表面；以及
移除该光致抗蚀剂层；
其中在移除该非金属保护层的步骤之后，该非金属保护层的一上表面高于该凸块结构的该顶部表面。
10.如权利要求8所述的形成集成电路元件的方法，其中该L型保护结构包括氮化硅层、聚酰亚胺层或前述的组合。
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