CN112310001A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN112310001A
CN112310001A CN202010641308.XA CN202010641308A CN112310001A CN 112310001 A CN112310001 A CN 112310001A CN 202010641308 A CN202010641308 A CN 202010641308A CN 112310001 A CN112310001 A CN 112310001A
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China
Prior art keywords
pads
disposed
connection
connection terminals
semiconductor package
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Pending
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CN202010641308.XA
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English (en)
Inventor
吴周贤
崔佑镇
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN112310001A publication Critical patent/CN112310001A/zh
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Abstract

提供了一种半导体封装件。所述半导体封装件可以包括基底，基底具有其上设置有多个第一垫的上表面和其上设置有多个第二垫的下表面。半导体封装件还可以包括设置在基底的上表面上的半导体芯片，在半导体芯片上设置有连接到多个第一垫中的第一组的连接电极。半导体封装件可以包括具有上表面的中介层，在上表面上设置有多个第一连接垫和多个第二连接垫，多个第一连接垫连接到多个第一垫中的第二组。半导体封装件还可以包括设置在中介层的多个第二连接垫中的一组上的多个连接端子和设置在基底的上表面上的模制材料。

Description

半导体封装件
本申请要求于2019年7月31日在韩国知识产权局提交的第10-2019-0093098号韩国专利申请的优先权的权益，该韩国专利申请的公开内容通过引用被全部包含于此。
技术领域
本发明构思涉及一种半导体封装件。
背景技术
随着电子工业的发展，对电子组件的高性能、高速和小型化的需求越来越多。根据该趋势，在半导体封装件领域中已经出现了诸如用于将多个半导体芯片安装在单个中介层(interposer)或封装基底上的堆叠封装件的封装件以及用于堆叠多个封装件的叠层封装件(package on package，POP)。另一方面，在POP结构中，由于上封装件和下封装件的外部连接端子彼此熔合，因此相邻的外部连接端子会发生短路。
发明内容
本发明构思的一个方面是提供一种能够防止在半导体封装件的外部连接端子之间发生短路的半导体封装件。
根据本发明构思的一个方面，可以公开一种半导体封装件。半导体封装件可以包括基底，基底具有上表面和下表面，在上表面上设置有多个第一垫，在下表面上设置有电连接到多个第一垫的多个第二垫。半导体封装件还可以包括半导体芯片，半导体芯片设置在基底的上表面上，半导体芯片具有第一表面和与第一表面相对的第二表面，在第一表面上设置有连接到多个第一垫中的第一组的连接电极。半导体封装件可以包括设置在半导体芯片的第二表面上的中介层，中介层具有上表面，在上表面上设置有多个第一连接垫和多个第二连接垫，多个第一连接垫连接到多个第一垫中的第二组，中介层具有与上表面相对并面向半导体芯片的第二表面的下表面，并且在至少一个方向上具有比半导体芯片的宽度大的宽度。半导体封装件还可以包括多个连接端子和模制材料，多个连接端子设置在中介层的多个第二连接垫中的一组上，模制材料设置在基底的上表面上。模制材料可以至少覆盖中介层的上表面，并且具有暴露多个连接端子中的两个或更多个相邻连接端子的至少一个沟槽部分。
根据本发明构思的一个方面，可以公开一种半导体封装件。半导体封装件可以包括基底，基底具有上表面和下表面，上表面和下表面中的每个设置有多个垫。半导体封装件还可以包括半导体芯片和中介层，半导体芯片设置在基底的上表面上并电连接到基底，中介层设置在半导体芯片上并具有设置有多个连接垫的上表面。半导体封装件还可以包括多个连接端子和模制材料，多个连接端子设置在中介层的多个连接垫中的至少第一组上，模制材料设置在基底的上表面上。模制材料可以至少覆盖中介层的上表面并具有暴露多个连接端子的至少一个沟槽部分。此外，中介层的多个连接垫中的未设置有多个连接端子的第二组连接垫可以连接到基底。
根据本发明构思的一个方面，可以公开一种半导体封装件。半导体封装件可以包括基底，基底具有上表面和下表面，上表面和下表面中的每个可设置有多个垫。半导体封装件还可以包括半导体芯片，半导体芯片设置在基底的上表面上并具有设置有多个连接垫的上表面。半导体封装件还可以包括多个连接端子和模制材料，多个连接端子设置在半导体芯片的上表面上并连接到多个连接垫中的至少一子集，模制材料具有沟槽部分，沟槽部分至少覆盖半导体芯片的上表面并暴露多个连接端子的至少一部分。
附图说明
通过下面结合附图进行的详细描述，将更清楚地理解本公开的以上和其它方面、特征以及其它优点，在附图中：
图1是示出根据本公开的实施例的半导体封装件的侧剖视图；
图2A至图2D是图1中所示的半导体封装件的俯视平面图并示出了沟槽部分的各种修改的形状；
图3至图8是示出制造图1中所示的半导体封装件的工艺的示意性侧剖视图；
图9至图11是示出第二半导体封装件结合到图1中示出的第一半导体封装件的结构的侧剖视图；
图12A、图12B、图13A和图13B是示出在图9和图10的部分“A”中的第一上连接端子和第二下连接端子熔合之前(a)和熔合之后(b)的状态以解释由于在本公开的实施例中采用的沟槽部分引起的效果的剖视图；
图14是示出连接端子可以在过孔结构和沟槽结构中占据的体积比的曲线图；
图15是示出根据本公开的另一实施例的半导体封装件的侧剖视图；
图16是示出图15中所示的半导体封装件和第二半导体封装件彼此结合的状态的侧剖视图；
图17是示出根据本公开的另一实施例的半导体封装件的侧剖视图；
图18是示出图17中所示的半导体封装件和第二半导体封装件彼此结合的状态的侧剖视图；
图19是示出根据本公开的另一实施例的半导体封装件的侧剖视图；以及
图20是示出图19中所示的半导体封装件和第二半导体封装件彼此结合的状态的侧剖视图。
具体实施方式
在下文中，将参照附图详细地描述本公开的示例实施例。
图1是示出根据本公开的实施例的半导体封装件100A的侧剖视图，并且图2A至图2D是半导体封装件的俯视平面图，其中示出了沟槽部分的各种形状。这里，图1是图2A至图2D的半导体封装件的沿线I-I'截取的剖视图。
参照图1，根据本公开的实施例的半导体封装件(或称为第一半导体封装件)100A包括基底110、半导体芯片120、中介层130和模制材料140。此外，还可以包括下连接端子150。
基底110可以包括多个第一垫(pad，或称为“焊盘”)111、多个第二垫112以及将多个第一垫111电连接到多个第二垫112的布线(未示出)。基底110可以是用于半导体封装件的基底，诸如印刷电路板(PCB)、陶瓷板、带布线板等。例如，基底110可以包括诸如环氧树脂的热固性树脂、诸如聚酰亚胺的热塑性树脂或光敏绝缘层。详细地，基底可以包括诸如半固化片、味之素复合膜(ABF，Ajinomoto build-up film)、FR-4、双马来酰亚胺三嗪(BT)、光可成像介电(PID)树脂等的材料。
多个第一垫111可以设置在基底110的上表面上，并且可以电连接和/或物理连接到半导体芯片120。
多个第一垫111可以具有比多个第二垫112的水平宽度小的水平宽度。因此，当半导体封装件连接到诸如主板的外部板时，可以补偿半导体芯片与外部基底之间的电路宽度的差。
多个第二垫112可以设置在基底110的下表面上，并且可以电连接和/或物理连接到下连接端子150。
多个第二垫112可以通过下连接端子150电连接到诸如主板的外部装置。例如，下连接端子150可以具有倒装芯片连接结构，该倒装芯片连接结构具有焊球、导电凸块或诸如引脚栅格阵列、球栅阵列或平面栅格阵列的网格阵列。这里描述的各种“垫”可以连接到它们所连接到的器件内的内部电路，并且可以将信号和/或供应电压传输到它们所附接到的器件和/或从它们所附接到的器件传输信号和/或供应电压。例如，设置在封装基底上的基底垫可以连接到设置在封装基底内的重布线和其它电线，并且设置在半导体芯片上的垫可以连接到在半导体芯片中的一个或更多个上的集成电路。这里描述的各种垫通常可以在用于连接到端子的位置处具有平坦的表面，该端子用于垫所连接到的器件外部的外部通信。例如，垫可以由诸如金属的导电材料形成。
半导体芯片120可以具有设置有连接电极120P的有效表面和与有效表面相对(opposite，或相反)的无效表面。半导体芯片120可以是逻辑芯片或存储器芯片。例如，半导体芯片120可以包括系统大规模集成(LSI)、逻辑电路、CMOS成像传感器(CIS)、诸如DRAM、SRAM、flash、PRAM、ReRAM、FeRAM、MRAM、高带宽存储器(HBM)、混合存储器立方体(HMC)等的存储器装置或微机电系统(MEMS)装置。
连接构件121可以设置在连接电极120P上。连接构件121可以包括焊球或铜柱，并且半导体芯片120可以通过连接构件121以倒装芯片结合的方式安装在基底110上。例如，在半导体芯片120的有效表面与基底110的上表面之间，可以设置将连接电极120P连接到多个第一垫111的至少一部分(例如，一组)的连接构件121。同时，尽管未在附图中示出，但是围绕连接构件121的底部填充树脂可以形成在半导体芯片120的有效表面与基底110的上表面之间。连接构件121可以由导电材料形成，并且可以是例如导电互连器(例如，导电布线)。
然而，本公开的实施例不限于此，并且在本公开的各种实施例中，半导体芯片120可以以引线键合的方式安装在基底110上。
中介层130可以包括设置在中介层的上表面上的多个第一连接垫131和多个第二连接垫132以及多个上连接端子133(这里也称为“连接端子”或“第一上连接端子”)。中介层130可以具有彼此相对的上表面和下表面。中介层130可以是半导体芯片或者包括半导体材料或绝缘材料的基底。例如，中介层可以包括硅、锗、硅-锗、镓-砷(GaAs)、玻璃、陶瓷等。
尽管在附图中示出了第一连接垫131和第二连接垫132设置在中介层130的上表面上，但是连接垫可以另外设置在中介层130的下表面上。此外，尽管未在附图中示出，但是中介层130可以被理解为包括将多个第一连接垫131和第二连接垫132彼此连接的布线电路(未示出)。
中介层130可以在至少一个方向上具有比半导体芯片120的宽度大的宽度。例如，中介层130可以具有比半导体芯片120的水平宽度120W大的水平宽度130W。因此，可以在中介层130的上表面和/或下表面上充分地确保用于布置多个第一连接垫131和第二连接垫132的空间。
多个第一连接垫131在中介层130的平面上可以设置为靠近边缘，而多个第二连接垫132在中介层130的平面上可以设置在由多个第一连接垫131围绕的内部中。此外，多个第一连接垫131可以设置在中介层130的平面上，并且可以位于在竖直方向上与半导体芯片叠置的区域之外。
上连接端子133可以设置在多个第二连接垫132中的至少一部分(例如，一组)上。未设置有上连接端子133的多个第一连接垫131可以连接到基底110的多个第一垫111中的一部分(例如，一组)。上连接端子133的每个上连接端子可以是例如焊球。多个第一连接垫131可以通过键合线WB连接到例如多个第一垫111中的一部分(例如，一组)。
此外，由于下面描述的原因，上连接端子133之间的距离d可以等于或小于约0.2mm(见图14的描述)。
模制材料140可以至少覆盖中介层130的上表面，并且可以具有暴露上连接端子133中的至少两个或更多个相邻连接端子133的至少一个沟槽部分141。例如，模制材料140可以覆盖基底110的上表面、半导体芯片120的侧表面和中介层130的上表面，并且可以填充半导体芯片120与基底110之间的空间。模制材料140可以包括绝缘材料。例如，可以使用环氧模塑料(EMC)。
沟槽部分141可以具有下表面141B和壁141S，下表面141B相对于模制材料140的最上表面具有台阶部分，壁141S将模制材料140的最上表面连接到沟槽部分141的下表面141B。沟槽部分141可以使用激光钻等形成。
沟槽部分141的下表面141B可以位于第一水平处，该第一水平在高度上比上连接端子133与多个第二连接垫132之间的接触界面的第二水平高。例如，模制材料140的一部分可以与上连接端子133的侧表面的至少一部分物理接触。因此，在半导体封装件翘曲时产生的外部冲击或应力被分散，因此可以改善上连接端子133的连接可靠性。
此外，为了确保用于上连接端子133的占用空间，沟槽部分141的下表面141B可以位于暴露上连接端子133的侧部的至少一部分的第一水平处。此外，沟槽部分141可以基于连接上连接端子133的最大宽度W1的线L暴露上连接端子133的上部区域和上连接端子133的下部区域的至少一部分(见图12A)。例如，上连接端子133的上部区域和上连接端子133的下部区域可以基于连接上连接端子133的相应最大宽度W1的水平线L彼此划定。
为了确保用于上连接端子133的占用空间，沟槽部分141的壁141S可以与相邻设置的上连接端子133间隔开。沟槽部分141的壁141S可以具有渐缩的形状，以与在模制材料140的最上表面处相比，朝向沟槽部分141的下表面141B更靠近相邻设置的上连接端子133。
参照图2A至图2D，沟槽部分141可以具有多个条形状，该多个条形状在平面上以一条线暴露上连接端子133，并且多个条可以彼此连接。
例如，上连接端子133可以布置为多行，并且至少一个沟槽部分141可以包括布置在多行中的每行中并暴露设置在每行中的上连接端子的多个沟槽。
例如，参照图2B，上连接端子133在中介层130的平面上沿中介层130的边缘以至少一个或更多个网格的形式设置，并且至少一个沟槽部分141可以包括多个沟槽，该多个沟槽以网格的形式布置并暴露设置在中介层130的平面的边缘处的多个连接端子133。
图3至图8是示出根据本公开的实施例的制造半导体封装件100A的工艺的示意性侧剖视图。
参照图3，可以提供基底110，该基底110的上表面设置有多个第一垫111，该基底110的下表面设置有电连接到多个第一垫111的多个第二垫112。尽管未在附图中示出，但是基底110还可以包括将第一垫111连接到第二垫112的布线电路。
参照图4，可以在基底110的上表面上设置半导体芯片120。设置在半导体芯片120的下表面上的连接电极120P可以通过连接构件121连接到基底110的上表面上的多个第一垫111。例如，连接构件121可以是铜柱。
参照图5，可以在半导体芯片120的上表面上设置中介层130。半导体芯片120的上表面和中介层130的下表面可以通过附接构件DA结合。附接构件DA可以是例如非导电膜(NCF)、各向异性导电膜(ACF)、UV敏感膜、瞬时粘合剂、热固性粘合剂、激光固化粘合剂、超声固化粘合剂、非导电胶(NCP)等。
可以在中介层130的上表面上设置多个第一连接垫131和第二连接垫132。在中介层130的平面上，与第二连接垫132相比，第一连接垫131可以设置在与半导体芯片120竖直叠置的区域之外，并且第一连接垫131可以通过键合线WB连接到多个第一垫111。此外，可以在与第一连接垫131相比设置在平面的内部区域上的多个第二连接垫132上形成上连接端子133。例如，上连接端子133可以是焊球。
参照图6，可以形成模制材料140，以覆盖基底110、半导体芯片120和中介层130。例如，模制材料140可以是环氧模塑料(EMC)。模制材料140可以形成为覆盖设置在中介层130的上表面上的多个上连接端子133。
参照图7，可以在模制材料140的上部中形成暴露上连接端子133的沟槽部分141。可以使用激光钻等形成沟槽部分141。沟槽部分141的下表面141B可以形成为位于在高度上比上连接端子133的下表面的水平高的水平上(当在侧剖视图中观看时)。因此，上连接端子133的侧部的一部分被模制材料140覆盖，因此可以改善上连接端子133的连接可靠性。
此外，沟槽部分141的壁141S与相邻于其的上连接端子133间隔开，并且可以具有渐缩的形状，以与在模制材料的较高部分处相比，朝向沟槽部分141的下表面141B更靠近相邻设置的上连接端子133。例如，沟槽部分141的水平宽度可以从沟槽部分141的最下部分到沟槽部分141的最上部分增大。
参照图8，可以在设置在基底110的下表面上的多个第二垫112上形成下连接端子150。例如，可以使用回流工艺形成下连接端子150。
图9至图11是示出第二半导体封装件200A和200B结合到图1中所示的第一半导体封装件100A的结构的侧剖视图。
参照图9，第二半导体封装件200A可以包括第二基底210、第二半导体芯片220、第二模制材料240和第二下连接端子250。例如，第二半导体芯片220可以通过键合线221安装在第二基底210上。第二半导体封装件200A的第二下连接端子250可以对应于第一半导体封装件100A的第一上连接端子133并且可以物理/电连接到第一半导体封装件100A的第一上连接端子133。
参照图10，例如，在部分“A”中，第一上连接端子133和第二下连接端子250可以使用回流工艺彼此熔合。
参照图11，在第二半导体封装件200B中，第二半导体芯片220可以以倒装芯片的方式安装在第二基底210上。例如，第二连接构件221可以设置在第二半导体芯片220与第二基底210之间。
图12A、图12B、图13A和图13B是示出在图9和图10的部分“A”中的第一上连接端子133和第二下连接端子250熔合之前(a)和熔合之后(b)的状态以解释由于在本公开的实施例中采用的沟槽部分而引起的效果的剖视图。
参照图12A和图12B，与第一上连接端子133和第二下连接端子250熔合之前(图12A)的第一上连接端子133的最大宽度W1相比，第一上连接端子133和第二下连接端子250熔合之后(图12B)的连接端子C的最大宽度W2可以进一步增大。
沟槽部分141可以基于连接第一上连接端子133的最大宽度W1的线L从模制材料140暴露第一上连接端子133的上部区域和第一上连接端子133的下部区域的至少一部分。因此，在熔合之后，可以充分地确保用于连接端子C的占用空间。
此外，当第一上连接端子133为焊球时，模制材料140可以具有第一上连接端子133穿过其的开口140H，并且开口140H的最大宽度HW可以比第一上连接端子133的最大宽度W1小。
另一方面，参照图13A和图13B，如果第一上连接端子133中的每个通过穿过模制材料140的过孔141'暴露，则在熔合之后(图13B)的连接端子C'的最大宽度W3可以快速增大。在图13A和图13B的示例实施例中，由于在回流工艺中熔融的第一上连接端子133与渐缩的过孔141'的壁141'S紧密接触并且到达过孔141'的上部，因此与图12B的熔合之后的连接端子C的最大宽度W2相比，图13B的熔合之后的连接端子C'的最大宽度W3可以进一步增大。
图14是示出连接端子可以在过孔结构和沟槽结构中占据的体积比(过孔/沟槽)的曲线图。
参照图14，当第一上连接端子133之间的距离为约0.4mm时，过孔结构与沟槽结构的体积比可以为约82％。当第一上连接端子133之间的距离为约0.2mm时，过孔结构与沟槽结构的体积比快速减小到约41％。
因此，当相邻设置的第一上连接端子133之间的距离等于或小于约0.2mm时，充分地确保了通过应用沟槽结构熔合的连接端子的占用空间，因此可以防止和/或抑制熔合的连接端子之间的短路的发生。
图15是示出根据本公开的另一实施例的半导体封装件100B的侧剖视图，并且图16是示出结合到图15中所示的半导体封装件100B的第二半导体封装件200A的侧剖视图。
参照图15和图16，在根据另一实施例的半导体封装件100B中，半导体芯片120可以具有设置有连接电极120P的下表面和设置有连接垫122的上表面。此外，连接垫122中的一部分可以通过键合线WB连接到基底110的第一垫111，而连接垫122中的剩余部分可以连接到上连接端子123。上连接端子123可以容纳第二半导体封装件200A的下连接端子。除非另有具体解释，否则本公开的组件的描述可以参考图1中所示的半导体封装件100A的相同或相似组件的描述。
图17是示出根据本公开的另一实施例的半导体封装件100C的侧剖视图，并且图18是示出结合到图17中所示的半导体封装件100C的第二半导体封装件200A的侧剖视图。
参照图17和图18，在根据本公开的另一实施例的半导体封装件100C中，半导体芯片120可以具有设置有连接电极120P的上表面和与上表面相对并附接到基底110的下表面。连接电极120P中的一部分可以通过键合线WB连接到基底110的第一垫111，而连接电极120P中的剩余部分可以连接到上连接端子123。上连接端子123可以容纳第二半导体封装件200A的下连接端子。除非另有具体解释，否则本公开的组件的描述可以参考图1中所示的半导体封装件100A的相同或相似组件的描述。
图19是示出根据本公开的另一实施例的半导体封装件100D的侧剖视图，图20是示出结合到图19中示出的半导体封装件100D的第二半导体封装件200A的侧剖视图。
参照图19和图20，在根据本公开的另一实施例的半导体封装件100D中，半导体芯片120可以具有设置有连接电极120P的下表面和设置有连接垫122的上表面，并且还可以包括将连接电极120P连接到连接垫122的贯穿电极124。连接垫122可以连接到上连接端子123。因此，上连接端子123可以容纳第二半导体封装件200A的下连接端子，并且可以通过半导体芯片120的贯穿电极124电连接到基底110。除非另有具体解释，否则本公开的组件的描述可以参考图1中所示的半导体封装件100A的相同或相似组件的描述。
如上所述，根据本发明构思的示例实施例，可以提供一种半导体封装件，该半导体封装件通过引入确保用于外部连接端子的占用空间的沟槽部分而能够防止和/或抑制半导体封装件的外部连接端子之间的短路的发生。
尽管已经在上面示出和描述了示例实施例，但是对于本领域技术人员将明显的是，可以在不脱离如由所附权利要求限定的本公开的范围的情况下做出修改和变化。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
基底，具有上表面和下表面，在所述上表面上设置有多个第一垫，在所述下表面上设置有电连接到所述多个第一垫的多个第二垫；
半导体芯片，设置在所述基底的所述上表面上，所述半导体芯片具有第一表面和与所述第一表面相对的第二表面，在所述第一表面上设置有连接到所述多个第一垫中的第一组的连接电极；
中介层，设置在所述半导体芯片的所述第二表面上，所述中介层具有上表面，在所述上表面上设置有多个第一连接垫和多个第二连接垫，所述多个第一连接垫连接到所述多个第一垫中的第二组，所述中介层具有与所述上表面相对并面向所述半导体芯片的所述第二表面的下表面，并且在至少一个方向上具有比所述半导体芯片的宽度大的宽度；
多个连接端子，设置在所述中介层的所述多个第二连接垫中的一组上；以及
模制材料，设置在所述基底的所述上表面上，所述模制材料至少覆盖所述中介层的所述上表面，并且具有暴露所述多个连接端子中的两个或更多个相邻的连接端子的至少一个沟槽部分。
2.根据权利要求1所述的半导体封装件，其中，所述模制材料的最上表面与所述沟槽部分的下表面形成台阶。
3.根据权利要求1所述的半导体封装件，其中，在侧剖视图中，所述沟槽部分的下表面位于第一水平处，所述第一水平在高度上比所述多个连接端子与所述多个第二连接垫之间的接触界面的第二水平高。
4.根据权利要求1所述的半导体封装件，其中，所述多个连接端子中的每个连接端子为焊球，
其中，所述沟槽部分暴露所述多个连接端子的上部区域和所述多个连接端子的下部区域的至少一部分，并且
其中，所述多个连接端子的所述上部区域和所述多个连接端子的所述下部区域基于连接所述多个连接端子的相应最大宽度的水平线彼此划定。
5.根据权利要求1所述的半导体封装件，其中，将所述模制材料的最上表面连接到所述沟槽部分的下表面的所述沟槽部分的壁与所述多个连接端子中的相邻设置的连接端子间隔开。
6.根据权利要求5所述的半导体封装件，其中，所述沟槽部分的所述壁是渐缩的，以与在所述模制材料的所述最上表面处相比，朝向所述沟槽部分的所述下表面更靠近所述相邻设置的连接端子。
7.根据权利要求1所述的半导体封装件，其中，所述多个连接端子布置为多行，并且
所述至少一个沟槽部分包括多个沟槽，所述多个沟槽分别布置为所述多行并暴露设置在所述多行中的所述多个连接端子。
8.根据权利要求1所述的半导体封装件，其中，所述多个连接端子沿所述中介层的边缘以至少一个或更多个网格的形式布置，并且
所述至少一个沟槽部分包括多个沟槽，所述多个沟槽以网格的形式布置并暴露设置在所述中介层的所述边缘处的所述多个连接端子。
9.根据权利要求1所述的半导体封装件，其中，所述多个第一连接垫设置为与所述中介层的平面的边缘相邻，并且所述多个第二连接垫在所述中介层的平面上设置在由所述多个第一连接垫围绕的第一区域中。
10.根据权利要求9所述的半导体封装件，其中，所述多个第一连接垫通过引线键合连接到所述多个第一垫中的所述第二组。
11.根据权利要求9所述的半导体封装件，其中，在侧剖视图中，所述多个第一连接垫在所述中介层上设置在与所述半导体芯片竖直叠置的第二区域之外。
12.根据权利要求1所述的半导体封装件，其中，所述多个连接端子中的彼此相邻设置的一对连接端子之间的距离等于或小于0.2mm。
13.根据权利要求1所述的半导体封装件，其中，所述多个第一垫中的每个垫的宽度比所述多个第二垫中的每个垫的宽度小。
14.根据权利要求1所述的半导体封装件，其中，将所述连接电极连接到所述多个第一垫中的至少一部分的连接构件设置在所述半导体芯片的所述第一表面与所述基底的所述上表面之间。
15.根据权利要求1所述的半导体封装件，其中，附接构件设置在所述半导体芯片的所述第二表面与所述中介层的所述下表面之间。
16.一种半导体封装件，所述半导体封装件包括：
基底，具有上表面和下表面，所述上表面和所述下表面中的每个设置有多个垫；
半导体芯片，设置在所述基底的所述上表面上，并且电连接到所述基底；
中介层，设置在所述半导体芯片上，并且具有设置有多个连接垫的上表面；
多个连接端子，设置在所述中介层的所述多个连接垫中的至少第一组上；以及
模制材料，设置在所述基底的所述上表面上，所述模制材料至少覆盖所述中介层的所述上表面，并且具有暴露所述多个连接端子的至少一个沟槽部分，
其中，所述中介层的所述多个连接垫中的未设置有所述多个连接端子的第二组连接垫连接到所述基底。
17.根据权利要求16所述的半导体封装件，其中，在侧剖视图中，所述沟槽部分的下表面位于第一水平处，所述第一水平在高度上比所述多个连接端子与所述多个连接垫之间的接触界面的第二水平高。
18.根据权利要求16所述的半导体封装件，其中，所述多个连接端子沿所述中介层的边缘以至少一个或更多个网格的形式布置，并且
所述至少一个沟槽部分包括多个沟槽，所述多个沟槽以网格的形式布置并暴露设置在所述中介层的所述边缘上的所述多个连接端子。
19.根据权利要求16所述的半导体封装件，其中，所述多个连接端子中的彼此相邻设置的一对连接端子之间的距离等于或小于0.2mm。
20.一种半导体封装件，所述半导体封装件包括：
基底，具有上表面和下表面，所述上表面和所述下表面中的每个设置有多个垫；
半导体芯片，设置在所述基底的所述上表面上，并且具有设置有多个连接垫的上表面；
多个连接端子，设置在所述半导体芯片的所述上表面上，并且连接到所述多个连接垫中的至少一子集；以及
模制材料，具有沟槽部分，所述沟槽部分至少覆盖所述半导体芯片的所述上表面并且暴露所述多个连接端子的至少一部分。
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