TWI609467B - 封裝結構及成形封裝結構之方法 - Google Patents

封裝結構及成形封裝結構之方法 Download PDF

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TWI609467B
TWI609467B TW102148199A TW102148199A TWI609467B TW I609467 B TWI609467 B TW I609467B TW 102148199 A TW102148199 A TW 102148199A TW 102148199 A TW102148199 A TW 102148199A TW I609467 B TWI609467 B TW I609467B
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metal
metal pad
package structure
conductive
pad
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TW102148199A
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TW201436138A (zh
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余振華
李明機
陳承先
曾裕仁
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台灣積體電路製造股份有限公司
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

封裝結構及成形封裝結構之方法
本發明是有關於一種封裝結構，特別是有關於一種成形封裝結構之方法。
半導體封裝已被連續改善去符合高性能、小尺寸及高速電子器具之需求。如上所述，半導體封裝已從舊式雙直插封裝(dual in-line packages，DIPs)進化成現代化之半導體封裝，例如，CSPs。因此，電子器具(例如，智慧型電話以及平板電腦)能夠使用CSPs而被微型化。
CSPs是特別適合於具有大量插腳於高速運作之一封裝或具有一相對大尺寸晶片之一封裝。雖然CSPs之定義未被確定於半導體工業之中，但小於一半導體晶片之尺寸之大約120%之封裝是典型地被指涉為一CSP。甚至大於一半導體晶片之尺寸之120%之半導體封裝(例如，球形陣列(BGA)封裝、地柵陣列(LGA)封裝以及小外形不含鉛(SON)封裝)可以被認為是一CSP。特別的是，具有焊錫球固定於下表面之球形陣列(BGA)封裝、具有一地柵陣列固定於下表面之地柵陣列(LGA)封裝以及具有兩地柵陣列固定於下表面之小外形不含鉛(SON)封裝係為CSPs之例子。
在一封裝(例如，覆晶晶片級封裝(fcCSP))之中，一積體電路(IC)可以透過線路內連線上之凸塊被固定於一底材 (例如，一印刷電路板(PCB)或其他積體電路載體)。
鑒於較小封裝之需求，降低相鄰凸塊間之距離(亦即，凸塊節距)的努力已被進行。降低凸塊節距之一方法係縮減使用於線路內連線中之金屬線路之寬度。不幸的是，降低金屬線路之寬度可能會導致不利的結果。
本發明基本上採用如下所詳述之特徵以為了要解決上述之問題。
本發明之一實施例提供一種封裝結構，其包括一積體電路晶片，係連結一導電柱；一底材，具有對於每一嵌入金屬線路之一金屬接墊，其中，該金屬接墊之寬度係大於一對應之嵌入金屬線路之寬度；以及一導電材料，係電性連接該導電柱於該金屬接墊。
根據上述之實施例，相鄰之金屬接墊係為交錯排列的。
根據上述之實施例，一金屬氧化物係設置於該導電柱之複數個側壁之上。
根據上述之實施例，該金屬接墊之寬度係小於該導電柱之寬度。
根據上述之實施例，該金屬接墊之長度係介於該導電柱之長度之70%與該導電柱之長度之130%之間。
根據上述之實施例，一模鑄化合物及一底部填充材料之至少一個係繞著該導電柱被設置以及係被設置於該積體電路晶片與該底材之間。
根據上述之實施例，該底材係為一嵌入圖案化製 程底材，以及該導電材料亦係電性連接該導電柱於該嵌入金屬線路。
根據上述之實施例，該金屬線路也可以具有各種 剖面形狀，例如矩形形狀、梯形形狀及倒梯形形狀之至少一種，並且係由銅、鋁、鎳、金及銀之至少一種所構成。
根據上述之實施例，該積體電路晶片上有連結導 電金屬凸塊。
根據上述之實施例，該金屬接墊具有矩形、正方 形、三角形、梯形、六邊形、八邊形、橢圓形、階梯形、菱形、圓角矩形、雙梯形、膠囊型、卵形或個六角端矩形之形狀。
本發明之另一實施例提供一種封裝結構，其包括 一積體電路晶片，係連結一金屬凸塊；一底材，具有對於每一金屬線路之一金屬接墊，其中，該金屬接墊係重疊該金屬線路於一方向之中；以及一導電材料，係電性連接該金屬凸塊於該金屬接墊。
根據上述之實施例，相鄰之金屬接墊係為交錯排 列的，以及該金屬接墊係電性連接該金屬凸塊。
根據上述之實施例，該金屬凸塊包括銅，一銅氧 化物係設置於該金屬凸塊之複數個側壁之上，以及該金屬接墊之長度係介於該金屬凸塊之長度之70%與該金屬凸塊之長度之130%之間。
根據上述之實施例，該底材係為一嵌入圖案化製 程底材。
根據上述之實施例，該金屬接墊之寬度係小於該 金屬凸塊之寬度。
根據上述之實施例，一底部填充材料係繞著該金 屬凸塊被設置以及該底部填充材料係被設置於該積體電路晶片與該底材之間。
本發明之又一種實施例提供一種成形封裝結構之 方法，其包括：成型對於每一嵌入金屬線路之一金屬接墊於一底材之中，其中，該金屬接墊之寬度係大於一對應之嵌入金屬線路之寬度；以及電性連接一積體電路晶片之一導電柱於該金屬接墊。
根據上述之實施例，該成形封裝結構之方法更包 括：成型一接合增進特徵於該金屬接墊之上。
根據上述之實施例，該成形封裝結構之方法更包 括：使相鄰之金屬接墊交錯；以及允許一金屬氧化物去形成於該導電柱之複數個側壁之上。
根據上述之實施例，該成形封裝結構之方法更包 括：使一底部填充材料繞著該導電柱流動以及在該積體電路晶片與該底材之間流動。
為使本發明之上述目的、特徵和優點能更明顯易 懂，下文特舉較佳實施例並配合所附圖式做詳細說明。
10、28、50、200、300‧‧‧封裝結構
12‧‧‧底材
14、32、52‧‧‧導電材料
16、34、76、226、326‧‧‧金屬線路
18、36、58‧‧‧導電柱
20‧‧‧積體電路晶片
22‧‧‧間距
24、42、62、212、312、412‧‧‧凸塊在線路上內連線
26、44、80‧‧‧線寬度
30、56‧‧‧嵌入圖案化製程底材
38、60‧‧‧積體電路晶片
46、48、84、234、334‧‧‧接合區域(接合面積)
54、204、304‧‧‧金屬接墊
64‧‧‧積體電路內連層
66‧‧‧保護層
68‧‧‧緩衝層
70‧‧‧重分佈層
72‧‧‧金屬氧化物
78‧‧‧金屬接墊寬度
82、232、332‧‧‧凸塊至金屬線路距離
86‧‧‧導電柱寬度
88‧‧‧金屬接墊長度
90‧‧‧導電柱長度
92‧‧‧金屬接墊形狀之範例
400‧‧‧接合增進層
402‧‧‧寬度
404‧‧‧輪廓
406‧‧‧間隔距離
408‧‧‧寬度
410‧‧‧長度
500‧‧‧光阻
502‧‧‧金屬
第1圖係顯示具有一半加成製程(SAP)底材之封裝結構之剖面示意圖； 第2圖係顯示相對於來自第1圖之封裝結構之一導電柱與金屬線路圖案之俯視示意圖；第3圖係顯示具有一嵌入圖案化製程底材之一封裝結構之剖面示意圖；第4圖係顯示相對於來自第3圖之封裝結構之一導電柱與金屬線路圖案之俯視示意圖；第5圖係顯示具有一嵌入圖案化製程底材之一封裝結構之剖面示意圖，其中，一金屬接墊係重疊於每一個金屬線路上；第6圖係顯示相對於來自第5圖之封裝結構之一導電柱與金屬接墊及金屬線路圖案之俯視示意圖；第7圖係顯示被使用於第3圖之封裝結構中之其中一個金屬接墊；第8圖係顯示對於金屬接墊之適當形狀之範例；第9圖係顯示成型第5圖之封裝結構之方法之流程圖；第10圖係顯示具有一嵌入圖案化製程底材之一封裝結構之剖面示意圖，其中，一金屬接墊係重疊每一個梯形金屬線路；第11圖係顯示具有一嵌入圖案化製程底材之一封裝結構之剖面示意圖，其中，一金屬接墊係重疊每一個倒梯形金屬線路；第12圖係顯示成型於金屬接墊及金屬線路上之一接合增進層之俯視示意圖；第13圖係顯示具有一嵌入圖案化製程底材之一封裝結構 之剖面示意圖，其中，一接合增進層係成型於金屬接墊及每一個金屬線路之上；第14圖係顯示具有一嵌入圖案化製程底材之一封裝結構之剖面示意圖，其中，一接合增進層係成型於金屬接墊及每一個梯形金屬線路之上；第15圖係顯示具有一嵌入圖案化製程底材之一封裝結構之剖面示意圖，其中，一接合增進層係成型於金屬接墊及每一個倒梯形金屬線路之上；以及第16圖至第18圖係顯示使用於成型如第12圖及第13-15圖中所示之接合增進層之一流程。
茲配合圖式說明本發明之較佳實施例。
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之一較佳實施例的詳細說明中，將可清楚的呈現。以下實施例中所提到的方向用語，例如：上、下、左、右、前或後等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明並非用來限制本發明。
本發明將以一特定背景之實施例來做說明，亦即，合併一凸塊於線路內連線上之一覆晶晶片級封裝(fcCSP)。然而，本發明之概念亦可以被應用於其他的封裝結構、內連線組件或半導體結構之中。
請參閱第1圖，具有一半加成製程(SAP)底材12之封裝結構10是被顯示。一導電材料14(例如，焊錫特徵、焊錫接頭)是電性連接位於底材12上之複數個金屬線路16於導電柱 18，其中，導電柱18是被一積體電路晶片20所連結。倘若金屬凸塊直連(bump on trace，BOT)內連線24中之導電材料14與第1圖中之一鄰接金屬線路16之間的距離22太小，則一不合意之橋接可能會發生於焊接過程之中，並且會導致良率損失。
參閱第2圖，相對於對應導電柱18之複數個金屬線 路16之一圖案之俯視示意圖。當位於第1圖之封裝結構10中之金屬線路16之一線寬度26是被降低至大約15μm或更小時，由於在金屬線路16與底材12之間的有限接觸面積，金屬線路16可能會不利地剝離於底材12。
為了減緩第1圖封裝結構10之橋接問題，如第3圖 所示，運用一嵌入圖案化製程(embedded patterning process，EPP)底材30之封裝結構28可以被使用。在第3圖之中，一導電材料32(例如，焊錫特徵、焊錫接頭)提供底材30中之複數個金屬線路34與導電柱36電性連接，其中，導電柱36與一積體電路晶片38連接。
因為在第3圖中之金屬線路34是被嵌入於底材30 之中，故在凸塊在線路上內連線42中之導電材料32與鄰接金屬線路34之間的距離是相對於第1圖中之距離22被增加。因此，導線橋接的情況可以被避免掉。
如第4圖所示，嵌入之金屬線路34之一線寬度44可 以被降低至大約10μm或更小。然而，如此之做法會縮減在嵌入之金屬線路34與凸塊在線路上內連線42中之導電材料32之間的一接合面積(區域)46。因為在第3圖中之接合面積(區域)46是小於在第1圖中之金屬線路16與導電材料14之間的一接合面 積48，故第3圖中之封裝結構28可能會更容易產生接合疲勞或焊錫裂縫。在此，焊錫裂縫在一接合製程或一可靠度測試過程中可能會形成。
現在請參閱第5圖，一封裝結構50是被繪示。封裝 結構50包括有一導電材料52(亦即，焊錫接合)，其中，導電材料52係電性連接嵌入圖案化製程(embedded patterning process，EPP)底材56中之一金屬接墊54與一積體電路晶片60所連接之一導電柱58。金屬接墊54一般係提供一更為結實與更為可靠之凸塊在線路上內連線62於封裝結構50。
如第5圖所示，積體電路晶片60包括有一積體電路 內連層64、一保護層66及一緩衝層68。在一實際應用之中，積體電路晶片60可以具有額外之層、結構或特徵。然而，為了清楚說明起見，如此額外之層、結構或特徵已被第5圖所省略。
如第5圖所示，積體電路內連層64、保護層66及緩 衝層68係部分地封入及支撐一重分佈層70。在此實施例之中，重分佈層70係為一鋁墊。
仍如第5圖所示，重分佈層70係電性連接於導電柱 58(例如，金屬凸塊)。在一實施例之中，導電柱58是由一金屬或金屬合金所製成，其可允許一金屬氧化物72成型於導電柱58之複數個側壁之上。在此金屬氧化物72存在之實施例之中，一模鑄化合物/底部填充材料繞著導電柱58被設置於積體電路晶片60與底材56之間且黏著性是被改善的，相對於無此金屬氧化物72存在時。在此實施例之中，導電柱58是由銅所製成，以及金屬氧化物72係為一銅氧化物。
請參閱第5圖及第6圖，每一條金屬線路76的末端 都會相互交疊金屬接墊54。金屬接墊寬度78是大於嵌入金屬線路76之線寬度80。換言之，每一個金屬接墊54係重疊其對應之金屬線路76於一個方向之中(亦即，從左至右於第6圖之中)。因此，每一個金屬接墊54可以提供一較寬之連接區域於凸塊在線路上內連線62之中。換言之，導電柱58之導電材料52係具有更多之接觸區域(面積)。如第6圖所示，在此實施例之中顯示出金屬接墊54與導電柱58之相對面積大小。
仍如第6圖所示，在一實施例之中，金屬接墊54係 為交錯的。換言之，鄰接之金屬接墊54是偏移於彼此。因此，在鄰接之金屬線路76之間的距離可以被減短。在此實施例之中，金屬接墊54及金屬線路76可以被成型於相同之金屬沉積步驟或分別之製程步驟之中。
藉由合併金屬接墊54至封裝結構50之中，如第5圖及第6圖所示，金屬線路76之線寬度80可以被保持相對的小。在此實施例之中，金屬線路76之線寬度80是大約為10μm或更小。因此，第5圖中所示之凸塊至金屬線路距離82亦可以保持相對的短，其可允許一較小之整體封裝結構50。甚至，在金屬接墊54與導電材料52之間的接合面積84可保持相對的大，原因為金屬接墊54所提供之較寬的接觸面積相對於更窄之金屬線路76。大的接合面積84可減輕或消除接合疲勞以及幫助防止焊錫裂縫產生於封裝結構50之中。
請參閱第7圖，顯示在第5圖之封裝結構50內之其中一個金屬接墊54以及其中一個金屬線路76。在此實施例之 中，金屬接墊寬度78是大於金屬線路寬度80以及小於或等於一導電柱寬度86。此外，在此實施例之中，一金屬接墊長度88是小於或等於一導電柱長度90。在此實施例之中，金屬接墊長度88是介於導電柱長度90之70%與導電柱長度90之130%之間。甚至，金屬接墊54、金屬線路76及導電柱58可以具有其他的尺寸。
請參閱第8圖，顯示對於金屬接墊54之適當形狀之 範例92。在此實施例之中，金屬接墊54可以具有形、正方形、三角形、梯形、六邊形、八邊形及橢圓形之形狀。金屬接墊54亦可以具有階梯形、菱形、圓角矩形、雙梯形、膠囊型、卵形或一個六角端矩形之形狀。值得注意的是，被提供於第8圖中之適當形狀只是示範性的說明，但並不以此為限。換言之，其他的對稱或非對稱形狀可以被使用去成型金屬接墊54。
請參閱第9圖，提供用於成型第5圖之封裝結構50 之方法100。在方塊102之中，每一條嵌入金屬線路的末端都會相互交疊金屬接墊。金屬接墊寬度是大於一對應之線路寬度。 在方塊104之中，一積體電路晶片之導電柱是電性連接於底材上的金屬接墊。
請參閱第10圖，顯示剖面具有一梯形形狀之金屬 接墊204及/或梯形之金屬線路226之封裝結構200。藉由給予金屬接墊204一梯形之形狀(或一類似之形狀)，封裝結構200係享有良好之線路黏著能力於凸塊在線路上內連線212處。此外，顯示於第10圖中之凸塊至金屬線路距離232亦可以保持相對的短，其可允許一較小之整體封裝結構200。甚至，在金屬接墊204與導電材料52之間的接合區域234係保持相對的大，由於金 屬接墊204所提供之較寬的接觸面積相對於更窄之金屬線路226。大的接合區域234可減輕或消除接合疲勞以及幫助防止焊錫裂縫產生於封裝結構200之中。
請參閱第11圖，顯示剖面具有一倒梯形形狀之金 屬接墊304及/或倒梯形之金屬線路326之封裝結構300。藉由給予金屬接墊304一倒梯形之形狀(或一類似之形狀)，封裝結構300係較不易發生接合疲勞於凸塊在線路上內連線312處。此外，顯示於第11圖中之凸塊至金屬線路距離332亦可以保持相對的短，其可允許一較小之整體封裝結構300。甚至，在金屬接墊304與導電材料52之間的接合區域334係保持相對的大，由於金屬接墊304所提供之較寬的接觸面積相對於更窄之金屬線路326。大的接合區域334可減輕或消除接合疲勞以及幫助防止焊錫裂縫產生於封裝結構300之中。
請參閱第12圖及第13圖，在此實施例之中，一接 合增進層400可以被成型或被沉積於金屬接墊54之上。接合增進層400係用來擴大接合面積以緩和或消除焊錫裂縫及金屬凸塊應力。此外，接合增進層400係降低內連線電阻於封裝結構50之中，可以分別改善電子遷移效應(electro migration，EM)及接合疲勞。
如第12圖府視圖所示，接合增進層400可以具有 一”H”形狀。在此實施例之中，”H”形之接合增進層400之每一個輪廓404之一寬度402係大約為5μm，以及在輪廓404之間的間隔距離406亦係大約為5μm。甚至，其他的尺寸都是被考慮的，以及輪廓404之寬度402與在它們之間的間隔距離406可以 是較大的或較小的。
在此實施例之中，接合增進層400之一寬度408是 大約為金屬接墊54之寬度78之80%。在此實施例之中，接合增進層400之一長度410是大約為金屬接墊54之長度88之80%。甚至，在其他實施例之中，接合增進層400相對於金屬接墊54之比例可以是較大的或較小的。
請參閱第13圖，接合增進層400係突出或延伸至導 電材料52之中。因此，接合增進層400提供額外之表面區域去產生一堅固的凸塊在線路上內連線412。此外，在此實施例之中，因為接合增進層400係凸出於金屬接墊54，故凸塊在線路上內連線412可以抵抗由如此側向偏移所引起之側向移動。
請參閱第14圖及第15圖，第10圖之封裝結構200以 及第11圖之封裝結構300皆已配備有接合增進層400。接合增進層400已被成型於第14圖中之梯形金屬接墊204之上以及第15圖中之梯形金屬接墊304之上。
請參閱第16圖至第18圖，顯示使用於第12圖及第 13圖至第15圖中之接合增進層400之成型流程。在第16圖之中，利用一微影製程做光阻500圖案雕刻在金屬接墊54及鄰接之線路76之上。如第16圖所示，光阻500已經被曝光然後顯影形成圖刻在金屬接墊54上。
在第17圖之中，利用一金屬電鍍製程去沉積金屬 502於光阻500之中。因此，金屬502是被成型於金屬接墊54之暴露部位上，如第16圖所示。在此實施例之中，沉積於被圖刻之光阻500中之金屬502係為銅。然而，其他適當之金屬亦可以 被採用。
在第18圖之中，光阻500被剝除。在此實施例之 中，光阻500是藉由濕蝕刻而被剝除。甚至，在其他實施例之中，光阻可以用別的方法被移除掉。如第18圖所示，當光阻500被移除掉時，接合增進層400仍然會存在。值得注意的是，如第16圖至第18圖所示之相同或類似之製程亦可已被使用去成型第14圖及第15圖之接合增進層400。此外，未顯示於第16圖至第18圖中之額外製程步驟可以被採用。
如上所述，第5圖之封裝結構50可以提供有利之特 色。舉例來說，內崁式金屬接墊54可允許封裝結構50的內連線間距減短。在相同間距設計下，封裝結構50之設計不僅可以擴大組裝失效容忍度，其還可以在接合製程或可靠度測試過程中防止焊錫破裂。此外，封裝結構50可以降低線路橋接失效之可能性。甚至，封裝結構50擁有比較大之間距在導電柱與附近鄰接之金屬線路之間。
再者，封裝結構50之設計可以允許金屬線路之間 距更為靠近。因此，一比較進取的金屬線路間距設計也能被採用。相較於傳統之封裝結構，封裝結構50亦能提供較低的電性阻抗、較佳的電遷移(EM)防護能力以及降低內連線電阻-電容(RC)延遲。此外，封裝結構50能夠提供較低之金屬線路剝離機率因為封裝結構50擁有較寬之金屬接墊。
雖然本發明已以較佳實施例揭露於上，然其並非 用以限定本發明，任何熟習此項工藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。
10‧‧‧封裝結構
12‧‧‧封裝底材
14‧‧‧導電材料
16‧‧‧金屬線路
18‧‧‧導電柱
20‧‧‧積體電路晶片
22‧‧‧導電材料與鄰接金屬線路的間距
24‧‧‧凸塊在導線上的直連結構
48‧‧‧接合區域(接合面積)

Claims (10)

  1. 一種封裝結構，包括：一積體電路晶片，係連結一導電柱；一底材，具有對於每一嵌入金屬線路之一金屬接墊，其中，該金屬接墊之寬度係大於一相對應之嵌入金屬線路之寬度，且該金屬接墊之長度大於該金屬接墊之寬度，其中該些金屬接墊為交錯排列；一導電材料，係電性連接該導電柱於該金屬接墊；以及一接合增進層，凸出於該金屬接墊並延伸至該導電材料中，且該接合增進層具有一H形結構，其中該H形結構是從該金屬接墊唯一的凸出結構。
  2. 如申請專利範圍第1項所述之封裝結構，其中，一金屬氧化物係設置於該導電柱之側壁之上。
  3. 如申請專利範圍第1項所述之封裝結構，其中，該金屬接墊之長度係介於該導電柱長度之70%與該導電柱長度之130%之間。
  4. 如申請專利範圍第1項所述之封裝結構，其中，一模鑄化合物及一底部填充材料之至少一個係繞著該導電柱被設置以及係被設置於該積體電路晶片與該底材之間。
  5. 如申請專利範圍第1項所述之封裝結構，其中，該底材係為一嵌入圖案化製程底材，以及該導電材料亦係電性連接該導電柱於該嵌入金屬線路。
  6. 如申請專利範圍第1項所述之封裝結構，其中，該等金屬線路具有矩形形狀、梯形形狀及倒梯形形狀之至少一種，並 且係由銅、鋁、鎳、金及銀之至少一種所構成。
  7. 一種封裝結構，包括：一積體電路晶片，係連結一金屬凸塊；一底材，具有對於每一金屬線路之一金屬接墊，其中，該金屬接墊係重疊該金屬線路於同一方向之中，且該金屬接墊之長度大於該金屬接墊之寬度，其中該些金屬接墊為交錯排列；一導電材料，係電性連接該金屬凸塊於該金屬接墊；以及一接合增進層，凸出於該金屬接墊並延伸至該導電材料中，且該接合增進層具有一H形結構，其中該H形結構是從該金屬接墊唯一的凸出結構。
  8. 如申請專利範圍第7項所述之封裝結構，其中，該金屬凸塊包括銅，一銅氧化物係設置於該金屬凸塊之側壁之上，以及該金屬接墊長度係介於該金屬凸塊長度之70%與該金屬凸塊長度之130%之間。
  9. 如申請專利範圍第7項所述之封裝結構，其中，一底部填充材料係繞著該金屬凸塊被設置以及係被設置於該積體電路晶片與該底材之間。
  10. 一種成形封裝結構之方法，包括：成型對於每一嵌入金屬線路之一金屬接墊於一底材之中，其中，該金屬接墊之寬度係大於一相對應之嵌入金屬線路之寬度，且該金屬接墊之長度大於該金屬接墊之寬度；電性連接一積體電路晶片透過一導電柱與該金屬接墊做電性連接； 成型一導電材料，其中該導電材料電性連接該金屬凸塊於該金屬接墊；成型一接合增進層接合於該金屬接墊之上，其中該接合增進層凸出於該金屬接墊並延伸至該導電材料中，且該接合增進層具有一H形結構；且該金屬接墊為交錯排列；允許一金屬氧化物去形成於該導電柱之側壁之上；以及使一底部填充材料繞著該導電柱流動以及在該積體電路晶片與該底材之間流動。
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US20140252598A1 (en) 2014-09-11
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US9536850B2 (en) 2017-01-03

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