CN105977242A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN105977242A
CN105977242A CN201510547161.7A CN201510547161A CN105977242A CN 105977242 A CN105977242 A CN 105977242A CN 201510547161 A CN201510547161 A CN 201510547161A CN 105977242 A CN105977242 A CN 105977242A
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China
Prior art keywords
duplexer
silicon substrate
semiconductor device
substrate
chip
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CN201510547161.7A
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English (en)
Inventor
栗田洋郎
栗田洋一郎
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Kioxia Corp
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Toshiba Corp
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Publication of CN105977242A publication Critical patent/CN105977242A/zh
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Abstract

实施方式的半导体装置及其制造方法具有：层叠体(20)，该层叠体(20)包括多个半导体芯片(11a～11h)，多个半导体芯片的至少一部分具有贯通半导体芯片的电极(12)，多个半导体芯片层叠并且通过电极互相连接，层叠体(20)具有第1宽度(W1)；硅基板(30)，设置在层叠体的第1面上，具有比第1宽度宽的第2宽度(W2)；布线层(50)，设置在层叠体的第2面上；及树脂(42，45)，设置在层叠体的周围。

Description

半导体装置及其制造方法
关联申请的引用
本申请以2015年3月11日申请的日本专利申请第2015－048491号的优先权的利益为基础，并且请求该利益，优先权申请的内容整体通过引用而包含于本申请。
技术领域
本实施方式涉及具有层叠有多个半导体芯片的芯片层叠体的半导体装置及其制造方法。
背景技术
为了实现半导体装置的小型化及高密度化，提出了在布线基板上层叠多个半导体芯片并封装化的技术。
然而，在使半导体芯片薄型化时，半导体芯片的刚性降低，容易产生半导体芯片翘曲。其结果是，在半导体芯片间连接不良，半导体装置的可靠性降低。该半导体芯片的翘曲在对半导体芯片进行层叠的情况下增加。并且，在通过垂直贯通半导体芯片的内部的贯通电极(TSV：Through Silicon Via)将半导体芯片间连接的构造中，半导体芯片的翘曲会显著发生。
发明内容
实施方式提供能够抑制芯片的翘曲的半导体装置及其制造方法。
实施方式提供一种半导体装置，其具备：
层叠体，该层叠体包括多个半导体芯片，所述多个半导体芯片的至少一部分具有贯通所述半导体芯片的电极，所述多个半导体芯片层叠并且通过所述电极互相连接，该层叠体具有第1宽度；
硅基板，设置在所述层叠体的第1面上，具有比所述第1宽度宽的第2宽度；
布线层，设置在所述层叠体的第2面上；以及
树脂，设置在所述层叠体的周围。
此外，实施方式提供一种半导体装置，其具备：
层叠体，该层叠体包括多个半导体芯片，所述多个半导体芯片具有贯通所述半导体芯片的电极，所述多个半导体芯片层叠并且通过所述电极互相连接，该层叠体具有第1宽度；
硅基板，设置在所述层叠体的第1面上，具有所述第1宽度，并构成半导体芯片；
布线层，设置在所述层叠体的第2面上；以及
树脂，设置在所述层叠体的周围，
所述硅基板具有所述层叠体的一个半导体芯片的厚度以上的厚度。
此外，实施方式提供一种半导体装置的制造方法，其具备：
形成层叠体的工序，该层叠体是在硅基板上使具有贯通半导体芯片的电极的多个半导体芯片层叠，所述多个半导体芯片通过所述电极互相连接而成的；
将布线层连接于所述层叠体的工序；
在所述硅基板上及所述层叠体的周围形成树脂的工序；及
切削所述硅基板而使所述硅基板的厚度变薄的工序。
附图说明
图1是第1实施方式所涉及的半导体装置的剖视图。
图2是第1实施方式所涉及的半导体装置的制造方法的流程图。
图3是对第1实施方式所涉及的半导体装置的制造工序进行表示的图。
图4是粘接图3对第1实施方式所涉及的半导体装置的制造工序进行表示的图。
图5是沿着图4的V－V线的基板及载体的剖视图。
图6是粘接图5对第1实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图7是粘接图6对第1实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图8是粘接图7对第1实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图9是粘接图8对第1实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图10是粘接图9对第1实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图11是第2实施方式所涉及的半导体装置的剖视图。
图12是第2实施方式所涉及的半导体装置的剖视图。
图13是第3实施方式所涉及的半导体装置的剖视图。
图14是第3实施方式所涉及的半导体装置的剖视图。
图15是第3实施方式所涉及的半导体装置的剖视图。
图16是第3实施方式所涉及的半导体装置的剖视图。
图17是对第4实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图18是对第4实施方式所涉及的半导体装置进行表示的剖视图。
图19是对第5实施方式所涉及的半导体装置的基板进行表示的俯视图。
图20是对第5实施方式所涉及的半导体装置的基板进行表示的俯视图。
图21是对第5实施方式所涉及的半导体装置的基板进行表示的俯视图。
图22是对第6实施方式所涉及的半导体装置的基板进行表示的剖视图。
图23是对图22的半导体装置的基板进行表示的俯视图。
图24是第7实施方式所涉及的半导体装置的制造方法的流程图。
图25是对第7实施方式所涉及的半导体装置的制造工序进行表示的图。
图26是对第7实施方式所涉及的半导体装置的制造工序进行表示的图。
图27是对第7实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图28是粘接图27对第7实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图29是对第8实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图30是对第9实施方式所涉及的半导体装置进行表示的剖视图。
图31是对第10实施方式所涉及的半导体装置进行表示的剖视图。
图32是对第10实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图33是粘接图32对第10实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图34是粘接图33对第10实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图35是粘接图34对第10实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图36是粘接图35对第10实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图37是粘接图36对第10实施方式所涉及的半导体装置的制造工序进行表示的剖视图。
图38是对第10实施方式所涉及的半导体装置的变形例进行表示的剖视图。
图39是对第10实施方式所涉及的半导体装置的变形例进行表示的剖视图。
具体实施方式
以下，参照附图对实施方式进行说明。另外，在以下的说明中，对于具有相同功能及结构的要素，附以共通的附图标记。
[1]第1实施方式
在第1实施方式的半导体装置中，通过使用硅基板作为芯片层叠体的支承体，来抑制半导体芯片的翘曲。
[1－1]构造
使用图1，对第1实施方式所涉及的半导体装置1的构造进行说明。
如图1所示，第1实施方式的半导体装置1具备芯片层叠体20、基板30、布线层50、树脂42及45。芯片层叠体20包括存储器芯片层叠体10及接口芯片(IF芯片)18。
存储器芯片层叠体10层叠多个半导体芯片11a～11h而形成。各半导体芯片11b～11h具有垂直贯通半导体芯片11b～11h的内部的例如由硅(Si)构成的贯通电极(TSV)12。在本图中，位于存储器芯片层叠体10的基板30侧的最下级的半导体芯片11a不具有贯通电极12，但也可以具有贯通电极12。多个半导体芯片11a～11h通过贯通电极12及凸点电极(bump electrode)13互相连接。在多个半导体芯片11a～11h间的未形成有贯通电极12及凸点电极13的区域设置有粘接剂14，通过该粘接剂14粘接并固定多个半导体芯片11a～11h。各半导体芯片11a～11h例如是具有NAND型闪存存储器的存储器芯片。
IF芯片18具备接口电路(IF电路)，该接口电路(IF电路)用于在构成存储器芯片层叠体10的多个半导体芯片11a～11h与外部器件(未图示)之间进行数据通信。IF芯片18通过布线15等与多个半导体芯片11a～11h连接。IF芯片18配置在芯片层叠体20的布线层50侧的最上面。但是，IF芯片18不限定于图1的位置，例如也可以配置在存储器芯片层叠体10的半导体芯片11a～11h间等，还可以不设置IF芯片18本身，而将IF电路搭载在半导体芯片11a～11h内。IF芯片18的宽度W4比半导体芯片11a～11h(存储器芯片层叠体10)的宽度W1窄。
基板30作为芯片层叠体20的支承体发挥功能。基板30隔着粘接剂41设置在芯片层叠体20的第1面上。基板30的宽度W2比半导体芯片11a～11h(存储器芯片层叠体10)的宽度W1宽，并与布线层的宽度W3相等。优选基板30具有一个半导体芯片11a～11h的厚度T1以上的厚度T2。基板30的厚度T2也可以比布线层50的厚度薄。基板30的厚度T2例如是100μm～200μm左右。另外，在多个半导体芯片11a～11h的厚度T1不同的情况下，优选基板30的厚度T2为最厚的半导体芯片的厚度T1以上。
优选基板30的材料是满足(a)具有与构成芯片层叠体20的材料(主要是硅)的热膨胀系数相近的热膨胀系数，(b)刚性高，(c)切断及研磨容易的材料。通过满足(a)，即使经过半导体装置1的制造工序中的热处理，也能够抑制芯片层叠体20的翘曲。通过满足(b)，能够抑制芯片层叠体20的翘曲。通过满足(c)，容易进行封装时的模切(die cutting)工序中的切断、或基于基板的薄化工序的研磨。作为满足这样的(a)至(c)的要求的材料，优选是硅。因此，作为基板30，优选使用硅基板。
基板30具有切割部31。切割部31与芯片层叠体20所配置的区域相比位于更外侧。切割部31从基板30的与芯片层叠体20对置的面30A一直贯通到与该面相反一侧的面30B为止。
布线层50设置在芯片层叠体20的第2面上。布线层50通过内部连接端子43及44与芯片层叠体20的电极片17连接。布线层50的与芯片层叠体20相反一侧的面上设置有外部连接端子46。外部连接端子46通过布线层50内的布线网(未图示)与内部连接端子43及44电连接。如该图所示，在将半导体装置1作为BGA(Ball GridArray：球栅阵列封装)封装使用的情况下，外部连接端子46由具有软钎料球、软钎料镀层、Au镀层等的突起端子构成。但是，本实施方式的半导体装置1也能够应用于设置有金属面作为外部连接端子46的LGA(Land Grid Array：平面网格阵列封装)型、CSP(Chip SizePackage：芯片尺寸封装)型等的其他的半导体封装。
布线层50例如是在绝缘树脂基板或者绝缘树脂层的表面及内部设置有布线网(未图示)的部件。作为布线层50，具体而言，利用使用了玻璃－环氧树脂、BT树脂(双马来酰亚胺·三嗪树脂)等的绝缘树脂的印制电路布线基板(多层印制电路基板等)。这样，构成布线层50的主要的材料是树脂，因此与基板30的材料(硅)不同。另外，作为布线层50，也包含内插板(interposer)、布线基板、封装基板、直接形成在芯片层叠体20上的再布线层。
树脂42设置在多个半导体芯片11a～11h间及存储器芯片层叠体10的侧面。树脂42将基板30的切割部31内填充。为此，树脂42从切割部31中的基板30的面30B露出。树脂45覆盖树脂42并设置在基板30与布线层50之间。
树脂42及45例如是热固化性树脂。作为热固化性树脂，例如使用在环氧类树脂、丙烯酸类树脂、胺类树脂、硅酮类树脂、聚酰亚胺类树脂等中混合了二氧化硅等的填充材料(填充物)的树脂。树脂42和树脂45例如使用成分不同的材料。树脂42例如优选是环氧类树脂，且是填充物粒子较小的材料、液状的易浸透的材料。树脂45例如优选是环氧类树脂，且是填充物粒子较大且热膨胀系数与芯片层叠体20的材料接近的材料。这样，优选的是，树脂42和树脂45即使是相同的环氧类树脂，成分也不同。但是，树脂42和树脂45也可以是相同成分的相同材料。
[1－2]制造方法
使用图2至图10，对第1实施方式所涉及的半导体装置1的制造方法进行说明。
首先，如图3所示，对例如Si基板30进行半切割，而形成切割部31(图2的ST1)。另外，切割部31具有不贯通基板30的程度的规定的深度(参照图5)。切割部31的深度例如是基板30的厚度的一半左右。之后，基板30按每个芯片被切断(图2的ST2)。
接下来，如图4及图5所示，在芯片载体60上搭载基板30(图2的ST3)。此时，基板30按每个芯片配置在芯片载体60的凹陷部61。优选基板30的厚度是后述的芯片层叠体20的厚度以上，例如是775μm左右。另外，在芯片载体60的凹陷部61的中央，设置有开口部62。
接下来，如图6所示，在基板30上隔着热固化性的粘接剂41形成芯片层叠体20(图2的ST4)。以下，参照图1，对芯片层叠体20的形成进行说明。
首先，在基板30上的规定的位置，对成为存储器芯片层叠体10的第一级的半导体芯片11a进行粘接。在此，规定的位置是指，例如收纳在基板30的切割部31的内侧的位置。之后，在半导体芯片11a上依次层叠规定的级数的半导体芯片11b～11h，从而形成存储器芯片层叠体10。此时，在半导体芯片11a～11h的相互间，以由硅构成的贯通电极12与凸点电极13连接的方式对位并连接贯通电极12与凸点电极13。然后，在未形成贯通电极12的区域，在半导体芯片11a～11h的单面，以分散的方式形成多个粘接剂14。通过该粘接剂14，在层叠半导体芯片11a～11h时，对置的半导体芯片11a～11h被粘接而固定。
接下来，在位于存储器芯片层叠体10的最上级的半导体芯片11h上形成绝缘膜16，在该绝缘膜16内形成与贯通电极12连接的布线15。然后，搭载与该布线15连接的IF芯片18。IF芯片18相对于存储器芯片层叠体10被倒转芯片式连接(FC(flip chip)连接)。这样，形成芯片层叠体20(图2的ST4)。
接下来，如图6所示，用模塑树脂42将芯片层叠体20的侧面及构成芯片层叠体20的半导体芯片11a～11h间密封(图2的ST5)。此时，树脂42填充在基板30的切割部31内。此外，切割部31成为阻挡部，避免树脂42向切割部31的更外侧蔓延。另外，基于树脂42的密封也可以在形成芯片层叠体20的工序中途适当进行。
接下来，如图7所示，芯片层叠体20与布线层50连接(图2的ST6)。具体而言，芯片层叠体20的IF芯片18以与布线层50对置的方式配置。然后，进行芯片层叠体20与对应于布线层50的内部连接端子43及44的对位，通过预先涂敷的暂时固定材料(未图示)进行暂时粘接。之后，在甲酸气氛等还原气氛中进行加热(软熔；reflow)，从而芯片层叠体20与布线层50电连接。
在此，使用还原气氛的目的在于，为了使电连接可靠而对在内部连接端子43的表面形成的氧化膜等进行还原并去除。此外，内部连接端子43例如以软钎料材料、Au为主成分。内部连接端子43进行存储器芯片层叠体10的最上级的半导体芯片11h与布线层50之间的电连接。
另外，上述示出了使用了在还原气氛中的软熔的连接方法，但除此以外，也可以使用一般的倒转芯片式连接方法，该倒转芯片式连接方法使用了软钎料软熔和使用了助焊剂的内部连接端子43的还原。
接下来，如图8所示，在用树脂45将芯片层叠体20与布线层50之间填充(图2的ST7)的同时，用树脂45覆盖基板30。另外，该工序也可以分离成用树脂将芯片层叠体20与布线层50之间填充的工序和用树脂覆盖基板30的工序而实施。在此情况下，也能够使用不同的树脂(未图示)。
接下来，如图9所示，同时研磨树脂45及基板30(图2的ST8)。此时，也可以切割部31内的树脂42也被研磨，树脂42从基板30露出。之后，在布线层50的外侧的面上形成外部连接端子46。
接下来，如图10所示，通过模切，切断基板30、布线层50及树脂45，并进行单片的封装化(图2的ST9)。这样，图1所示的层叠型半导体装置1完成。
[1－3]效果
根据上述第1实施方式，使用硅基板30作为芯片层叠体20的支承体。这样的硅基板30的热膨胀系数与具有使用硅基板而形成的半导体芯片11a～11h及IF芯片18的芯片层叠体20相同。此外，硅的刚性高，切断及研磨容易。为此，通过使用硅基板30作为支承体，能够抑制半导体芯片11a～11h的翘曲，能够提高半导体装置1的可靠性。并且，由于硅基板30容易研磨及模切，因此容易实现封装的小型化及薄化。
[2]第2实施方式
在第1实施方式中，芯片层叠体20的支承体的基板30的厚度T2一定。与此相对，第2实施方式中，基板30的厚度T2在中央部和端部不同。在第2实施方式中，使用图11及图12，对与第1实施方式的不同点进行说明。
如图11及图12所示，在第2实施方式的半导体装置1中，基板30及芯片层叠体20翘曲，从而基板30的中央部的厚度T2a与基板30的端部的厚度T2b不同。但是，在此所述的基板30及芯片层叠体20翘曲，是现有的问题能够充分降低的程度的少许翘曲。
在图11的情况下，芯片层叠体20具有向基板30侧突出的翘曲。为此，基板30的面30A成为向内侧凹陷的凹形状。即，基板30的中央部的厚度T2a变得比基板30的端部的厚度T2b薄。
在图12的情况下，芯片层叠体20具有向布线层50侧突出的翘曲。为此，基板30的面30A成为向外侧突出的凸形状。即，基板30的中央部的厚度T2a变得比基板30的端部的厚度T2b厚。
在此，在图11及图12的半导体装置1中，优选基板30的芯片层叠体20所形成的区域即基板30的中央部的厚度T2a，为一个半导体芯片11a～11h的厚度T1以上。
根据上述第2实施方式，即使在基板30及芯片层叠体20少许翘曲的情况下，也与第1实施方式同样地，相比于以往，能够抑制半导体芯片11a～11h的翘曲。
另外，在基板30及芯片层叠体20不翘曲而基板30的厚度T2有偏差的情况下，也优选芯片层叠体20所形成的区域的基板30的厚度T2为一个半导体芯片11a～11h的厚度T1以上。
[3]第3实施方式
第3实施方式的半导体装置1是基板30的切割部31的变形例。在第3实施方式中，使用图13至图16，对与第1实施方式的不同点进行说明。
如图13所示，切割部31也可以是凹部形状。即，切割部31是从与芯片层叠体20对置的面30A凹陷的凹部。为此，切割部31内的树脂42不从基板30的外侧面30B露出。这样的图13的半导体装置1的情况下，通过树脂42进入到凹部，由此具有如下效果：基板30相对于树脂42的贴紧性提高，对应于封装的变形应力的可靠性提高。
如图14所示，也可以在切割部31的内部进行模切。即，切割部31内的树脂42从基板30的侧面露出。换言之，成为基板30的周围被树脂42覆盖的状态。在这样的图14的半导体装置1的情况下，基板30的端部不在封装端部露出而被树脂42所保护，具有封装对于耐冲击的可靠性提高的效果。
如图15所示，也可以在凹部形状的切割部31的内部进行模切。即，切割部31内的树脂42从基板30的内侧部分的侧面露出。换言之，成为基板30的内侧部分的侧面的周围被树脂42覆盖的状态。此外，基板30成为朝向芯片层叠体20突出的凸形状。这样的图15的半导体装置1的情况下，通过基板30的端部形成得较薄，因此由树脂42与基板30的热膨胀系数之差产生的应力通过基板30变形得到缓和，具有热可靠性提高的效果。
如图16所示，也可以在相比于切割部31更靠内侧进行模切，也可以没有切割部31。这样的图16的半导体装置1的情况下，通过比较厚的基板30一直存在直到封装端部为止，从而具有如下效果：封装整体的刚性提高，封装的处理的可靠性提高。
根据如以上那样的第3实施方式的半导体装置1，与第1实施方式同样地，能够抑制半导体芯片11a～11h的翘曲。
[4]第4实施方式
第4实施方式的半导体装置1是与切割部31内的树脂相关的变形例。在第4实施方式中，使用图17及图18，对与第1实施方式的不同点进行说明。
如图17所示，在用树脂42将芯片层叠体20的周围密封时，树脂42也可以不进入到切割部31内。在此情况下，在最终构造的半导体装置1中，也可以如图18所示用树脂45填充切割部31。
根据如以上那样的第4实施方式的半导体装置1，与第1实施方式同样地，能够抑制半导体芯片11a～11h的翘曲。
此外，在第4实施方式的半导体装置1中，通过用树脂45填充切割部31内，与用树脂42填充切割部31内的情况相比，具有如下效果：热膨胀系数相对较大的树脂42的固化时的收缩应力不对基板30较薄的部分施加影响，可靠性提高。
[5]第5实施方式
在第5实施方式中，使用图19至图21，对各实施方式的基板30的俯视图进行说明。
如图19所示，在基板30的内侧设置切割部31，基板30的侧面的周围未被树脂42及45包围。这样的俯视图的半导体装置1例如具有如图1那样的截面构造。图19的半导体装置1，通过树脂42或树脂45进入到切割部31，从而具有如下效果：基板30对于树脂42或者45的贴紧性提高，封装对于变形应力的可靠性提高。
如图20所示，基板30的周围形成有树脂42或者45，基板30的侧面全部被树脂42或者45覆盖。这样的俯视图的半导体装置1例如具有如图14那样的截面构造。图20的半导体装置1具有，基板30的端部不在封装端部露出而被树脂42或树脂45所保护，从而封装对于耐冲击的可靠性提高的效果。
如图21所示，基板30的侧面的一部分被树脂42或者45所覆盖。这样的俯视图的半导体装置1例如具有如图14、图16那样的截面构造。图21的半导体装置1具有，对于基板30的端部不在封装端部露出而被树脂42或树脂45所保护的部分，封装对于耐冲击的可靠性提高的效果。
根据如以上那样的第5实施方式的半导体装置1，与第1实施方式同样地，能够抑制半导体芯片11a～11h的翘曲。
另外，基板30的切割部31并不限定于在基板30的一个侧面通过1条切割部形成，也可以设置多条切割部。
[6]第6实施方式
第6实施方式的半导体装置1是与基板30的宽度W2相关的变形例。在第6实施方式中，使用图22及图23，对与第1实施方式的不同点进行说明。
如图22所示，基板30的宽度W2也可以比布线层50的宽度W3窄。在此情况下，如图23所示，基板30的侧面的周围被树脂45覆盖。
根据如以上那样的第6实施方式的半导体装置1，与第1实施方式同样地，能够抑制半导体芯片11a～11h的翘曲。
另外，基板30的宽度W2也可以与芯片层叠体20的宽度W1相同。
[7]第7实施方式
在第7实施方式中，使用图24至图28，对与第1实施方式不同的半导体装置1的制造方法进行说明。在此，对与第1实施方式的不同点进行说明。
首先，如图25至图27所示，例如对硅基板30进行半切割，形成切割部31(图24的ST1)。基板30可以是图25的硅晶片(圆形)或图26的硅的长条基板(长方形)。
接下来，如图28所示，在基板30上隔着热固化性的粘接剂41，形成芯片层叠体20(图24的ST2’)。
接下来，在芯片层叠体20的侧面上，构成芯片层叠体20的半导体芯片11a～11h之间的空间及切割部31内，填充层间密封树脂42(图24的ST3’)。
接下来，基板30按每个芯片被切断(图24的ST4’)。
之后，与第1实施方式同样地，执行图24的步骤ST6～ST9。
在第1实施方式中，在半切割后进行基板30的按每个芯片的切断。与此相对，在第7实施方式中，在用树脂42将芯片层叠体20的侧面密封后进行基板30的按每个芯片的切断。此外，在第7实施方式的半导体装置1的制造工序中，不使用芯片载体60。这样的第7实施方式的半导体装置1也与第1实施方式同样地，能够抑制半导体芯片11a～11h的翘曲。
[8]第8实施方式
第8实施方式的半导体装置1是与研磨前的基板30的形状相关的变形例。在第8实施方式中，使用图29，对与第1实施方式的不同点进行说明。
如图29所示，基板30也可以具有与载体60的开口部62对应的突出部32。突出部32设置在基板30的与形成有切割部31的面相反一侧的面上。
另外，基板30的突出部32在图9的研磨工序中被去除。为此，第8实施方式所涉及的最终的半导体装置10是与图1同样的构造。但是，在图9的研磨工序后，也可以残留基板30的突出部32。
根据如以上那样的第8实施方式的半导体装置1，与第1实施方式同样地，能够抑制半导体芯片11a～11h的翘曲。并且，根据第8实施方式，在向芯片载体60传送时，基板30的突出部32与载体60的开口部62嵌合。因此，之后的处理能够稳定地进行。
[9]第9实施方式
第9实施方式的半导体装置1，是使用DRAM作为各半导体芯片11a～11h的情况。在第9实施方式中，使用图30，对与第1实施方式的不同点进行说明。
如图30所示，各半导体芯片11a～11h例如也可以是具有DRAM的存储器芯片。在此情况下，IF芯片18使用宽度比图1的构造宽的芯片，并与内部连接端子43及44连接。
根据如以上那样的第9实施方式的半导体装置1，与第1实施方式同样地，能够抑制半导体芯片11a～11h的翘曲。
[10]第10实施方式
第10实施方式是使用半导体芯片作为成为芯片层叠体20的支承体的基板70的例子。在此，对与第1实施方式的不同点进行说明。
[10－1]构造
使用图31，对第10实施方式所涉及的半导体装置1的构造进行说明。
如图31所示，在第10实施方式的半导体装置1中，在成为芯片层叠体20的支承体的基板70上，搭载有半导体集成电路。即，基板70采用与构成芯片层叠体20的半导体芯片11a～11h相同的结构。因此，也可以说基板70是芯片层叠体20的第一级的半导体芯片的基板。
优选基板70的厚度T2是一个半导体芯片11a～11h的厚度T1以上的厚度。基板70的厚度T2例如是一个半导体芯片11a～11h的厚度T1的3～5倍左右。例如，基板70的厚度T2为150μm左右，各半导体芯片11a～11h的厚度T1为30～50μm左右。
基板70的宽度W2与半导体芯片11a～11h(存储器芯片层叠体10)的宽度W1相等。但是，基板70的宽度W2也能够比半导体芯片11a～11h(存储器芯片层叠体10)的宽度W1宽。此外，基板70与半导体芯片11a～11h(存储器芯片层叠体10)可以是相同尺寸。
基板70不具有在半导体芯片11a～11h内设置的贯通电极12。但是，也能够在基板70内形成贯通电极12。
树脂45设置在多个半导体芯片11a～11h间、存储器芯片层叠体10及基板70的侧面。
[10－2]制造方法
使用图32至图37，对第10实施方式所涉及的半导体装置1的制造方法进行说明。
首先，如图32所示，在芯片载体60上搭载基板70。基板70是搭载有半导体集成电路的半导体芯片的基板。优选基板70的厚度是芯片层叠体20的厚度以上，例如是775μm左右。
接下来，如图33所示，在基板70上形成芯片层叠体20。接下来，如图34所示，芯片层叠体20通过内部连接端子43与布线层50连接。接下来，如图35所示，用树脂45密封基板70、芯片层叠体20及布线层50。此时，树脂45也可以填充在芯片层叠体20的多个半导体芯片11a～11h间。
接下来，如图36所示，同时研磨树脂45及基板70，基板70被薄化。接下来，如图37所示，通过模切，基板70、布线层50及树脂45被切断，进行单片的封装化。这样，图10所示的层叠型半导体装置1完成。
根据如以上那样的第10实施方式的半导体装置1，与第1实施方式同样地，能够抑制半导体芯片11a～11h的翘曲。
另外，第10实施方式的半导体装置1如图38及图39所示，与上述第2实施方式的半导体装置1同样地，基板70的中央部的厚度T2a与基板70的端部的厚度T2b可以不同。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例子而提示的，无意限定发明的范围。这些新的实施方式能够以其他各种方式实施，在不脱离发明的主旨的范围，能够进行各种省略、置换、变更。这些实施方式及其变形包含于发明的范围及主旨，并且包含于专利请求的范围所记载的发明及其均等的范围。

Claims (20)

1.一种半导体装置，具备：
层叠体，该层叠体包括多个半导体芯片，所述多个半导体芯片的至少一部分具有贯通所述半导体芯片的电极，所述多个半导体芯片层叠并且通过所述电极互相连接，该层叠体具有第1宽度；
硅基板，设置在所述层叠体的第1面上，具有比所述第1宽度宽的第2宽度；
布线层，设置在所述层叠体的第2面上；以及
树脂，设置在所述层叠体的周围。
2.如权利要求1所述的半导体装置，
所述硅基板具有切割部，
所述切割部与所述层叠体所配置的区域相比位于更外侧，
所述树脂设置在所述切割部内。
3.如权利要求2所述的半导体装置，
所述切割部从所述硅基板的第3面贯通到第4面，
所述第3面与所述层叠体的所述第1面对置，
所述第4面位于与所述第3面相反一侧。
4.如权利要求3所述的半导体装置，
所述切割部内的所述树脂从所述硅基板的所述第4面露出。
5.如权利要求2所述的半导体装置，
所述切割部是从所述硅基板的与所述层叠体的所述第1面对置的面凹陷的凹部。
6.如权利要求1所述的半导体装置，
所述硅基板具有一个半导体芯片的厚度以上的厚度。
7.如权利要求1所述的半导体装置，
所述硅基板的中央部的厚度与所述硅基板的端部的厚度不同。
8.如权利要求1所述的半导体装置，
所述硅基板的所述第2宽度与所述布线层的第3宽度相等。
9.如权利要求1所述的半导体装置，
所述硅基板的所述第2宽度比所述布线层的第3宽度窄。
10.如权利要求1所述的半导体装置，
所述硅基板的侧面的至少一部分被所述树脂覆盖。
11.如权利要求1所述的半导体装置，
所述硅基板的侧面全部从所述树脂露出。
12.如权利要求1所述的半导体装置，
所述半导体装置具有第1芯片，该第1芯片设置在所述布线层与所述层叠体的所述第2面之间，与所述层叠体电连接，并具有比所述第1宽度窄的第4宽度。
13.一种半导体装置，具备：
层叠体，该层叠体包括多个半导体芯片，所述多个半导体芯片具有贯通所述半导体芯片的电极，所述多个半导体芯片层叠并且通过所述电极互相连接，该层叠体具有第1宽度；
硅基板，设置在所述层叠体的第1面上，具有所述第1宽度，并构成半导体芯片；
布线层，设置在所述层叠体的第2面上；以及
树脂，设置在所述层叠体的周围，
所述硅基板具有所述层叠体的一个半导体芯片的厚度以上的厚度。
14.如权利要求13所述的半导体装置，
所述硅基板的中央部的厚度与所述硅基板的端部的厚度不同。
15.如权利要求13所述的半导体装置，
所述硅基板的中央部的厚度比所述硅基板的端部的厚度薄。
16.如权利要求13所述的半导体装置，
所述硅基板的中央部的厚度比所述硅基板的端部的厚度厚。
17.如权利要求13所述的半导体装置，
所述半导体装置具有第1芯片，该第1芯片设置在所述布线层与所述层叠体的所述第2面之间，与所述层叠体电连接，具有比所述第1宽度窄的第2宽度。
18.一种半导体装置的制造方法，具备：
形成层叠体的工序，该层叠体是在硅基板上使具有贯通半导体芯片的电极的多个半导体芯片层叠，所述多个半导体芯片通过所述电极互相连接而成的；
将布线层连接于所述层叠体的工序；
在所述硅基板上及所述层叠体的周围形成树脂的工序；以及
切削所述硅基板而使所述硅基板的厚度变薄的工序。
19.如权利要求18所述的半导体装置的制造方法，
所述层叠体具有第1宽度，
所述硅基板具有比所述第1宽度宽的第2宽度。
20.如权利要求18所述的半导体装置的制造方法，
所述半导体装置的制造方法还具备，在形成所述层叠体前在所述硅基板形成切割部的工序，
所述切割部与形成有所述层叠体的区域相比位于更外侧，
所述树脂形成在所述切割部内。
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