JP2012227337A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2012227337A JP2012227337A JP2011093125A JP2011093125A JP2012227337A JP 2012227337 A JP2012227337 A JP 2012227337A JP 2011093125 A JP2011093125 A JP 2011093125A JP 2011093125 A JP2011093125 A JP 2011093125A JP 2012227337 A JP2012227337 A JP 2012227337A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】基板2の素子搭載面の上にはんだ層3を介して半導体素子1が接合され、基板2と半導体素子1がエポキシ樹脂からなる封止樹脂体4で封止されてなるケースレス構造の半導体装置10であって、基板2の素子搭載面のうち、半導体素子1が搭載されていない領域における半導体素子1の端部位置(もしくははんだ層の端部位置)から素子搭載面の端部までの長さをLとした際に、0.4L〜0.9Lの長さの1つの凹溝2aが素子搭載面の前記領域に設けられ、該凹溝2a内に封止樹脂体4の一部が入り込んでいる。
【選択図】図1
Description
図1は本発明の半導体装置の一実施の形態を示した縦断面図であり、図2は図1のII−II矢視図であって半導体装置の一実施の形態の平面図である。なお、図2は、封止樹脂体を透視してその下方の平面を示したものである。図示する半導体装置10は、回路基板2の上にはんだ層3を介して半導体素子1が接続され、回路基板2の露出部、はんだ層3の露出部および半導体素子1が比較的硬質の封止樹脂体4で包囲されてその全体が大略構成されており、ケースレス構造を呈するものである。
図4は、半導体装置の他の実施の形態を図2に対応するように平面図で示したものである。
同図で示す半導体装置10Aは、平面視長方形の半導体素子1およびはんだ層3の4つの端辺に対応する4つの凹溝2a’が回路基板2の表面に形成され、各凹溝2a’内に封止樹脂体4の一部が入り込んで双方の接続が図られたものである。
本発明者等は、図5で模擬するように、凹溝M1aを具備する回路基板M1に対してエポキシ樹脂素材の封止樹脂体M2をその一部が凹溝M1a内に入り込むようにして試験体Mを試作し、せん断力Qを付与して双方の接続強度(せん断破壊時の強度)を測定する実験をおこなった。
Claims (3)
- 基板の素子搭載面の上にはんだ層を介して半導体素子が接合され、基板と半導体素子がエポキシ樹脂からなる封止樹脂体で封止されてなるケースレス構造の半導体装置であって、
前記基板の素子搭載面のうち、半導体素子が搭載されていない領域における半導体素子の端部位置もしくははんだ層の端部位置から素子搭載面の端部までの長さをLとした際に、縦断面的に見て0.4L〜0.9Lの長さの1つの凹溝が素子搭載面の前記領域に設けられ、該凹溝内に封止樹脂体の一部が入り込んでいる半導体装置。 - 前記凹溝が半導体素子の周囲を囲繞している請求項1に記載の半導体装置。
- 前記半導体素子が平面視多角形の場合に、該多角形を構成する各辺の側方の前記領域に前記凹溝が設けられている請求項1に記載の半導体装置。
Priority Applications (1)
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JP2011093125A JP5772179B2 (ja) | 2011-04-19 | 2011-04-19 | 半導体装置 |
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JP2011093125A JP5772179B2 (ja) | 2011-04-19 | 2011-04-19 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2012227337A true JP2012227337A (ja) | 2012-11-15 |
JP5772179B2 JP5772179B2 (ja) | 2015-09-02 |
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JP2011093125A Expired - Fee Related JP5772179B2 (ja) | 2011-04-19 | 2011-04-19 | 半導体装置 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105355569A (zh) * | 2015-11-05 | 2016-02-24 | 南通富士通微电子股份有限公司 | 封装方法 |
JP2016171124A (ja) * | 2015-03-11 | 2016-09-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
CN111952203A (zh) * | 2020-08-25 | 2020-11-17 | 山东砚鼎电子科技有限公司 | 一种指纹识别封装及其形成方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62183150A (ja) * | 1986-02-06 | 1987-08-11 | Nec Corp | 半導体装置 |
JPH06112398A (ja) * | 1992-09-29 | 1994-04-22 | Mitsubishi Electric Corp | 樹脂封止型半導体装置 |
JP2000040774A (ja) * | 1998-07-24 | 2000-02-08 | Kyocera Corp | 半導体装置 |
JP2007250943A (ja) * | 2006-03-17 | 2007-09-27 | Hitachi Metals Ltd | 半導体装置 |
JP2007294568A (ja) * | 2006-04-24 | 2007-11-08 | Denso Corp | 半導体装置 |
JP2009105362A (ja) * | 2007-10-03 | 2009-05-14 | Panasonic Corp | 半導体装置とその製造方法および半導体基板 |
JP2010192930A (ja) * | 2010-04-30 | 2010-09-02 | Rohm Co Ltd | アイランド露出型半導体装置 |
-
2011
- 2011-04-19 JP JP2011093125A patent/JP5772179B2/ja not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62183150A (ja) * | 1986-02-06 | 1987-08-11 | Nec Corp | 半導体装置 |
JPH06112398A (ja) * | 1992-09-29 | 1994-04-22 | Mitsubishi Electric Corp | 樹脂封止型半導体装置 |
JP2000040774A (ja) * | 1998-07-24 | 2000-02-08 | Kyocera Corp | 半導体装置 |
JP2007250943A (ja) * | 2006-03-17 | 2007-09-27 | Hitachi Metals Ltd | 半導体装置 |
JP2007294568A (ja) * | 2006-04-24 | 2007-11-08 | Denso Corp | 半導体装置 |
JP2009105362A (ja) * | 2007-10-03 | 2009-05-14 | Panasonic Corp | 半導体装置とその製造方法および半導体基板 |
JP2010192930A (ja) * | 2010-04-30 | 2010-09-02 | Rohm Co Ltd | アイランド露出型半導体装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016171124A (ja) * | 2015-03-11 | 2016-09-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
CN105977242A (zh) * | 2015-03-11 | 2016-09-28 | 株式会社东芝 | 半导体装置及其制造方法 |
CN105355569A (zh) * | 2015-11-05 | 2016-02-24 | 南通富士通微电子股份有限公司 | 封装方法 |
CN111952203A (zh) * | 2020-08-25 | 2020-11-17 | 山东砚鼎电子科技有限公司 | 一种指纹识别封装及其形成方法 |
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