JPS62183150A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS62183150A
JPS62183150A JP61025110A JP2511086A JPS62183150A JP S62183150 A JPS62183150 A JP S62183150A JP 61025110 A JP61025110 A JP 61025110A JP 2511086 A JP2511086 A JP 2511086A JP S62183150 A JPS62183150 A JP S62183150A
Authority
JP
Japan
Prior art keywords
groove
resin
plate
heat sink
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61025110A
Other languages
English (en)
Inventor
Masataka Yanaga
彌永 政孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61025110A priority Critical patent/JPS62183150A/ja
Publication of JPS62183150A publication Critical patent/JPS62183150A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 (産業上の利用分野〕 本発明は、半導体装置に関し、特に耐湿性の優れた樹脂
封止半導体装置に関する。
〔従来の技術〕
従来の耐湿性に優れた樹脂封止半導体装置の代表例を第
3図(a)の断面図、同図(b)の封止樹脂を透視した
平面図で示す。図において、半導体素子3が取付けられ
る放熱板11に、半導体素子3の搭載部の周りを囲んで
溝12が設けられている。この溝12の部分で、樹脂6
と放熱板11の界面より浸入してきた水分をストップさ
せ、半導体素子3を浸入水分から保護する。溝の断面形
状は、第4図(a)または(blに示すように、U型1
2、またはV型13というよりに、溝の深い部分での溝
の幅は狭くなるか、浅い所と同じ幅となっている。
〔発明が解決しようとする問題点〕
上述した従来の樹脂封止半導体装置は、放熱板11と樹
脂6との界面からの水分の浸入に対して、溝部12によ
シ、より以上の水分の進入をストップさせるのであるが
、溝12の形状が、溝の深い部分での幅が狭くなるか、
浅い所と同じ幅になっている事から、溝の深さ方向での
樹脂6と放熱板11の密着強度が弱いという欠点がある
。この為機械的ストレス、熱的ストレスが装置に加わっ
た際に、溝の深さ方向での樹脂と放熱板との間でずれが
生じ、樹脂6と放熱板11の界面に隙間が発生し、樹脂
6と放熱板11の界面に沿う水分の進入を防ぐ効果が薄
くなってしまう。
〔問題点を解決するための手段〕
上記問題点に対し本発明では、放熱板の半導体素子搭載
部の周りを囲む溝の横断面形状において、少くとも一箇
所の溝幅の部分的に狭くなったくびれ部を備えている。
〔実施例〕
次に1本発明について、図面を参照して説明するO 第1図(a)は本発明の一実施例の断面図、同図(tl
は封止樹脂を透視して示した平面図である0第1図(a
l 、 (blにおいて、放熱板1の上面ナホ中央に半
導体素子3が搭載され、半導体素子3とリード4の間は
金属細線5で接続後、樹脂6によシ封止されている。放
熱板lには、半導体素子3の搭載部の周シを囲んで溝2
が設けられているが、溝2の横断面形状は、入シロが狭
くて、深い部分で溝幅が広くなったところの、入シロで
くびれた形をなしている。この実施例において、深いと
ころの溝の幅の広い部分にある封止樹脂は、溝の深さ方
向に対して、おさえられる事になシ、放熱板1と樹脂6
の密着強度が強くなる。(少なくとも、溝2の中での樹
脂6と放熱板1の密着強度は強くなる。)このよりに、
本発明によシ、樹脂6と放熱板1の密着強度が強められ
るので、樹脂6と放熱板1の界面から浸入する水分の進
入は、従来のものよシは遅くなる事が明らかである。さ
らに、機械的ストレス、熱的ストレスが装置に加わった
際も、溝の深さ方向での樹脂と放熱板のズレを防止する
事も明らかである。
第2図(a)〜(d)/l′i、放熱板に設けた水分浸
入阻止用の溝の断面形状のいろいろの変形例を示す図で
、図ta>は、溝2の入り口部に狭くくびれだくびれ部
2aがあり、深くなるにつれて、溝幅が広くなった、三
角形の頭をきったような形の例、図(blは円弧の一部
をきって、溝7の入り口部にくびれ部7aのある例、図
(C)は、溝8の入シロ部と深さの途中の2箇所でくび
れ部8a、8aのある例1図(d)は、溝9の深さの途
中で一箇所くひれ部9aのある例である。
〔発明の効果〕
る事によシ、樹脂と放熱板の密着性を向上させ。
機械的ストレス、熱的ストレスに強<シ、さらに耐湿性
を向上できる効果がある。
【図面の簡単な説明】
第1図<alは本発明の一実施例の断面図、同図(b)
は封止樹脂を透視して示し丸干面図、第2図(a)〜(
d)は水分浸入阻止用のいろいろの溝の変形例を示1.
11・・・・・・放熱板、2,7,8,9.12・・・
・・・水分浸入阻止用溝、3・・・・・・半導体素子、
4・・・・・・リード、5・・・・・・金属細線、6・
・・・・・封止樹脂。 代理人 弁理士  内 原   晋゛′°゛。 (b) 第 1 図 府Z図

Claims (1)

    【特許請求の範囲】
  1. 放熱板の上面に半導体素子が搭載され樹脂で封止された
    半導体装置において、前記放熱板には、その素子搭載部
    の周りを囲んで溝が設けられ、かつ、この溝の横断面形
    状において、溝幅が部分的に狭くなったくびれ部が少く
    とも一箇所有することを特徴とする半導体装置。
JP61025110A 1986-02-06 1986-02-06 半導体装置 Pending JPS62183150A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61025110A JPS62183150A (ja) 1986-02-06 1986-02-06 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61025110A JPS62183150A (ja) 1986-02-06 1986-02-06 半導体装置

Publications (1)

Publication Number Publication Date
JPS62183150A true JPS62183150A (ja) 1987-08-11

Family

ID=12156785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61025110A Pending JPS62183150A (ja) 1986-02-06 1986-02-06 半導体装置

Country Status (1)

Country Link
JP (1) JPS62183150A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001085591A (ja) * 1999-08-24 2001-03-30 Fairchild Korea Semiconductor Kk チップパッドが放熱通路として用いられるリードフレーム及びこれを含む半導体パッケージ
US7268427B2 (en) 2004-08-10 2007-09-11 Fujitsu Limited Semiconductor package, printed board mounted with the same, and electronic apparatus having the printed board
JP2012227337A (ja) * 2011-04-19 2012-11-15 Toyota Motor Corp 半導体装置
JP2018063999A (ja) * 2016-10-11 2018-04-19 トヨタ自動車株式会社 半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001085591A (ja) * 1999-08-24 2001-03-30 Fairchild Korea Semiconductor Kk チップパッドが放熱通路として用いられるリードフレーム及びこれを含む半導体パッケージ
US7268427B2 (en) 2004-08-10 2007-09-11 Fujitsu Limited Semiconductor package, printed board mounted with the same, and electronic apparatus having the printed board
JP2012227337A (ja) * 2011-04-19 2012-11-15 Toyota Motor Corp 半導体装置
JP2018063999A (ja) * 2016-10-11 2018-04-19 トヨタ自動車株式会社 半導体装置

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