WO2013118275A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2013118275A1
WO2013118275A1 PCT/JP2012/052973 JP2012052973W WO2013118275A1 WO 2013118275 A1 WO2013118275 A1 WO 2013118275A1 JP 2012052973 W JP2012052973 W JP 2012052973W WO 2013118275 A1 WO2013118275 A1 WO 2013118275A1
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WIPO (PCT)
Prior art keywords
metal plates
metal plate
semiconductor elements
semiconductor device
longitudinal direction
Prior art date
Application number
PCT/JP2012/052973
Other languages
English (en)
French (fr)
Inventor
菊池　正雄
吉松　直樹
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2012/052973 priority Critical patent/WO2013118275A1/ja
Publication of WO2013118275A1 publication Critical patent/WO2013118275A1/ja

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Definitions

  • the present invention relates to a semiconductor device in which each member is covered with a resin, and more particularly, to a semiconductor device capable of preventing deformation due to a shrinkage rate or mechanical property difference between each member and the resin.
  • a semiconductor device is configured by mounting a semiconductor element on a metal plate, bonding a wiring member to the upper surface of the semiconductor element, and covering these members with a mold resin (for example, refer to Patent Document 1).
  • the shrinkage rate of each member and resin is different at the time of resin sealing, the outer shape of the device is deformed so as to swell or warp. Since the resin shrinks even when cured, the resin further promotes deformation. In addition, since the mechanical properties such as the linear expansion coefficient and elastic modulus of each member and the resin are different, the apparatus is deformed even when an environmental load such as a temperature cycle is applied.
  • This deformation causes stress inside the device, and damage may occur in parts with low mechanical strength such as solder and adhesive that join members having different physical properties. As a result, there is a problem that cracking progresses and the power transfer function is impaired, and the heat dissipation of the semiconductor element is deteriorated.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device capable of preventing deformation due to a difference in contraction rate or mechanical property between each member and resin. .
  • a semiconductor device is mounted on a first metal plate, a plurality of second metal plates that are spaced apart from each other and separated from each other, the first metal plate, and a lower surface that is mounted on the first metal plate.
  • a plurality of first semiconductor elements commonly bonded to the first metal plate and a plurality of first semiconductor elements mounted on the plurality of second metal plates, respectively, and a plurality of lower surfaces individually bonded to the plurality of second metal plates, respectively.
  • a wiring member, and a resin that covers the first and second metal plates, the first and second semiconductor elements, and the first and second wiring members are provided.
  • FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG.
  • FIG. 3 is a cross-sectional view taken along the line BB ′ of FIG.
  • FIG. 3 is a cross-sectional view taken along the line CC ′ of FIG.
  • FIG. 7 is a cross-sectional view taken along the line AA ′ of FIG.
  • FIG. 1 is a circuit diagram showing a semiconductor device according to an embodiment of the present invention.
  • Six pairs of transistor elements 1a to 1f and diodes 2a to 2f form a three-phase half-bridge circuit. Power from the power supply is supplied to the load via the U, V, and W terminals.
  • the transistor elements 1 a to 1 f are insulated gate bipolar transistors (IGBT: “Insulated Gate Gate Bipolar Transistor”) that conduct current supplied from a power source for a necessary time.
  • IGBT Insulated Gate Gate Bipolar Transistor
  • FIG. 2 is a transparent top view showing the inside of the semiconductor device according to the embodiment of the present invention.
  • 3 is a sectional view taken along the line AA ′ in FIG. 2
  • FIG. 4 is a sectional view taken along the line BB ′ in FIG. 2
  • FIG. 5 is a sectional view taken along the line CC ′ in FIG.
  • the metal plate 3a and the metal plates 3b to 3d are spaced apart from each other on the left and right.
  • the metal plates 3b to 3d are separated from each other.
  • Transistor elements 1a to 1c and diodes 2a to 2c are mounted side by side on a metal plate 3a, and their lower surfaces are commonly joined to the metal plate 3a with solder 4.
  • Transistor elements 1d to 1f and diodes 2d to 2f are mounted on metal plates 3b to 3d, respectively, and their lower surfaces are individually joined to metal plates 3b to 3d with solder 4, respectively.
  • Wiring members 5a to 5c separated from each other are individually joined by solder 4 to the upper surfaces of the transistor elements 1a to 1c.
  • a wiring member 5d is commonly bonded to the upper surfaces of the transistor elements 1d to 1f with solder 4.
  • a conductive adhesive or the like may be used instead of the solder 4.
  • the transistor elements 1a to 1c and the wiring members 5a to 5c are arranged side by side in the longitudinal direction of the metal plate 3a.
  • the metal plates 3b to 3d and the transistor elements 1d to 1f are arranged side by side in the longitudinal direction of the wiring member 5d.
  • the longitudinal direction of the metal plate 3a and the longitudinal direction of the wiring member 5d are parallel.
  • the wiring members 5a to 5c are connected to the metal plates 3b to 3d, respectively.
  • the signal wirings 6a to 6c are wire-connected to the control terminals of the transistor elements 1a to 1c, respectively.
  • the signal wirings 6d to 6f are wire-connected to the control terminals of the transistor elements 1d to 1f, respectively.
  • the metal plates 3a to 3d, the transistor elements 1a to 1f, the diodes 2a to 2f, a part of the wiring members 5a to 5d, and a part of the signal wirings 6a to 6fc are covered with a mold resin 7.
  • Wiring members 5a to 5d are responsible for power transmission / reception from the outside of the apparatus.
  • the wiring members 5a to 5d and the signal wirings 6a to 6f are formed in a state in which the same metal plate is punched or etched like a lead frame and integrally connected with an outer frame. A part thereof is covered with the mold resin 7 and mechanically held, and then the outer frame is removed to divide the wiring members 5a to 5d and the signal wirings 6a to 6f. As a result, a large number of wiring members 5a to 5d and signal wirings 6a to 6f can be assembled together, so that productivity is high and industrial value is high.
  • the wiring members 5a to 5c on the upper surfaces of the transistor elements 1d to 1f are separated from each other, but one metal plate 3a is commonly bonded to the lower surfaces of the transistor elements 1a to 1c.
  • the metal plates 3b to 3d on the lower surfaces of the transistor elements 1d to 1f are separated from each other, but a single wiring member 5d is commonly bonded to the upper surfaces of the transistor elements 1d to 1f. That is, the left side of the device is supported by a highly rigid metal plate 3a, and the right side of the device is supported by a highly rigid wiring member 5d.
  • the signal wirings 6a to 6f are inserted into through holes of an external control board (not shown) and soldered or press-fitted, positional accuracy is required. Therefore, in the present embodiment, the signal wirings 6a to 6c are provided side by side in the longitudinal direction of the metal plate 3a, and the signal wirings 6d to 6f are provided side by side in the longitudinal direction of the wiring member 5d. As a result, the signal wirings 6a to 6f are less likely to fall in the longitudinal direction due to the rigidity of the metal plate 3a and the wiring member 5d, and the positional accuracy is improved and the signal wirings 6a to 6f are easily inserted into the through holes.
  • the metal plates 3a to 3d must be insulated from each other.
  • the lower surfaces of the metal plates 3a to 3d are exposed from the mold resin 7. Therefore, when the semiconductor device is mounted on the cooler, it is necessary to sandwich an insulating layer therebetween.
  • FIG. 6 is a top view showing a modification of the semiconductor device according to the embodiment of the present invention.
  • FIG. 7 is a cross-sectional view taken along the line AA ′ of FIG.
  • an insulating layer 8 is provided on the lower surfaces of the metal plates 3a to 3d, and the insulating layer 8 is also integrally sealed with the mold resin 7 to constitute a semiconductor device. Even in this case, since the deformation of the device is small, the stress of the insulating layer 8 can be reduced.
  • the insulating layer 8 may be formed by providing a gap between the lower surface of the metal plates 3a to 3d and the bottom surface of the mold during resin sealing, and allowing the mold resin 7 to flow into the gap. It is good also as a member different from. The latter is preferable because the thermal conductivity of the insulating layer 8 can be improved.
  • the insulating layer 8 serves as a heat dissipation path of the semiconductor element, it is necessary to make it thin enough to ensure insulation to improve heat dissipation performance (to reduce thermal resistance). However, if the insulating layer 8 is made thin, it is easily damaged by deformation. On the other hand, since the device of the present embodiment is less deformed, the damage of the insulating layer 8 can be reduced and the reliability can be improved.
  • Individual insulating layers may be provided on the lower surfaces of the metal plates 3a to 3d, respectively, but one insulating layer 8 is integrally provided on the lower surfaces of all the metal plates 3a to 3d that require insulation on the lower surface side of the apparatus. Is preferred. Thereby, even if the apparatus is enlarged, an increase in stress can be avoided, and the deformation of the apparatus can be further reduced to ensure reliability. And since a number of members can be reduced, production improves. Furthermore, since the manufacturing is simplified, the quality is improved.
  • a metal plate made of the same kind of material as the metal plates 3a to 3d may be provided below the insulating layer 8. Thereby, the curvature at the time of a thermal cycle is suppressed, and the stress of the insulating layer 8 is reduced.
  • the metal plates 3a to 3d, the transistor elements 1a to 1f, the diodes 2a to 2f, and the wiring members 5a to 5d constitute a three-phase half bridge circuit.
  • This three-phase half-bridge circuit is used as an inverter circuit for controlling the power of a load such as a motor. By providing this circuit in one mold resin 7, a compact inverter control system and power converter can be realized.
  • the transistor elements 1a to 1f and the diodes 2a to 2f are not limited to those containing silicon as a main component, but may be those containing silicon carbide or gallium nitride as a main component. In this case, it can be operated at a higher temperature than an element mainly composed of silicon. As the temperature increases, the difference in linear expansion of the constituent members increases. However, in this embodiment, deformation of the device can be suppressed, and positional accuracy such as connection to the outside can be maintained.
  • an element mainly composed of silicon carbide or gallium nitride has high voltage resistance and high allowable current density, and thus can be miniaturized.
  • a semiconductor device incorporating this element can also be miniaturized.
  • the heat resistance of the element is high, the heat dissipating fins of the heat sink can be reduced in size and the water cooling part can be cooled in the air, so that the semiconductor device can be further reduced in size.
  • the power loss of the element is low and the efficiency is high, the semiconductor device can be highly efficient. It is desirable that both the transistor elements 1a to 1f and the diodes 2a to 2f are mainly composed of silicon carbide or gallium nitride, but only one of them may be used, and the effects described in this embodiment can be obtained. .
  • the cross-section of the wiring members 5a to 5d is not limited to a rectangle, but is preferably a shape that can achieve high rigidity, such as a rectangular U-shape or a rib shape.
  • the materials of the metal plates 3a to 3d and the wiring members 5a to 5d are materials having both electrical conductivity and mechanical strength. For example, materials mainly composed of copper or aluminum, alloys thereof, or composite materials including these materials. It is.
  • the mold resin 7 is made of a resin material such as epoxy, and is not limited to the transfer mold resin but may be a liquid potting resin.
  • Transistor element first semiconductor element 1d to 1f Transistor element (second semiconductor element) 3a Metal plate (first metal plate) 3b-3d metal plate (second metal plate) 5a to 5c Wiring member (first wiring member) 5d wiring member (second wiring member) 6a to 6c Signal wiring (first signal wiring) 6d to 6f Signal wiring (second signal wiring) 7 Mold resin (resin) 8 Insulating layer (insulating layer)

Abstract

　金属プレート３ａと金属プレート３ｂ～３ｄが離間して配置されている。金属プレート３ｂ～３ｄは互いに分離している。トランジスタ素子１ａ～１ｃが金属プレート３ａ上に実装され、それらの下面は金属プレート３ａに共通に接合されている。トランジスタ素子１ｄ～１ｆが金属プレート３ｂ～３ｄ上にそれぞれ実装され、それらの下面は金属プレート３ｂ～３ｄにそれぞれ個別に接合されている。互いに分離した配線部材５ａ～５ｃがトランジスタ素子１ａ～１ｃの上面にそれぞれ個別に接合されている。配線部材５ｄがトランジスタ素子１ｄ～１ｆの上面に共通に接合されている。金属プレート３ａ～３ｄ、トランジスタ素子１ａ～１ｆ、及び配線部材５ａ～５ｄはモールド樹脂７により覆われている。

Description

半導体装置
　本発明は、各部材を樹脂で覆った半導体装置に関し、特に各部材と樹脂の収縮率や機械的物性の違いによる変形を防止することができる半導体装置に関する。
　金属プレート上に半導体素子が実装され、半導体素子の上面に配線部材が接合され、これらの部材がモールド樹脂で覆われることで半導体装置が構成される（例えば、特許文献１参照）。
特開２００２－０３３４４５号公報
　樹脂封止時において各部材と樹脂の収縮率が異なるため、装置の外形はうねる又は反るように変形する。樹脂は硬化時にも収縮するために更に変形を助長する。また、各部材と樹脂の線膨張係数や弾性率などの機械的物性が異なるため、温度サイクルなどの環境負荷が加えられても装置は変形する。
　この変形により装置内部にストレスが生じて、物性が異なる各部材を接合するはんだや接着剤などの機械的強度が小さい部分にダメージが発生する場合が有った。この結果、割れが進展して電力の授受の機能を損ない、半導体素子の放熱性が悪化するという問題があった。
　また、変形が大きいと半導体装置を基板等の外部保持部材に固定する際に必要な外部荷重が大きくなる。この結果、半導体装置へのダメージが生じ、必要な外部荷重を与えるための構造物が大型化するなどの問題があった。
　本発明は、上述のような課題を解決するためになされたもので、その目的は各部材と樹脂の収縮率や機械的物性の違いによる変形を防止することができる半導体装置を得るものである。
　本発明に係る半導体装置は、第１金属プレートと、前記第１金属プレートとは離間して配置され、互いに分離した複数の第２金属プレートと、前記第１金属プレート上に実装され、下面が前記第１金属プレートに共通に接合された複数の第１半導体素子と、前記複数の第２金属プレート上にそれぞれ実装され、下面が前記複数の第２金属プレートにそれぞれ個別に接合された複数の第２半導体素子と、前記複数の第１半導体素子の上面にそれぞれ個別に接合され、互いに分離した複数の第１配線部材と、前記複数の第２半導体素子の上面に共通に接合された第２配線部材と、前記第１及び第２金属プレート、前記第１及び第２半導体素子、及び前記第１及び第２配線部材を覆う樹脂とを備えることを特徴とする。
　本発明により、各部材と樹脂の収縮率や機械的物性の違いによる変形を防止することができる。
本発明の実施の形態に係る半導体装置を示す回路図である。 本発明の実施の形態に係る半導体装置の内部を示す透視上面図である。 図２のＡ－Ａ´に沿った断面図である。 図２のＢ－Ｂ´に沿った断面図である。 図２のＣ－Ｃ´に沿った断面図である。 本発明の実施の形態に係る半導体装置の変形例を示す上面図である。 図６のＡ－Ａ´に沿った断面図である。
　本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
　図１は、本発明の実施の形態に係る半導体装置を示す回路図である。トランジスタ素子１ａ～１ｆとダイオード２ａ～２ｆの６つのペアが３相ハーフブリッジ回路を構成する。Ｕ、Ｖ、Ｗ端子を介して電源からの電力を負荷に供給する。トランジスタ素子１ａ～１ｆは、電源から供給される電流を必要な時間だけ導通する絶縁ゲート型バイポーラトランジスタ（IGBT: Insulated Gate Bipolar Transistor）である。ダイオード２ａ～２ｆは、トランジスタ素子１ａ～１ｆが導通状態から遮断状態になる際に、電流を還流させる。
　図２は、本発明の実施の形態に係る半導体装置の内部を示す透視上面図である。図３は図２のＡ－Ａ´に沿った断面図、図４は図２のＢ－Ｂ´に沿った断面図、図５は図２のＣ－Ｃ´に沿った断面図である。
　金属プレート３ａと金属プレート３ｂ～３ｄが左右に離間して配置されている。金属プレート３ｂ～３ｄは互いに分離している。トランジスタ素子１ａ～１ｃ及びダイオード２ａ～２ｃが金属プレート３ａ上に並んで実装され、それらの下面は金属プレート３ａにはんだ４で共通に接合されている。トランジスタ素子１ｄ～１ｆ及びダイオード２ｄ～２ｆが金属プレート３ｂ～３ｄ上にそれぞれ実装され、それらの下面は金属プレート３ｂ～３ｄにそれぞれはんだ４で個別に接合されている。互いに分離した配線部材５ａ～５ｃがトランジスタ素子１ａ～１ｃの上面にそれぞれはんだ４で個別に接合されている。配線部材５ｄがトランジスタ素子１ｄ～１ｆの上面にはんだ４で共通に接合されている。なお、はんだ４の代わりに導電性接着剤などを用いてもよい。
　トランジスタ素子１ａ～１ｃ及び配線部材５ａ～５ｃは金属プレート３ａの長手方向に並んで配置されている。金属プレート３ｂ～３ｄ及びトランジスタ素子１ｄ～１ｆは配線部材５ｄの長手方向に並んで配置されている。金属プレート３ａの長手方向と配線部材５ｄの長手方向は平行である。配線部材５ａ～５ｃは金属プレート３ｂ～３ｄにそれぞれ接続されている。
　信号配線６ａ～６ｃはトランジスタ素子１ａ～１ｃの制御端子にそれぞれワイヤ接続されている。信号配線６ｄ～６ｆはトランジスタ素子１ｄ～１ｆの制御端子にそれぞれワイヤ接続されている。これらの金属プレート３ａ～３ｄ、トランジスタ素子１ａ～１ｆ、ダイオード２ａ～２ｆ、配線部材５ａ～５ｄの一部、及び信号配線６ａ～６ｆｃの一部はモールド樹脂７により覆われている。
　配線部材５ａ～５ｄは装置外部との電力の授受を担っている。配線部材５ａ～５ｄ及び信号配線６ａ～６ｆは、例えばリードフレームのように同一の金属板を打ち抜き又はエッチングして外枠で一体的に連結した状態で形成される。その一部をモールド樹脂７で覆って機械的に保持してから外枠を除去して配線部材５ａ～５ｄ及び信号配線６ａ～６ｆを分割する。これにより、数の多い配線部材５ａ～５ｄ及び信号配線６ａ～６ｆを一括で組み付けすることができるので、生産性が良く、かつ工業上の価値が高くなる。
　ここで、装置の左側では、トランジスタ素子１ｄ～１ｆの上面の配線部材５ａ～５ｃは互いに分離しているが、一枚の金属プレート３ａがトランジスタ素子１ａ～１ｃの下面に共通に接合されている。装置の右側では、トランジスタ素子１ｄ～１ｆの下面の金属プレート３ｂ～３ｄは互いに分離しているが、一枚の配線部材５ｄがトランジスタ素子１ｄ～１ｆの上面に共通に接合されている。即ち、装置の左側は剛性の高い金属プレート３ａにより支持され、装置の右側は剛性の高い配線部材５ｄにより支持されている。
　このようにモールド樹脂７内部の強度のバランスを取ることで、各部材と樹脂の収縮率や機械的物性の違いによる装置の変形を防止することができる。これにより、装置内部に発生するストレスが小さくなる。また、半導体装置を外部保持部材に固定する際の取り付けやすさが向上する。さらに、装置を外部に接続する際の位置決め精度が向上する。
　また、信号配線６ａ～６ｆは、外部の制御基板（不図示）のスルーホールに挿入してはんだ付けされるか又は圧入されるため、位置精度が求められる。そこで、本実施の形態では、信号配線６ａ～６ｃを金属プレート３ａの長手方向に並んで設け、信号配線６ｄ～６ｆを配線部材５ｄの長手方向に並んで設けている。これにより、信号配線６ａ～６ｆは、金属プレート３ａ及び配線部材５ｄの剛性によってその長手方向の倒れが少なくなり、位置精度が向上してスルーホールに挿入しやすくなる。
　トランジスタ素子１ａ～１ｃ，１ｄ，１ｅ，１ｆの電源端子はそれぞれ電位が異なるため、互いに絶縁しなければならない。従って、金属プレート３ａ～３ｄは互いに絶縁しなければならない。上記の実施の形態では、金属プレート３ａ～３ｄの下面がモールド樹脂７から露出しているため、半導体装置を冷却器上に実装する場合には両者の間に絶縁層を挟む必要がある。
　図６は、本発明の実施の形態に係る半導体装置の変形例を示す上面図である。図７は図６のＡ－Ａ´に沿った断面図である。変形例では、金属プレート３ａ～３ｄの下面に絶縁層８を設け、絶縁層８もモールド樹脂７で一体的に封止して半導体装置を構成する。この場合でも装置の変形が少ないため、絶縁層８のストレスを低減することができる。
　絶縁層８は、樹脂封止時に金属プレート３ａ～３ｄの下面とモールド金型の底面との間に間隙を設けて、この間隙にモールド樹脂７を流入させて形成してもよく、モールド樹脂７とは別の部材としてもよい。後者は、絶縁層８の熱伝導率の向上が可能となるので好ましい。
　絶縁層８は、半導体素子の放熱経路となるため、絶縁が確保できる程度に薄くして放熱性能を良くする（熱抵抗を小さくする）必要がある。ただし、絶縁層８は薄くすると変形に対してダメージを受けやすくなる。これに対して、本実施の形態の装置は変形が少ないため、絶縁層８のダメージを低減して信頼性を向上させることができる。
　金属プレート３ａ～３ｄの下面にそれぞれ個別の絶縁層を設けてもよいが、装置下面側の絶縁が必要な全ての金属プレート３ａ～３ｄの下面に１枚の絶縁層８を一体的に設けるのが好ましい。これにより、装置を大型化してもストレスの増加が回避でき、装置の変形を更に低減して信頼性が確保できる。そして、部材点数を削減できるために生産が向上する。さらに、製造が簡略するために、品質も向上する。
　また、絶縁層８の下側にさらに金属プレート３ａ～３ｄと同種の材質からなる金属プレートを設けてもよい。これにより、冷熱サイクルが加わる際の反りが抑制されて絶縁層８のストレスが軽減される。
　また、金属プレート３ａ～３ｄ、トランジスタ素子１ａ～１ｆ、ダイオード２ａ～２ｆ、及び配線部材５ａ～５ｄは３相ハーフブリッジ回路を構成する。この３相ハーフブリッジ回路は、モータなどの負荷の電力制御をするインバータ回路として用いられる。この回路を１つのモールド樹脂７内に設けることでコンパクトなインバータ制御システムや電力変換装置を実現することができる。
　また、トランジスタ素子１ａ～１ｆ及びダイオード２ａ～２ｆは、珪素を主成分とするものに限らず、炭化珪素又は窒化ガリウムを主成分とするものでもよい。この場合には、珪素を主成分とする素子に比べて高温で動作させることができる。温度が高くなるほど構成部材の線膨張の差が大きくなるが、本実施の形態では装置の変形を抑制することができ、外部との接続などの位置精度を維持することができる。
　また、炭化珪素又は窒化ガリウムを主成分とする素子は、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された素子を用いることで、この素子を組み込んだ半導体装置も小型化できる。また、素子の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体装置を更に小型化できる。また、素子の電力損失が低く高効率であるため、半導体装置を高効率化できる。なお、トランジスタ素子１ａ～１ｆ及びダイオード２ａ～２ｆの両方が炭化珪素又は窒化ガリウムを主成分とすることが望ましいが、何れか一方だけでもよく、この実施の形態に記載の効果を得ることができる。
　なお、配線部材５ａ～５ｄの断面は矩形に限らず、直角のコの字状やリブ状など高剛性化が図れる形状であれば更に好ましい。また、金属プレート３ａ～３ｄ及び配線部材５ａ～５ｄの材質は、導電性と機械的強度を併せ持つ材料であり、例えば銅又はアルミを主成分とする材料、これらの合金、又はこれらを含む複合材である。また、モールド樹脂７はエポキシなどの樹脂材料からなり、トランスファモールド樹脂に限らず、液状ポッティング樹脂などでもよい。
１ａ～１ｃ　トランジスタ素子（第１半導体素子）
１ｄ～１ｆ　トランジスタ素子（第２半導体素子）
３ａ　金属プレート（第１金属プレート）
３ｂ～３ｄ　金属プレート（第２金属プレート）
５ａ～５ｃ　配線部材（第１配線部材）
５ｄ　配線部材（第２配線部材）
６ａ～６ｃ　信号配線（第１信号配線）
６ｄ～６ｆ　信号配線（第２信号配線）
７　モールド樹脂（樹脂）
８　絶縁層（絶縁層）

Claims (7)

  1. 　第１金属プレートと、
    　前記第１金属プレートとは離間して配置され、互いに分離した複数の第２金属プレートと、
    　前記第１金属プレート上に実装され、下面が前記第１金属プレートに共通に接合された複数の第１半導体素子と、
    　前記複数の第２金属プレート上にそれぞれ実装され、下面が前記複数の第２金属プレートにそれぞれ個別に接合された複数の第２半導体素子と、
    　前記複数の第１半導体素子の上面にそれぞれ個別に接合され、互いに分離した複数の第１配線部材と、
    　前記複数の第２半導体素子の上面に共通に接合された第２配線部材と、
    　前記第１及び第２金属プレート、前記第１及び第２半導体素子、及び前記第１及び第２配線部材を覆う樹脂とを備えることを特徴とする半導体装置。
  2. 　前記複数の第１半導体素子及び前記複数の第１配線部材は前記第１金属プレートの長手方向に並んで配置され、
    　前記複数の第２金属プレート及び前記複数の第２半導体素子は前記第２配線部材の長手方向に並んで配置され、
    　前記第１金属プレートの長手方向と前記第２配線部材の長手方向は平行であることを特徴とする請求項１に記載の半導体装置。
  3. 　前記複数の第１半導体素子の制御端子にそれぞれ接続され、前記樹脂の外部に導出され、前記第１金属プレートの長手方向に並んで設けられた複数の第１信号配線と、
    　前記複数の第２半導体素子の制御端子にそれぞれ接続され、前記樹脂の外部に導出され、前記第２配線部材の長手方向に並んで設けられた複数の第２信号配線とを更に備えることを特徴とする請求項１又は２に記載の半導体装置。
  4. 　前記複数の第１配線部材は前記複数の第２金属プレートにそれぞれ接続され、
    　前記第１及び第２金属プレート、前記第１及び第２半導体素子、及び前記第１及び第２配線部材は３相ハーフブリッジ回路を構成することを特徴とする請求項１～３に記載の半導体装置。
  5. 　前記複数の第２金属プレートの下面に設けられた絶縁層を更に備えることを特徴とする請求項１～４に記載の半導体装置。
  6. 　前記絶縁層は前記第１金属プレート及び前記複数の第２金属プレートの下面に一体的に設けられていることを特徴とする請求項５に記載の半導体装置。
  7. 　前記第１及び第２半導体素子は炭化珪素又は窒化ガリウムを主成分とすることを特徴とする請求項１～６に記載の半導体装置。
PCT/JP2012/052973 2012-02-09 2012-02-09 半導体装置 WO2013118275A1 (ja)

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JP2018029201A (ja) * 2017-10-13 2018-02-22 ローム株式会社 半導体装置
WO2018193581A1 (ja) * 2017-04-20 2018-10-25 三菱電機株式会社 電力変換装置
JP2018182220A (ja) * 2017-04-20 2018-11-15 三菱電機株式会社 電力変換装置
EP3474322A1 (en) * 2017-10-23 2019-04-24 Nexperia B.V. Semiconductor device and method of manufacture
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JP2011249364A (ja) * 2010-05-21 2011-12-08 Denso Corp 半導体モジュールおよびその製造方法
JP2011253862A (ja) * 2010-06-01 2011-12-15 Mitsubishi Electric Corp パワー半導体装置

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JP2011249364A (ja) * 2010-05-21 2011-12-08 Denso Corp 半導体モジュールおよびその製造方法
JP2011253862A (ja) * 2010-06-01 2011-12-15 Mitsubishi Electric Corp パワー半導体装置

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10777542B2 (en) 2014-03-04 2020-09-15 Rohm Co., Ltd. Power semiconductor module for an inverter circuit and method of manufacturing the same
US10784214B2 (en) * 2017-02-06 2020-09-22 Fuji Electric Co., Ltd. Semiconductor module, electric automobile and power control unit
WO2018193581A1 (ja) * 2017-04-20 2018-10-25 三菱電機株式会社 電力変換装置
JP2018182220A (ja) * 2017-04-20 2018-11-15 三菱電機株式会社 電力変換装置
JPWO2018193581A1 (ja) * 2017-04-20 2019-11-07 三菱電機株式会社 電力変換装置
JP2018029201A (ja) * 2017-10-13 2018-02-22 ローム株式会社 半導体装置
EP3474322A1 (en) * 2017-10-23 2019-04-24 Nexperia B.V. Semiconductor device and method of manufacture
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