CN106571344B - 封装胶体包裹的封装基材 - Google Patents

封装胶体包裹的封装基材 Download PDF

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CN106571344B
CN106571344B CN201610666741.2A CN201610666741A CN106571344B CN 106571344 B CN106571344 B CN 106571344B CN 201610666741 A CN201610666741 A CN 201610666741A CN 106571344 B CN106571344 B CN 106571344B
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redistribution circuit
circuit
redistribution
dielectric layer
disposed
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CN106571344A (zh
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胡迪群
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Abstract

本发明公开了一种封装胶体包裹的封装基材，包括重新分配电路、多个顶部开口、封装胶体和多个底部开口，重新分配电路埋设于介电层中，具有多个顶部金属垫和多个底部金属垫；重新分配电路的电路向下扇出，使得底部金属垫的密度低于顶部金属垫的密度；多个顶部开口设置于介电层的顶面，每个顶部开口裸露一个对应的顶部金属垫的顶表面；封装胶体包裹介电层的四个侧面和底面；多个底部开口设置于封装胶体的底面，每个底部开口裸露一个对应的底部金属垫的底面。封装胶体包裹薄膜封装基材的侧面和底面，使薄膜封装基材不发生皱褶。

Description

封装胶体包裹的封装基材
技术领域
本发明涉及半导体芯片的封装基材，特别是一种具有封装胶体包裹四个侧面和底面作为支撑，用以避免皱褶(wrinkles)的产生的一种薄膜封装基材。
背景技术
如图1所示，美国专利US20120146209A1公开的一种习知的芯片封装用基材，显示一个具有复数个通孔(through hole)212的中介层(interposer)21，上层电路重新分配层213设置于中介层21的上方，中介层21埋设于封装胶体22中；封装胶体22具有裸露的第一表面22a、以及一个第二表面22b，芯片27设置于第一表面22a上方。增层结构24设置于封装胶体22的下方，即是第二表面22b。增层结构24包括有介电层240和布线层241，导通金属242设置于介电层240中，用以电性耦合纵向导通金属210与布线层241；防焊层25设置于增层结构24下方，并且让复数个金属垫243裸露于下方；中介层21系由玻璃或是陶瓷所制成，例如Al2O3和AlN，其中的陶瓷具有热膨胀系数(Coefficient Thermal Expansion；CTE)约3ppm/℃，即接近硅的热膨胀系数。芯片27通过焊锡球271电性耦合至金属垫211以及上层电路重新分配层213；底部填充材料270填充在金属垫211和芯片27之间的空间中；多个焊锡球26设置于金属垫243作为芯片封装电性耦合至外部印刷电路板(图中未显示)用。
习知技术的封装基材，主要是由玻璃/陶瓷制成的中介层21作为支撑。然而，半导体封装技术进步的速度越来越快，近期以来，不具有中介层的高密度薄膜封装基材被开发，由于CTE不匹配问题，薄膜封装基材会有皱褶或是板翘问题，需要开发一种新的支撑结构，用以提供高密度薄膜封装基材的支撑坚硬度，是近来研发人员的一大研究课题。
发明内容
针对现有技术的上述不足，根据本发明的实施例，希望提供一种可避免皱褶(wrinkles)或板翘的产生，用以提供高密度薄膜封装基材的支撑坚硬度之封装胶体包裹的封装基材。
根据实施例，本发明提供的一种封装胶体包裹的封装基材，包括重新分配电路、多个顶部开口、封装胶体和多个底部开口，其中：
重新分配电路埋设于介电层中，具有多个顶部金属垫和多个底部金属垫；重新分配电路的电路向下扇出，使得底部金属垫的密度低于顶部金属垫的密度；
多个顶部开口设置于介电层的顶面，每个顶部开口裸露一个对应的顶部金属垫的顶表面；
封装胶体包裹介电层的四个侧面和底面；
多个底部开口设置于封装胶体的底面，每个底部开口裸露一个对应的底部金属垫的底面。
根据实施例，本发明提供的另一种封装胶体包裹的封装基材，包括第一重新分配电路、第二重新分配电路、多个顶部开口、封装胶体和多个底部开口，其中：
第一重新分配电路依据第一设计准则所制作，具有埋设于第一介电层中的第一重新分配电路；第一重新分配电路具有多个第一顶部金属垫和多个第一底部金属垫；
第二重新分配电路设置于第一重新分配电路的底面，依据第二设计准则所制作，其具有埋设于第二介电层中的第二重新分配电路；第二重新分配电路具有多个第二顶部金属垫和多个第二底部金属垫；每个第二顶部金属垫电性耦合至对应的第一底部金属垫；第一重新分配电路的电路向下扇出，使得第一底部金属垫的密度低于第一顶部金属垫的密度；第二重新分配电路的电路向下扇出，使得第二底部金属垫的密度低于第二顶部金属垫的密度；第二设计准则比第一设计准则具有较低的电路密度；
多个顶部开口设置于第一介电层的顶面，每个顶部开口裸露一个对应的第一顶部金属垫的顶表面；
封装胶体包裹介电层的四个侧面和最底层介电层的底面；
多个底部开口设置于封装胶体的底面，每个底部开口裸露一个对应的第二底部金属垫的底面。
相对于现有技术，本发明提供的两种封装胶体(molding compound)包裹的高密度薄膜封装基材(package substrate)，封装胶体提供薄膜封装基材的坚硬度与稳定性。封装基材顶部具有裸露金属垫，提供芯片安装；封装基材底部具有焊锡球，提供芯片封装(chippackage)安装到外部的系统板。封装胶体包裹在封装基材(package substrate)至少四个侧面以及底面，用以支撑薄膜封装基材，使薄膜封装基材不发生皱褶，避免了皱褶(wrinkles)的产生，使其保持尺寸稳定性。另外，包含金属柱设置于电路下方且被封装胶体包裹周边，提高了薄膜封装基材的稳定性。
附图说明
图1为一个习知技术的结构示意图。
图2A～2B为本发明的第一实施例的结构示意图。
图3A～3B为本发明的第二实施例的结构示意图。
图4A～4B为本发明的第三实施例的结构示意图。
图5A～图5B为本发明的第四实施例的结构示意图。
图6A～6B为本发明的第五实施例的结构示意图。
图7A～7B为本发明的第六实施例的结构示意图。
图8A～8B为本发明第七实施例的结构示意图。
图9A～图9B为本发明的第八实施例的结构示意图。
图10A～10B为图9A～9B的顶视图。
其中：31为重新分配电路；31B为底部金属垫；31D为介电层；31T为顶部金属垫；321为顶部开口；33为金属柱；35为封装胶体；351为底部开口；36为芯片；37为焊锡球；381、382为芯片；41为左边重新分配电路；411为右边重新分配电路；412为横向导通电路；412T、413T为顶部金属垫；41B为底部金属垫；41D为介电层；41T为顶部金属垫；421为底部开口；43为金属柱；45为封装胶体；451为底部开口；452为底部开口；461、462为芯片；47为焊锡球；48为底部凹槽；481、482为芯片；51为重新分配电路；51B为底部金属垫；51D为介电层；51T为顶部金属垫；52为重新分配电路；521为顶部开口；52B为底部金属垫；52D为介电层；52T为顶部金属垫；53为金属柱；55为封装胶体；551为底部开口；56为芯片；57为焊锡球；61为重新分配电路；611为重新分配电路；612为横向导通电路；612T为顶部金属垫；613T为顶部金属垫；61B为底部金属垫；61D为介电层；61T为顶部金属垫；62为重新分配电路；621为底部开口；622为重新分配电路；62B为底部金属垫；62D为介电层；62T为顶部金属垫；63为金属柱；65为封装胶体；651为底部开口；652为底部开口；66为芯片；661、662为芯片；67为焊锡球；68为底部凹槽；681、682为芯片。
具体实施方式
下面结合附图和具体实施例，进一步阐述本发明。这些实施例应理解为仅用于说明本发明而不用于限制本发明的保护范围。在阅读了本发明记载的内容之后，本领域技术人员可以对本发明作各种改动或修改，这些等效变化和修改同样落入本发明权利要求所限定的范围。
图2A～2B显示本发明的第一实施例。
图2A显示本发明的第一封装基材。
图2A显示一个电路重新分配层(RDL)，具有埋设于介电层31D的重新分配电路31；重新分配电路31具有多个顶部金属垫31T和多个底部金属垫31B；重新分配电路31的电路向下扇出，使得底部金属垫31B的密度低于顶部金属垫31T的密度。多个顶部开口321设置于介电层31D的顶面上，每个顶部开口321裸露一个对应的顶部金属垫31T的顶表面。封装胶体35包装介电层31D四个侧面和底面；多个底部开口351设置于封装胶体35的底面上，每个开口351裸露一个对应的底部金属垫31B的底面。
图2B显示使用图2A的封装基材的一个芯片封装。
图2B显示至少一个芯片36设置于重新分配电路31的上面且电性耦合至重新分配电路31；多个焊锡球37设置于重新分配电路31的底部，每个焊锡球37设置于一个对应的底部金属垫31B下方。
图3A～3B显示本发明的第二实施例。
图3A显示图2A的修饰结构。
图3A显示一个电路重新分配层(RDL)，具有埋设于介电层31D的重新分配电路31；其中，重新分配电路31具有多个顶部金属垫31T和多个底部金属垫31B；重新分配电路31的电路向下扇出，使得底部金属垫31B的密度低于顶部金属垫31T的密度。多个金属柱33设置于重新分配电路31的底部，每个金属柱33设置于一个对应的底部金属垫31B的底面。多个顶部开口321设置于介电层31D的顶部，每个顶部开口321裸露一个对应的顶部金属垫31T的顶表面。封装胶体35包装介电层31D的四个侧面和底面；多个底部开口351设置于封装胶体35的底面，每个底部开口351裸露一个对应的金属柱33的底面。
图3B显示使用图3A的封装基材的一个芯片封装。
图3B显示至少一个芯片36设置于重新分配电路31的上面且电性耦合至重新分配电路31；多个焊锡球37设置于重新分配电路31的底部，每个焊锡球37分别设置于一个对应的金属柱33的底面。
图4A～4B显示本发明的第三实施例。
图4A显示图3A的修饰结构。图4A显示封装基材中的重新分配层RDL，包括有左边重新分配电路41和右边重新分配电路411，这两个重新分配电路41、411埋设于介电层41D中。左边重新分配电路41具有多个顶部金属垫41T和多个底部金属垫41B；左边重新分配电路41的电路向下扇出，使得底部金属垫的密度41B低于顶部金属垫41T的密度。右边重新分配电路411具有多个顶部金属垫和多个底部金属垫；右边重新分配电路411电路向下扇出，使得底部金属垫的密度低于顶部金属垫的密度。多个顶部开口421设置于介电层41D的顶面；每个顶部开口421裸露一个对应的顶部金属垫41T的顶表面。
多个金属柱43设置于重新分配电路41、411的底面，每个金属柱43分别设置于一个对应的底部金属垫41B的底面。封装胶体45包裹介电层41D四个侧面和底面；封装胶体45也包裹多个金属柱43；多个底部开口451设置于封装胶体45的底面，每个开口451裸露一个对应的金属柱43的底面。
横向导通电路412设置于左边重新分配电路41和右边重新分配电路411之间；横向导通电路412具有多个左边顶部金属垫412T和多个右边顶部金属垫413T裸露于介电层41D的顶面。
图4B显示使用图4A的封装基材的一个芯片封装。
图4B显示至少一个左边芯片461与一个右边芯片462分别设置于重新分配电路41、411上面；左边芯片461设置于左边重新分配电路41的上面且电性耦合至左边重新分配电路41；右边芯片462设置于右边重新分配电路411的上面且电性耦合至右边重新分配电路411。多个焊锡球47设置于重新分配电路41、411底部，每个焊锡球47设置于一个对应的金属柱43的底面；横向导通电路412设置于第一芯片461和第二芯片462相邻处的下方，提供芯片之间最短路径的电性耦合。
图5A～图5B显示本发明的第四实施例。
图5A显示图4A的修饰结构。
图5A显示一个底部凹槽48设置于介电层41D的底部，封装胶体45环绕底部凹槽48外围周边；多个底部开口452设置于底部凹槽48内，每一个开口452裸露一个对应的底部金属垫41B的底面。
图5B显示使用图5A的封装基材的一个芯片封装。
图5B显示两个芯片481、482电性耦合至底部凹槽48内的底部金属垫41B；多个焊锡球47设置于重新分配电路41、411的底面，每个焊料球47设置于一个对应的金属柱43的底面。
图6A～6B显示本发明的第五实施例。
图6A显示本发明的另外一个封装基材。
图6A显示一个具有第一电路重新分配层RDL1以及第二电路重新分配层RDL2的封装基材。其中，第一电路重新分配层RDL1是依据第一设计准则所制作者。第一电路重新分配层RDL1具有埋设于第一介电层51D的第一重新分配电路51；第一重新分配电路51具有多个第一顶部金属垫51T和多个第一底部金属垫51B。
第二电路重新分配层RDL2设置于第一电路重新分配层RDL1的底面，且电性耦合至第一电路重新分配层RDL1。第二电路重新分配层RDL2是依据第二设计准则所制作者，RDL2具有埋设于第二介电层52D的第二重新分配电路52。第二重新分配电路52具有多个第二顶部金属垫52T和多个第二底部金属垫52B；每个第二顶部金属垫52T电性耦合至对应的第一底部金属垫51B；第一重新分配电路51的电路向下扇出，使得第一底部金属垫51B的密度低于第一顶部金属垫51T的密度；第二重新分配电路52的电路向下扇出，使得第二底部金属垫52B的密度低于第二顶部金属垫52T的密度。其中，第二设计准则具有比第一设计准则较低的电路密度。多个顶部开口521设置于第一介电层51D的顶面；每个顶部开口521裸露一个对应的第一顶部金属垫51T的顶表面；封装胶体55封装第一电路重新分配层RDL1以及第二电路重新分配层RDL2的四个侧面和第二电路重新分配层RDL2的底面；多个底部开口551设置于封装胶体55的底面，每个底部开口551裸露一个对应的第二底部金属垫52B的底面。
图6B显示使用图6A的封装基材的一个芯片封装。
图6B显示至少一个芯片56设置于第一电路重新分配层RDL1上方且电性耦合至第一重新分配电路51；多个焊锡球57设置于第二重新分配电路52的底面，每个焊锡球57设置于一个对应的第二金属垫52B的底面。
图7A～7B显示本发明的第六实施例。
图7A显示本发明的另外一个封装基材。图7A显示一个具有第一电路重新分配层RDL1、第二电路重新分配层RDL2以及底部金属柱53的封装基材。第一电路重新分配层RDL1是依据第一设计准则所制作，第一电路重新分配层RDL1具有埋设于第一介电层51D的第一重新分配电路51；第一重新分配电路51具有多个第一顶部金属垫51T和多个第一底部金属垫51B。第二电路重新分配层RDL2设置于第一电路重新分配层RDL1的底面且电性耦合至第一电路重新分配层RDL1；RDL2是依据第二设计准则所制作，第二电路重新分配层RDL2具有埋设于第二介电层52D的第二重新分配电路52；第二重新分配电路52具有多个第二顶部金属垫52T和多个第二底部金属垫52B。每个第二顶部金属垫52T分别电性耦合至一个对应的第一底部金属垫51B。第一重新分配电路51的电路向下扇出，使得第一底部金属垫51B的密度低于第一顶部金属垫51T的密度；第二重新分配电路52的电路向下扇出，使得第二底部金属垫52B的密度低于第二顶部金属垫52T的密度。其中，第二设计准则具有比第一设计准则具有较低的电路密度。
多个金属柱53设置于第二重新分配电路52下方，每个金属柱53设置于一个对应的金属垫52B的底面；多个顶部开口521设置于第一介电层51D的顶面，每个顶部开口521裸露一个对应的第一顶部金属垫51T的顶表面；封装胶体55封装第一介电层51D的侧面、也封装第二介电层52D与金属柱53的侧面和底面；多个底部开口551设置于封装胶体55的底面，每个开口551裸露一个对应的金属柱53的底面。
图7B显示使用图7A的封装基材的一个芯片封装。
图7B显示至少一个芯片56设置于第一重新分配电路51上方且电性耦合至第一重新分配电路51；多个金属柱53设置于第二重新分配电路52的底面；多个焊锡球57设置于封装基材的下方，每个焊锡球57设置于一个对应的金属柱53的底面。
图8A～8B显示本发明第七实施例。
图8A显示本发明另一个封装基材。图8A显示一个具有第一电路重新分配层RDL1、第二电路重新分配层RDL2、多个金属柱63的封装基材；第一电路重新分配层RDL1是依据第一设计准则所制作；第一电路重新分配层RDL1具有第一重新分配电路61,611埋设于第一介电层61D中；第一重新分配电路61，611具有多个第一顶部金属垫61T以及多个第一底部金属垫61B。
第二电路重新分配层RDL2是依据第二设计准则所制作的，第二电路重新分配层RDL2设置于第一电路重新分配层RDL1的底面。第二电路重新分配层RDL2具有第二重新分配电路62,622埋设于第二介电层62D中；第二重新分配电路62,622具有多个第二顶部金属垫62T和多个第二底部金属垫62B。其中的第二设计准则具有比第一设计准则低的电路密度，第一重新分配电路还包括：第一左边重新分配电路61埋设于第一介电层61D中，具有多个第一顶部金属垫61T和多个第一底部金属垫61B；第一右边重新分配电路611，埋设于第一介电层61D中，具有多个第一顶部金属垫和多个第一底部金属垫。
第二重新分配电路包括：第二左边重新分配电路62，埋设于第二介电层62D，具有多个第二顶部金属垫62T和多个第二底部金属垫62B；第二右边重新分配电路622，埋设于第二介电层62D中，具有多个第二顶部金属垫62T和多个第二底部金属垫62B；每个第二顶部金属垫62T电性耦合至对应的第一底部金属垫61B。第一重新分配电路61、611的电路向下扇出，使得第一底部金属垫61B的密度低于第一顶部金属垫61T的密度。第二重新分配电路62、622的电路向下扇出，使得第二底部金属垫62B的密度比第二顶部金属垫62T的密度低。多个顶部开口621设置于第一介电层61D的顶面，每个顶部开口621裸露一个对应的第一顶部金属垫61T的顶表面。
多个金属柱63设置于第二重新分配电路62下方，每个金属柱63设置于一个对应的第二底部金属垫62B的底面。封装胶体65封装第一介电层61D、第二介电层62D以及金属柱63的侧面；多个底部开口651设置于封装胶体65的底面，每个开口651裸露一个对应的金属柱63的底面。
横向导通电路612是依据第一设计准则所制作，设置于第一左边重新分配电路61和第一右边重新分配电路611之间；多个顶部金属垫612T、613T，裸露于第一介电层61D的顶面。横向导通电路612，借着顶部金属垫613T电性耦合至上方的芯片661、662，提供相邻芯片最短路径的电性耦合。
图8B显示使用图8A的封装基材的一个芯片封装。
图8B显示两个芯片661、662设置于第一重新分配电路的顶部，横向导通电路612电性耦合至上方的两个芯片661、662，提供芯片661、662之间最短路径的电性耦合。多个焊锡球67设置于第二个重新分配电路62的底面，每个焊锡球67设置于一个对应的金属柱63的底部。
图9A～图9B显示本发明的第八实施例。
图9A是图8A的修饰结构。
图9A显示一个底部凹槽68设置于第二介电层62D的下方，封装胶体65设置于底部凹槽68的周边；多个底部开口652设置于第二介电层62D的底面且位于底部凹槽68内，每个开口652分别裸露一个对应的第二金属垫62B的底面。
图9B显示使用图9A的封装基材的一个芯片封装。
图9B显示的芯片681、682设置于底部凹槽68内，多个金属柱63分别设置于一个对应的第二底部金属垫62B的下方；多个焊锡球67设置于第二个重新分配电路62的底面，每个焊料球67设置于一个对应的金属柱63的底面。
图10A～10B分别显示图9A～9B的顶视图。
图10A显示图9A的顶视图。图10A显示封装胶体65包裹在第一介电层61D的四边，横向导通电路612埋设于第一介电层61D中。
图10B显示图9B的顶视图。图10B显示第一介电层61D的顶表面上配置的芯片661、662，横向导通电路612埋设于第一介电层61D内，提供芯片661、662芯片之间的最短距离的电性耦合。

Claims (13)

1.一种封装胶体包裹的封装基材，其特征是，所述封装基材包括：
重新分配电路埋设于介电层中，具有多个顶部金属垫和多个底部金属垫；所述重新分配电路的电路向下扇出，使得所述底部金属垫的密度低于所述顶部金属垫的密度；
多个顶部开口设置于所述介电层的顶面，每个所述顶部开口裸露一个对应的所述顶部金属垫的顶表面；
封装胶体包裹所述介电层的四个侧面和底面；
多个底部开口设置于所述封装胶体的底面；
多个金属柱设置于所述重新分配电路的底面且每个所述金属柱设置于一个对应的所述底部金属垫的底面，所述封装胶体包裹所述金属柱的侧面，每个所述底部开口裸露一个对应的所述金属柱的底面；以及
多个焊锡球，每个所述焊锡球设置于一个对应的所述金属柱的所述底面。
2.如权利要求1所述的封装胶体包裹的封装基材，其特征是，还包括至少一个芯片，所述芯片设置于所述重新分配电路的顶面且电性耦合至所述重新分配电路的所述顶部金属垫。
3.如权利要求1所述的封装胶体包裹的封装基材，其特征是，所述重新分配电路包含左边重新分配电路和右边重新分配电路。
4.如权利要求3所述的封装胶体包裹的封装基材，其特征是，还包括横向导通电路，所述横向导通电路设置于所述左边重新分配电路和所述右边重新分配电路之间。
5.如权利要求1所述的封装胶体包裹的封装基材，其特征是，还包括左边芯片与右边芯片以及横向导通电路，所述左边芯片与右边芯片设置于所述重新分配电路上方且电性耦合至所述重新分配电路；所述横向导通电路具有多个顶部金属垫，分别电性耦合至上方的所述左边芯片与所述右边芯片，所述横向导通电路提供相邻的所述左边芯片与所述右边芯片之间最短路径的电性耦合。
6.如权利要求1所述的封装胶体包裹的封装基材，其特征是，还包括底部凹槽和多个开口，所述底部凹槽设置于所述介电层的所述底面；所述封装胶体包围所述底部凹槽的周边；所述开口设置于所述底部凹槽内所述介电层的所述底面，每个所述开口裸露一个对应的所述底部金属垫的所述底面。
7.如权利要求6所述的封装胶体包裹的封装基材，其特征是，还包括至少一个芯片，所述芯片设置于所述底部凹槽内，且电性耦合至所述底部凹槽内的所述底部金属垫。
8.一种封装胶体包裹的封装基材，其特征是，所述封装基材包括：
第一重新分配电路依据第一设计准则所制作，具有埋设于第一介电层中的第一重新分配电路；所述第一重新分配电路具有多个第一顶部金属垫和多个第一底部金属垫；
第二重新分配电路设置于所述第一重新分配电路的底面，所述第二重新分配电路依据第二设计准则所制作，其具有埋设于第二介电层中的第二重新分配电路；所述第二重新分配电路具有多个第二顶部金属垫和多个第二底部金属垫；每个所述第二顶部金属垫电性耦合至对应的所述第一底部金属垫；所述第一重新分配电路的电路向下扇出，使得所述第一底部金属垫的密度低于所述第一顶部金属垫的密度；所述第二重新分配电路的电路向下扇出，使得所述第二底部金属垫的密度低于所述第二顶部金属垫的密度；所述第二设计准则比所述第一设计准则具有较低的电路密度；
多个顶部开口设置于所述第一介电层的顶面，每个所述顶部开口裸露一个对应的所述第一顶部金属垫的顶表面；
封装胶体包裹所述第一介电层和所述第二介电层的四个侧面和所述第二介电层的底面；
多个底部开口设置于所述封装胶体的底面；
多个金属柱设置于所述第二重新分配电路的底面且每个所述金属柱分别设置于一个对应的所述第二底部金属垫的底面，所述封装胶体包裹金属柱的侧面，每个所述底部开口裸露一个对应的所述金属柱的底面；以及
多个焊锡球，每个所述焊锡球设置于一个对应的所述金属柱的所述底面。
9.如权利要求8所述的封装胶体包裹的封装基材，其特征是，还包括至少一个芯片，所述芯片设置于所述第一重新分配电路的顶面且电性耦合至所述第一重新分配电路的所述第一顶部金属垫。
10.如权利要求8所述的封装胶体包裹的封装基材，其特征是，所述第一重新分配电路还包括第一左边重新分配电路与第一右边重新分配电路；所述第二重新分配电路还包括第二左边重新分配电路与第二右边重新分配电路；所述第二左边重新分配电路电性耦合至所述第一左边重新分配电路；所述第二右边重新分配电路电性耦合至所述第一右边重新分配电路。
11.如权利要求10所述的封装胶体包裹的封装基材，其特征是，还包括横向导通电路，所述横向导通电路依据所述第一设计准则制作，设置于所述第一左边重新分配电路与所述第一右边重新分配电路之间，所述横向导通电路具有多个顶部金属垫裸露于所述第一介电层的所述顶面。
12.如权利要求11所述的封装胶体包裹的封装基材，其特征是，还包括左边芯片与右边芯片，所述左边芯片与所述右边芯片分别电性耦合至所述横向导通电路的所述顶部金属垫，使得所述左边芯片和所述右边芯片以最短路径做电性耦合。
13.如权利要求8所述的封装胶体包裹的封装基材，其特征是，还包括底部凹槽和多个开口，所述底部凹槽设置于所述第二介电层的所述底面，所述封装胶体包围所述底部凹槽的周边；所述开口设置于所述底部凹槽内所述第二介电层的所述底面，每个所述开口裸露一个对应的所述第二底部金属垫的所述底面。
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