TW201916306A - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TW201916306A
TW201916306A TW106139723A TW106139723A TW201916306A TW 201916306 A TW201916306 A TW 201916306A TW 106139723 A TW106139723 A TW 106139723A TW 106139723 A TW106139723 A TW 106139723A TW 201916306 A TW201916306 A TW 201916306A
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Taiwan
Prior art keywords
dielectric
interposer
layer
conductive
dielectric layer
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TW106139723A
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TWI780081B (zh
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丁國強
吳集錫
侯上勇
俞篤豪
許家豪
林品佐
陳家新
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台灣積體電路製造股份有限公司
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Publication of TWI780081B publication Critical patent/TWI780081B/zh

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Abstract

根據本發明之一些實施例，一種半導體元件包括：一電介質中介層、一第一互連層、一電子組件、複數個電導體及複數個導電結構。該電介質中介層具有一第一表面及與該第一表面相對之一第二表面。該第一互連層在該電介質中介層之該第一表面之上。該電子組件在該第一互連層之上且電連接至該第一互連層。該等電導體在該電介質中介層之該第二表面之上。該等導電結構穿過該電介質中介層，其中該等導電結構電連接至該第一互連層及該等電導體。

Description

半導體元件及其製造方法
本揭示係關於半導體元件及其製造方法。
在積體電路之封裝中，半導體晶粒可藉由接合來堆疊，且堆疊式電子組件之間的互連件可藉由矽中介層來實施。矽中介層具有高介電常數，且因此經受電流洩漏及RC延遲。另外，矽中介層之厚度之減小由於其材料性質而受限制，且不能最小化半導體元件之整體體積。
根據本發明之一實施例，一種半導體結構包含：電介質中介層，其具有第一表面及與該第一表面相對之第二表面；第一互連層，其在該電介質中介層之該第一表面之上；電子組件，其在該第一互連層之上且電連接至該第一互連層；複數個電導體，其在該電介質中介層之該第二表面之上；及複數個導電結構，其穿過該電介質中介層，其中該等導電結構電連接至該第一互連層及該等電導體。 根據本發明之一實施例，一種半導體結構包含：非半導電電介質中介層，其具有第一表面及與該第一表面相對之第二表面；第一互連層，其在該非半導電電介質中介層之該第一表面之上；電子組件，其在該第一互連層之上且電連接至該第一互連層；複數個電導體，其在該非半導電電介質中介層之該第二表面之上；複數個導電結構，其穿過該非半導電電介質中介層，且電連接至該第一互連層及該等電導體；及封裝基板，其在該複數個電導體之上且電連接至該複數個電導體。 根據本發明之一實施例，一種製造半導體元件之方法包含：將電介質層沈積於第一載體基板之上；在該電介質層之第一表面之上形成第一互連層；將電子組件安置在該第一互連層之上；將該電子組件接合至第二載體基板並自該電介質層釋放該第一載體基板；形成穿過該電介質層且電連接至該第一互連層之複數個導電結構；及在該電介質層之第二表面之上形成電連接至該複數個導電結構之複數個電導體。
以下揭示內容提供用於實施所提供之標之物之不同特徵件之許多不同實施例或實例。下文描述元件及配置之具體實例以簡化本揭示。當然，此等具體實例僅係實例，且不希望具限制性。舉例而言，在以下描述中在第二特徵件之上或上形成第一特徵件可包括其中第一及第二特徵件經形成直接接觸之實施例，且還可包括其中額外特徵件可經形成於第一與第二特徵件之間使得第一與第二特徵件可能並不直接接觸之實施例。另外，在各種實例中，本揭示可重複元件符號及/或字母。此重複係為了簡化及清楚之目的且其本身並不指示所論述之各種實施例及/或組態之間的關係。 此外，為了便於描述，本文可使用空間相對術語，例如「在…下方」、「在…下面」、「下」、「在…上面」、「上部」、「上」及類似物來描述如圖中所說明之一個元件或特徵件與另一(另外)元件或特徵件之關係。空間相對術語希望涵蓋元件在使用或操作中除圖中所描繪之定向之外的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文使用之空間相對描述符可同樣地因此而解譯。 如本文所使用，術語例如「第一」、「第二」及「第三」描述各種元件、組件、區域、層及/或區段，此等元件、組件、區域、層及/或區段不應受此等術語限制。此等術語僅可用於區別一個元件、組件、區域、層或區段與另一元件、組件、區域、層或區段。術語例如「第一」、「第二」及「第三」在用於本文中時不暗含順序或次序，除非上下文明確指示。 如本文所使用，術語「大約」、「基本上」、「基本」及「約」用於描述及解釋小變化。當連同事件或情況一起使用時，術語可指代其中事件或情況恰恰發生之例子以及其中事件或情況近似接近地發生之例子。舉例而言，當連同數值一起使用時，術語可指代小於或等於該數值之±10%之變化範圍，例如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%。舉例而言，若兩個數值之間的差值小於或等於該值之平均值之±10%，例如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%，則可認為兩個數值「基本上」相同或相等。舉例而言，「基本上」平行可指代相對於0°之小於或等於±10°之角度變化範圍，例如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°或小於或等於±0.05°。舉例而言，「基本上」垂直可指代相對於90°之小於或等於±10°之角度變化範圍，例如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°或小於或等於±0.05°。 還可包括其他特徵或過程。舉例而言，可包括測試結構以協助3D封裝或3DIC元件之驗證測試。測試結構可包括(例如)形成於重新分佈層中或基板上之測試墊，該基板允許測試3D封裝或3DIC、使用探針及/或探針板及類似物。可對中間結構以及最終結構執行驗證測試。另外，本文揭示之結構及方法可連同併入已知良好晶粒之中間驗證來增加良率並降低成本之測試方法學一起使用。 在本發明之一或多個實施例中，包括非半導電電介質中介層之半導體元件用於互連安置在其兩個相對表面之上的兩個或兩個以上電子組件。非半導電電介質中介層具有低介電常數，這幫助減輕電流洩漏及RC延遲。具有低介電常數，則非半導電電介質中介層之厚度可減小，且不會在安置在非半導電電介質中介層之兩個相對側上之電子組件之間引起干擾，且因此，半導體元件之整體體積可減小。 圖1為說明根據本發明之一或多個實施例之各種態樣的製造半導體元件的方法之流程圖。方法100以操作110開始，其中將電介質層沈積在第一載體基板之上。方法100繼續進行操作120，其中在電介質層之第一表面之上形成第一互連層。方法100繼續進行操作130，其中在第一互連層之上安置電子組件。方法100繼續進行操作140，其中將電子組件接合至第二載體基板，且自電介質層釋放第一載體基板。方法100繼續進行操作150，其中形成穿過電介質層且電連接至第一互連層之複數個導電結構。方法100繼續進行操作160，其中在電介質層之第二表面之上形成電連接至複數個導電結構之複數個電導體。 方法100僅係實例，且不希望將本揭示限制在申請專利範圍中明確陳述之內容之外。可在方法100之前、期間及之後提供額外操作，且針對方法之額外實施例，可替換、取消或移動所描述之一些操作。 圖2A、圖2B、圖2C、圖2D、圖2E、圖2F及圖2G為根據本發明之一或多個實施例的製造半導體元件之各種操作中的一個操作處之示意圖。如圖2A中所描繪，電介質層20經沈積於第一載體基板10之上。第一載體基板10經組態為用於形成電介質層20及其他結構層之臨時載體基板，且隨後將被移除。在一些實施例中，第一載體基板10可包括(但不限於)毯覆式晶圓。電介質層20包括第一表面201及與第一表面201相對之第二表面202。在一些實施例中，電介質層20由非半導電材料製成。在一些實施例中，電介質層20經組態為加固層，以增強半導體元件之穩健性。在一些實施例中，電介質層20經組態為非半導電電介質中介層，其可替換例如矽中介層之半導體中介層。在一些實施例中，電介質層20之介電常數小於例如矽中介層之半導體中介層之介電常數。在一些實施例中，電介質層20之介電常數在自約1至約10之範圍內。作為實例，電介質層20之介電常數在自約3至約8之範圍內，在自約3至約7之範圍內，在自約3至約6之範圍內，在自約3至約5之範圍內或在自約3至約4之範圍內。在一些實施例中，電介質層20之彈性模量不同於例如矽中介層之半導體中介層之彈性模量。作為實例，電介質層20之彈性模量大於例如矽中介層之半導體中介層之彈性模量。在一些實施例中，電介質層20之厚度小於例如矽中介層之半導體中介層之厚度，半導體中介層之厚度大於50微米。作為實例，電介質層20之厚度在自約5微米至約30微米之範圍內，在自約10微米至約25微米之範圍內，在自約10微米至約20微米之範圍內或在自約10微米至約15微米之範圍內。在一些實施例中，電介質層20可例如藉由化學氣相沈積(CVD)、實體氣相沈積(PVD)、旋塗、施配或其他合適之操作形成於第一載體基板10之上。在一些實施例中，電介質層20包括無機電介質材料，例如氧化矽、氮化矽、氮氧化矽、其組合或其他合適之無機電介質材料。在一些實施例中，電介質層20包括有機電介質材料，例如聚醯亞胺、聚甲基丙烯酸甲酯(PMMA)、聚苯并噁唑(PBO)、其組合或其他合適之有機電介質材料。在一些實施例中，電介質層20為單層電介質層，其可包括上述無機電介質材料或有機電介質材料。 如圖2B中所描繪，第一互連層30形成於電介質層20之第一表面201之上。在一些實施例中，第一互連層30可包括一或多個重新分佈層(RDL)、一或多個路由層或類似物。在一些實施例中，第一互連層30可包括絕緣層31、32及穿過絕緣層31、32之導電層33。 如圖2C中所描繪，電子組件40經安置於第一互連層30之上且電連接至第一互連層30。在一些實施例中，電子組件40可包括一或多個半導體晶粒、一或多個半導體封裝或其他主動或被動電子組件。在一些實施例中，電子組件40使用電連接器42 (例如導電凸塊、導電膏、導電球或類似物)電連接至第一互連層30。在一些實施例中，底料填充層44可經插入於電子組件40與第一互連層30之間且環繞電連接器42。在一些實施例中，囊封劑46 (例如模製化合物)可形成於第一互連層30之上以圍封電子組件40之一部分。在一些實施例中，囊封劑46可圍封電子組件40之一部分，例如電子組件40之邊緣。在一些實施例中，囊封劑46可進一步圍封電子組件40之上表面。 如圖2D中所描繪，電子組件40接合至第二載體基板12。在一些實施例中，第二載體基板12經組態為臨時載體基板，其用於支撐電介質層20、第一互連層30及電子組件40使得其他層或組件可形成於電介質層20之第二表面202之上。在一些實施例中，第二載體基板12可包括(但不限於)毯覆式晶圓。在一些實施例中，電子組件40使用黏著層14接合至第二載體基板12。在將電子組件40接合至第二載體基板12之後，可自電介質層20之第一表面201釋放第一載體基板10。 如圖2E中所描繪，形成穿過電介質層20且電連接至第一互連層30之複數個導電結構50。在一些實施例中，鈍化層52可形成於電介質層20之第二表面202之上，且導電結構50可進一步穿透鈍化層52。在一些實施例中，導電結構50之厚度基本上等於電介質層20之厚度。在一些實施例中，導電結構之厚度在自約5微米至約30微米之範圍內。 如圖2F中所描繪，複數個電導體60形成於電介質層20之第二表面202之上且分別電連接至導電結構50。在一些實施例中，複數個接合墊62可分別形成於電導體60與導電結構50之間。在一些實施例中，接合墊62可(但不限於)由掩模層64 (例如焊料掩模)界定。在一些實施例中，電導體60可包括堆疊至彼此之第一導電材料601及第二導電材料602。作為實例，第一導電材料601可包括銅，且第二導電材料602可包括錫。 如圖2G中所描繪，第二載體基板12自電子組件40釋放以形成本發明之一些實施例之半導體元件1。 在本發明之一些實施例中，半導體元件1使用電介質層20作為電介質中介層以互連第一表面201之上之電子組件40及第二表面202之上之電導體60。與半導體中介層相比，電介質中介層可包括以下優點。電介質中介層具有低成本。電介質中介層更薄，這使互連距離變短以改良電效能。電介質中介層具有低介電常數，這幫助減輕安置於中介層之兩個相對表面上之電子組件之間的電流洩漏及RC延遲。具有低介電常數，電介質中介層之厚度可減小，而不會在安置在中介層之兩個相對表面上之電子組件之間引起干擾，且因此，半導體元件1之整體體積可減小。電介質中介層比半導體中介層更靈活，且因此可幫助釋放應力且減小分層風險。 圖3為根據本發明之一或多個實施例的半導體元件之示意圖。如圖3中所描繪，與圖2G之半導體元件1相比，半導體元件1'之電介質層20可包括多層電介質層，其可包括堆疊在彼此上之兩個或兩個以上電介質膜21及22。多層電介質層之膜21及22中之每一者可個別地包括無機電介質材料或有機電介質材料。作為實例，電介質膜21可包括無機電介質材料，例如氧化矽、氮化矽、氮氧化矽、其組合或其他合適之無機電介質材料。其他電介質膜22可包括有機電介質材料，例如聚醯亞胺、聚甲基丙烯酸甲酯(PMMA)、聚苯并噁唑(PBO)、其組合或其他合適之有機電介質材料。在一些實施例中，電介質膜21可包括有機電介質材料，而電介質膜22可包括無機電介質材料。在一些實施例中，多層電介質層20之介電常數小於例如矽中介層之半導體中介層之介電常數。在一些實施例中，電介質層20之介電常數在自約1至約10之範圍內。作為實例，多層電介質層20之介電常數在自約3至約8之範圍內，在自約3至約7之範圍內，在自約3至約6之範圍內，在自約3至約5之範圍內或在自約3至約4之範圍內。在一些實施例中，多層電介質層20之彈性模量不同於例如矽中介層之半導體中介層之彈性模量。作為實例，電介質層20之彈性模量大於例如矽中介層之半導體中介層之彈性模量。在一些實施例中，多層電介質層20之厚度小於例如矽中介層之半導體中介層之厚度，半導體中介層之厚度大於50微米。作為實例，電介質層20之厚度在自約5微米至約30微米之範圍內，在自約10微米至約25微米之範圍內，在自約10微米至約20微米之範圍內，或在自約10微米至約15微米之範圍內。 在本發明之一些實施例中，半導體元件1'使用多層電介質層20作為電介質中介層以互連第一表面201之上之電子組件40與第二表面202之上之電導體60。與半導體中介層相比，電介質中介層可包括以下優點。電介質中介層具有低成本。電介質中介層更薄，這使互連距離變短以改良電效能。電介質中介層具有低介電常數，這幫助減輕安置於中介層之兩個相對表面上之電子組件之間的電流洩漏及RC延遲。具有低介電常數，電介質中介層之厚度可減小，而不會在安置在中介層之兩個相對表面上之電子組件之間引起干擾，且因此，半導體元件1'之整體體積可減小。電介質中介層比半導體中介層更靈活，且因此可幫助釋放應力且減小分層風險。多層電介質層20可進一步經組態以補償鄰近結構層之間的非匹配(例如CTE非匹配或應力非匹配)，且因此可緩和翹曲問題。 本揭示之半導體元件及其製造方法不限於上文提及之實施例，且可具有其他不同實施例。為簡化描述，且為便於在本發明之實施例中之每一者之間作比較，使用相同元件符號標記以下實施例中之每一者中之相同組件。為了使其更容易比較實施例之間的差異，以下描述將詳細描述不同實施例之中的相異點，且將不再冗餘地描述相同特徵。 圖4為根據本發明之一或多個實施例的半導體元件之示意圖。如圖4中所描繪，與圖2G之半導體元件1相比，半導體元件2可包括基板上晶圓上晶片(COWOS)封裝結構，其可進一步包括電導體60之上之且電連接至電導體60之封裝基板70。在一些實施例中，電路可形成於封裝基板70中。在一些實施例中，半導體元件2可進一步包括封裝基板70之上之且電連接至封裝基板70之且與電導體60相對之複數個第二電導體72。第二電導體72可藉由封裝基板70、電導體60、導電結構50及第一互連層30電連接至電子組件40。在一些實施例中，第二電導體72經組態以將電子組件40電連接至另一電子組件(例如印刷電路板(PCB))。在一些實施例中，第二電導體72可包括(但不限於)導電凸塊、導電膏、導電球或類似物。在一些實施例中，電介質層20可為如圖2A至圖2G中描述之單層電介質層。在一些實施例中，電介質層20可為如圖3中描述之多層電介質層。 在本發明之一些實施例中，半導體元件2使用電介質層20作為電介質中介層以互連第一表面201之上之電子組件40與第二表面202之上之電導體60。與半導體中介層相比，電介質中介層可包括以下優點。電介質中介層具有低成本。電介質中介層更薄，這使互連距離變短以改良電效能。電介質中介層具有低介電常數，這幫助減輕安置於中介層之兩個相對表面上之電子組件之間的電流洩漏及RC延遲。具有低介電常數，則電介質中介層之厚度可減小，且不會在安置在中介層之兩個相對表面上之電子組件之間引起干擾，且因此，半導體元件2之整體體積可減小。電介質中介層比半導體中介層更靈活，且因此可幫助釋放應力且減小分層風險。 圖5為說明根據本發明之一或多個實施例之各種態樣的製造半導體元件的方法之流程圖。方法200以操作110開始，其中將電介質層沈積在第一載體基板之上。方法繼續進行操作120，其中在電介質層之第一表面之上形成第一互連層。方法繼續進行操作130，其中在第一互連層之上安置電子組件。方法繼續進行操作140，其中將電子組件接合至第二載體基板，且自電介質層釋放第一載體基板。方法繼續進行操作150，其中形成穿過電介質層且電連接至第一互連層之複數個導電結構。方法繼續操作155，其中在電介質層之第二表面之上形成第二互連層。方法繼續進行操作160，其中在電介質層之第二表面之上形成電連接至複數個導電結構之複數個電導體。 方法200僅係實例，且不希望將本揭示限制在申請專利範圍中明確陳述之內容之外。可在方法200之前、期間及之後提供額外操作，且針對方法之額外實施例，可替換、取消或移動所描述之一些操作。 圖6A、圖6B及圖6C為根據本發明之一或多個實施例的製造半導體元件之各種操作中之一個操作處之示意圖。在一些實施例中，可在圖2E之後實施圖6A、圖6B及圖6C之半導體元件之製造。如圖6A中所描繪，第二互連層80形成於電介質層20之第二表面202之上且電連接至導電結構50。在電導體60形成之前形成第二互連層80。在一些實施例中，第二互連層80可包括一或多個重新分佈層(RDL)、一或多個路由層或類似物。在一些實施例中，第二互連層80可包括一或多個絕緣層81及穿過絕緣層81之一或多個導電層82。 如圖6B中所描繪，在一些實施例中，另一鈍化層84可形成於第二互連層80之上。在一些實施例中，鈍化層84暴露第二互連層80之一部分。複數個電導體60形成於第二互連層80之上且藉由第二互連層80電連接至導電結構50。在一些實施例中，複數個接合墊62可形成於電導體60與第二互連層80之間。在一些實施例中，接合墊62可(但不限於)由掩模層64 (例如焊料掩模)界定。在一些實施例中，電導體60可包括堆疊至彼此之第一導電材料601及第二導電材料602。作為實例，第一導電材料601可包括銅，且第二導電材料602可包括錫。 如圖6C中所描繪，第二載體基板12自電子組件40釋放以形成本發明之一些實施例之半導體元件3。 在本發明之一些實施例中，半導體元件3使用電介質層20作為電介質中介層以互連第一表面201之上之電子組件40與第二表面202之上之電導體60。與半導體中介層相比，電介質中介層可包括以下優點。電介質中介層具有低成本。電介質中介層更薄，這使互連距離變短以改良電效能。電介質中介層具有低介電常數，這幫助減輕安置於中介層之兩個相對表面上之電子組件之間的電流洩漏及RC延遲。具有低介電常數，則電介質中介層之厚度可減小，且不會在安置在中介層之兩個相對表面上之電子組件之間引起干擾，且因此，半導體元件3之整體體積可減小。電介質中介層比半導體中介層更靈活，且因此可幫助釋放應力且減小分層風險。在一些實施例中，第二互連層80可經組態以重新分佈電路佈局。在一些實施例中，電介質層20可為如圖2A至圖2G中描述之單層電介質層。在一些實施例中，電介質層20可為如圖3中描述之多層電介質層。 圖7為根據本發明之一或多個實施例的半導體元件之示意圖。如圖7中所描繪，與圖6C之半導體元件3相比，半導體元件4可包括基板上晶圓上晶片(COWOS)封裝結構，其可進一步包括電導體60之上之且電連接至電導體60之封裝基板70。在一些實施例中，電路可形成於封裝基板70中。在一些實施例中，半導體元件4可進一步包括封裝基板70之上之且電連接至封裝基板70之且與電導體60相對之多個第二電導體72。第二電導體72可藉由封裝基板70、電導體60、導電結構50及第一互連層30電連接至電子組件40。在一些實施例中，第二電導體72經組態以將電子組件40電連接至另一電子組件(例如印刷電路板(PCB))。在一些實施例中，第二電導體72可包括(但不限於)導電凸塊、導電膏、導電球或類似物。在一些實施例中，電介質層20可為如圖2A至圖2G中描述之單層電介質層。在一些實施例中，電介質層20可為如圖3中描述之多層電介質層。 在本發明之一些實施例中，半導體元件4使用電介質層20作為電介質中介層以互連第一表面201之上之電子組件40與第二表面202之上之電導體60。與半導體中介層相比，電介質中介層可包括以下優點。電介質中介層具有低成本。電介質中介層更薄，這使互連距離變短以改良電效能。電介質中介層具有低介電常數，這幫助減輕安置於中介層之兩個相對表面上之電子組件之間的電流洩漏及RC延遲。具有低介電常數，電介質中介層之厚度可減小，而不會在安置在中介層之兩個相對表面上之電子組件之間引起干擾，且因此，半導體元件4之整體體積可減小。電介質中介層比半導體中介層更靈活，且因此可幫助釋放應力且減小分層風險。在一些實施例中，第二互連層80可經組態以重新分佈電路佈局，且自第二電導體72釋放應力。 在本發明之一或多個實施例中，非半導電電介質中介層用於互連安置在其兩個相對表面之上之兩個或兩個以上電子組件。與半導體中介層相比，非半導電電介質中介層具有低介電常數，這幫助減輕電流洩漏及RC延遲。具有低介電常數，非半導電電介質中介層之厚度可減小，而不會在安置在非半導電電介質中介層之兩個相對側上之電子組件之間引起干擾，且因此，半導體元件之整體體積可減小。在本發明之一些實施例中，非半導電電介質中介層比半導體中介層更靈活，且因此幫助減小分層風險。在本發明之一些實施例中，非半導電電介質中介層可為多層之，其可經組態以補償鄰近結構層之間的非匹配(例如CTE非匹配或應力非匹配)，且因此可緩和翹曲問題。 在一個示例性態樣中，半導體元件包括電介質中介層、第一互連層、電子組件、複數個電導體及複數個導電結構。該電介質中介層具有第一表面及與該第一表面相對之第二表面。該第一互連層在該電介質中介層之該第一表面之上。該電子組件在該第一互連層之上且電連接至該第一互連層。該等電導體在該電介質中介層之該第二表面之上。該等導電結構穿過該電介質中介層，其中該等導電結構電連接至該第一互連層及該等電導體。 在另一態樣中，半導體元件包括非半導電電介質中介層、第一互連層、電子組件、複數個電導體、複數個導電結構及封裝基板。該非半導電電介質中介層具有第一表面及與該第一表面相對之第二表面。該第一互連層在該非半導電電介質中介層之該第一表面之上。該電子組件在該第一互連層之上且電連接至該第一互連層。該等電導體在該非半導電電介質中介層之該第二表面之上。該等導電結構穿過該電介質中介層，且電連接至該第一互連層及該等電導體。該封裝基板在該複數個電導體之上且電連接至該複數個電導體。 在又另一態樣中，一種製造半導體元件之方法包括：將電介質層沈積於第一載體基板之上；在該電介質層之第一表面之上形成第一互連層；將電子組件安置在該第一互連層之上；將該電子組件接合至第二載體基板並自該電介質層釋放該第一載體基板；形成穿過該電介質層且電連接該第一互連層之複數個導電結構；及在該電介質層之第二表面之上形成電連接至該複數個導電結構之複數個電導體。 前述內容概述若干實施例之結構使得熟習此項技術者可更佳地理解本揭示之態樣。熟習此項技術者應瞭解，他們可容易地使用本揭示作為設計或修改用於實施本文引入之實施例之相同目的之間的及/或實現本文引入之實施例之相同優點之其他過程及結構之基礎。熟習此項技術者還應意識到，此類等效構造不背離本揭示之精神及範疇，且他們可在不背離本揭示之精神及範疇之情況下在本文中做出各種變化、替代、及更改。
1‧‧‧半導體元件
1'‧‧‧半導體元件
2‧‧‧半導體元件
3‧‧‧半導體元件
4‧‧‧半導體元件
10‧‧‧第一載體基板
12‧‧‧第二載體基板
14‧‧‧黏著層
20‧‧‧電介質層
21‧‧‧電介質膜
22‧‧‧電介質膜
30‧‧‧第一互連層
31‧‧‧絕緣層
32‧‧‧絕緣層
33‧‧‧導電層
40‧‧‧電子組件
42‧‧‧電連接器
44‧‧‧底料填充層
46‧‧‧囊封劑
50‧‧‧導電結構
52‧‧‧鈍化層
60‧‧‧導電體
62‧‧‧接合墊
64‧‧‧掩模層
70‧‧‧封裝基板
72‧‧‧第二電導體
80‧‧‧第二互連層
81‧‧‧絕緣層
82‧‧‧導電層
84‧‧‧鈍化層
100‧‧‧方法
110‧‧‧操作
120‧‧‧操作
130‧‧‧操作
140‧‧‧操作
150‧‧‧操作
155‧‧‧操作
160‧‧‧操作
200‧‧‧方法
201‧‧‧第一表面
202‧‧‧第二表面
601‧‧‧第一導電材料
602‧‧‧第二導電材料
當結合附圖閱讀時，自以下詳細描述更佳地理解本發明之實施例之態樣。應注意，根據工業中之標準實踐，各種結構並非按比例繪製。事實上，為了清楚地論述，可任意增大或減小各種結構之尺寸。 圖1為說明根據本發明之一或多個實施例之各種態樣的製造半導體元件的方法之流程圖。 圖2A、圖2B、圖2C、圖2D、圖2E、圖2F及圖2G為根據本發明之一或多個實施例的製造半導體元件之各種操作中的一個操作處之示意圖。 圖3為根據本發明之一或多個實施例的半導體元件之示意圖。 圖4為根據本發明之一或多個實施例的半導體元件之示意圖。 圖5為說明根據本發明之一或多個實施例之各種態樣的製造半導體元件的方法之流程圖。 圖6A、圖6B及圖6C為根據本發明之一或多個實施例的製造半導體元件之各種操作中的一個操作處之示意圖。 圖7為根據本發明之一或多個實施例的半導體元件之示意圖。

Claims (1)

  1. 一種半導體結構，其包含： 一電介質中介層，其具有一第一表面及與該第一表面相對之一第二表面； 一第一互連層，其在該電介質中介層之該第一表面之上； 一電子組件，其在該第一互連層之上且電連接至該第一互連層； 複數個電導體，其在該電介質中介層之該第二表面之上；及 複數個導電結構，其穿過該電介質中介層，其中該等導電結構電連接至該第一互連層及該等電導體。
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