TWI493679B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI493679B
TWI493679B TW101116308A TW101116308A TWI493679B TW I493679 B TWI493679 B TW I493679B TW 101116308 A TW101116308 A TW 101116308A TW 101116308 A TW101116308 A TW 101116308A TW I493679 B TWI493679 B TW I493679B
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substrate
forming material
stress
compensation layer
wafer
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TW201330215A (zh
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Chun Hung Lin
Yu Feng Chen
Han Ping Pu
Hung Jui Kuo
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Taiwan Semiconductor Mfg Co Ltd
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Description

半導體裝置及其製造方法
本發明係有關於一種半導體技術，特別是有關於一種半導體裝置及其製造方法。
自積體電路的發明創造以來，由於各個電子部件(即，電晶體、二極體、電阻、電容等等)的集積度(integration density)持續的改進，使半導體業持續不斷的快速成長發展。主要來說，集積度的改進來自於最小特徵尺寸(minimum feature size)不斷縮小而容許更多的部件整合至既有的晶片面積內。
這些集積度的改進實質上是朝二維(two-dimensional,2D)方面的，因為積體部件所佔的體積實際上位於半導體晶圓的表面。儘管微影(lithography)技術的精進為2D積體電路製作帶來相當大的助益，二維空間所能擁有的密度還是有其物理限制。這些限制之一在於製作這些部件所需的最小尺寸。再者，當更多的裝置放入一晶片中，需具有更複雜的電路設計。
為了進一步增加積體電路密度，已開始研究三維(3D)積體電路(three-dimensional integrated circuit,3DIC)。在典型的3DIC製程中，二個晶片彼此接合，且在每一晶片與基底上的接觸墊之間形成電性連接。例如，在彼此上方接合二個晶片。疊置的晶片接著與一承載基底(carrier substrate)接合，而接線將每一晶片上的接觸墊電性耦接至承載基底上的接觸墊。
另一種3D封裝使用了疊層封裝(packaging-on-packaging,PoP)或轉接板(interposer)技術來疊置晶片，以降低形狀因素(form factor)。PoP通常包括一電性耦接至矽轉接板的第一晶片以及放置於第一晶片上方並與矽轉接板電性耦接的另一封裝後的晶片。矽轉接板接著電性耦接至另一基板，例如一印刷電路板(printed circuit board,PCB)。
在本發明一實施例中，一種半導體裝置，包括：一第一基底，具有一第一側及一第二側；一第一晶片，裝設於第一基底的第一側上；一成形材料，形成於第一基底的第一側的至少一部分上；一應力補償層，形成於第一基底的第二側上；以及一第二基底，電性耦接至第一基底，且位於第一側上。
在本發明另一實施例中，一種半導體裝置，包括：一封裝體，包括一第一積體電路晶片；一第一基底，具有一第一導電特徵部件組，其位於第一基底的一第一側上，且具有一第二導電特徵部件組，其位於第一基底的一第二側上，封裝體耦接至位於第一基底的第一側上的第一導電特徵部件組中一第一次組；一第二積體電路晶片，電性耦接至位於第一基底的第一側上的第一導電特徵部件組中一第二次組；一成形材料，至少局部封裝第二積體電路晶片；以及一應力補償層，順沿著第一基底的第二側，應力補償層內具有複數個開口，以至少局部露出位於第一基底的第二側上所對應的第二導電特徵部件組，當成形材料施加一應力時，應力補償層施加一反方向的力。
在本發明又另一實施例中，一種半導體裝置之製造方法，包括：提供一第一基底，其具有一第一側及相對的一第二側；將一第一晶片貼合至於第一基底的第一側；在第一基底的第一側上形成一成形材料；以及在第一基底的第二側上形成一應力補償層。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
請參照第1圖，其繪示出根據本發明一實施例之基底108與基底104剖面示意圖。在一實施例中，基底108為封裝體100的一部件，可包括一積體電路晶片106，其透過一導電連接器110而裝設於基底108上。導電連接器110可包括無鉛焊料、共晶鉛、導電柱體(pillar)及/或其組合等等。
基底108可為封裝基底、印刷電路板(PCB)或高密度多層線路板(high-density interconnect)等等。通孔電極(through via,TV)(未繪示)可用於積體電路晶片106與位於基底108的背側表面的一導電特徵部件組112之間的電性連接。基底108可包括重佈局線(redistribution line,RDL)，其位於基底108的一表面或二表面的內部及/或上方，以提供不同的引腳(pin)配置，也提供較大的電性連接。一封膠體(encapsulant)114或壓模成型材料(overmold)可形成於上述部件上，以保護上述部件不受到環境或外界汙染。
在一實施例中，基底104可具有一積體電路晶片102裝設於上。以下有更詳細的說明。封裝體100將電性耦接至基底104，以構成疊層封裝(POP)。
基底104更包括一導電特徵部件組116，其與積體電路晶片102位於基底104的相同表面上，且一導電特徵部件組118與積體電路晶片102位於基底104的相對表面上。在本實施例中，基底104提供積體電路晶片106與積體電路晶片102之間的電性連接，及/或透過後續形成的導電連接器組(如第5圖所示)來提供基底104的導電特徵部件組118與積體電路晶片106及積體電路晶片102中之一者或兩者之間的電性連接。基底104內的通孔電極(TV)提供導電特徵部件組116與導電特徵部件組118之間的電性連接。基底104也可包括重佈局線(RDL)(未繪示)，其位於基底104的一表面或二表面的內部及/或上方，以提供不同的引腳配置，也提供較大的電性連接。在一實施例中，基底104可為任何適合的基底，例如矽基底、有機基底、陶瓷基底、介電基底或層壓(laminate)基底等等。
如第1圖所示，積體電路晶片102透過一導電連接器120而電性耦接至位於基底104上的第二導電特徵部件組中某些導電特徵部件。導電連接器120可包括無鉛焊料、共晶鉛、導電柱體及/或其組合等等。
積體電路晶片102及積體電路晶片106可為用於特定應中任何適合的積體電路晶片。舉例而言，積體電路晶片102及積體電路晶片106其中一者可為記憶體晶片，例如DRAM、SRAM及/或NVRAM等等，而另一者可為邏輯電路。
請參照第2圖，其繪示出塗覆於基底104上的成形材料230。在一實施例中，成形材料230為模塑底膠填充物(molding underfill)，其包括高分子及/或環氧化物等等。成形材料230可與積體電路晶片102的上表面及邊緣接觸。成形材料230可使用壓縮模塑或傳遞模塑而形成於積體電路晶片102及基底104上。第2圖所示的實施例中成形材料230的上表面與積體電路晶片102的上表面為共平面。在其他實施例中，成形材料230的上表面可高於積體電路晶片102的上表面，使積體電路晶片102完全封裝於成形材料230內。可選擇性地進行一研磨製程，以自積體電路晶片102的上表面去除局部的成形材料230而露出積體電路晶片102。
第3圖係繪示出在成形材料230內形成開口332。可透過鑽孔或蝕刻等等，以形成開口332，且可露出位於基底104上的導電特徵部件組116中對應的導電特徵部件。以下有更詳的說明。開口332將用於提供基底108上的導電特徵部件組112與基底104上的導電特徵部件組116中對應的導電特徵部件之間的電性連接。
第4圖係繪示出根據一實施例之在基底104中相對於成形材料230的一表面上形成應力補償層434。可發現到當基底104及成形材料230的溫度改變時，各個膜層會因為用於形成各個結構的不同材料之間的熱膨脹係數(coefficient of thermal expansion,CTE)差異而有不同膨脹及/或收縮速率。舉例而言，在一實施例中，基底104包括一矽轉接板，當溫度從170℃降至25℃(約為室溫)時，成形材料230收縮速率快於矽轉接板。由於CTE之間的差異，收縮速率造成成形材料230對基底104施加一應力，而在某些狀態下會造成基底104彎曲變形。此彎曲變形又再造成基底104與其他基底(例如，基底108及/或耦接至基底104的其他基底)之間的電性連接器(例如，焊球)內產生應力。在這些情形下，相信在沿著基底104中相對於成形材料230的一表面上形成應力補償層434可抵消成形材料230所施加的應力，藉以減少彎曲變形以及電性連接器上的應力。
在一實施例中，基底104包括一矽轉接板，應力補償層434可包括液態成形材料(例如，住友(Sumitomo)G350S)及/或聚醯亞胺(polyimide,PI)(例如，HD Microsystems所供應的HD-8820聚對苯撐苯並二噁唑(phenylenebenzobisoxazole PBO)以及JSR公司所供應的WPR-5105)等等。可調整應力補償層434的厚度，以施加適當的應力抵消量。在一實施例中，應力補償層434的厚度由以下的方程式所決定：
其中：CTEMolding 為成形材料230的熱膨脹係數；EMolding 為成形材料230的楊氏係數；THKMolding 為成形材料230的厚度；CTECompensation 為應力補償層434的熱膨脹係數；ECompensation 為該應力補償層434的楊氏係數；以及THKLMC 為應力補償層434的厚度。
一第二組開口436可形成於應力補償層434內，以露出導電特徵部件組118中對應的導電特徵部件。第二組開口436可透過鑽孔或蝕刻等等而形成。以下將有更詳細的說明。第二組開口436將用以提供位於基底104上導電特徵部件組116與一第三基底(如第5圖所示)的導電特徵部件中對應的導電特徵部件之間電性連接。
第5圖係繪示出根據本發明一實施例之在將封裝體100耦接至基底104以及將基底104耦接至一基底550之後的一實施例。在一實施例中，可分別利用導電部件552及554，將封裝體100耦接至基底104，且將基底104耦接至一基底550。導電部件552及554可由共晶焊料或無鉛焊料等等所構成。在其他實施例中，導電部件552及554可包括具有或不具有焊料或焊料類型材料的導電柱體。基底108、基底104及/或基底550可包括一凸塊方金屬(under bump metallization,UBM)層，以提供導電特徵部件適當的接觸區域。在一實施例中，位於基底108上的導電特徵部件組112及位於基底104上的第二及第三導電特徵部件組116及118可排列成一球柵陣列(ball grid array,BGA)。
基底550可為任何適合的基底，其上可貼附基底104。舉例而言，基底550可為印刷電路板(PCB)、高密度多層線路板、矽基底、有機基底、陶瓷基底、介電基底或層壓基底等等。
在第5圖的實施例中基底108與成形材料230之間以及應力補償層434與基底550之間具有空隙。在其他實施例中，這些空隙可填入底膠材料，以提供額外的保護來對抗環境因素。
可以理解的是上述說明提供一般實施例，而上述實施例可包括許多的其他特徵部件。舉例而言，上述實施例可包括凸塊下方金屬層、鈍化護層、成形材料、額外的晶片及/或基底等等。另外，上述積體電路晶片106與積體電路晶片102的結構、放置及位置僅僅用於說明之目的，因此在其他實施例中，可採用不同的結構、放置及位置。
可以理解的是上述的各個步驟順序僅僅用於說明之目的，因此在其他實施例中，可採用不同的步驟順序。舉例而言，應力補償層434可形成步驟可在將積體電路晶片102耦接至基底104之前或之後及/或在將基底108耦接基底104之前或之後進行。這些步驟順序也包括於上述實施例的範圍中。
在一實施例中，提供一種半導體裝置。半導體裝置包括：一第一基底，具有一第一側及一第二側；一第一晶片，裝設於第一基底的第一側上；一成形材料，形成於第一基底的第一側的至少一部分上；一應力補償層，形成於第一基底的第二側上；以及一第二基底，電性耦接至第一基底，且位於第一側上。
在另一實施例中，提供一種半導體裝置。半導體裝置包括：一封裝體，包括一第一積體電路晶片；以及一第一基底，具有一第一導電特徵部件組，其位於第一基底的一第一側上，且具有一第二導電特徵部件組，其位於第一基底的一第二側上。封裝體耦接至位於第一基底的第一側上的第一導電特徵部件組中一第一次組。半導體裝置更包括：一第二積體電路晶片，其電性耦接至位於第一基底的第一側上的第一導電特徵部件組中一第二次組；一成形材料，至少局部封裝第二積體電路晶片；以及一應力補償層，順沿著第一基底的第二側，應力補償層內具有複數個開口，以至少局部露出位於第一基底的第二側上所對應的第二導電特徵部件組，當成形材料施加一應力時，應力補償層施加一反方向的力。
又在另一實施例中，提供一種半導體裝置之製造方法，其包括：提供一第一基底，其具有一第一側及相對的一第二側；將一第一晶片貼合至於第一基底的第一側；在第一基底的第一側上形成一成形材料；以及在第一基底的第二側上形成一應力補償層。
雖然本發明之實施例及其優點已揭露如上，然其在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。
再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
100．．．封裝體
102．．．積體電路晶片
104．．．基底
106．．．積體電路晶片
108．．．基底
110．．．導電連接器
112．．．導電特徵部件組
114．．．封膠體
116．．．導電特徵部件組
118．．．導電特徵部件組
120．．．導電連接器
230．．．成形材料
332．．．開口
434．．．應力補償層
436．．．開口
552、554．．．導電部件
550．．．基底
第1至5圖係繪示出根據本發明一實施例之半導體裝置之製造方法剖面示意圖。
100．．．封裝體
102、106．．．積體電路晶片
104、108．．．基底
110、120．．．導電連接器
112、116、118．．．導電特徵部件組
114．．．封膠體
230．．．成形材料
434．．．應力補償層
552、554．．．導電部件
550．．．基底

Claims (7)

  1. 一種半導體裝置，包括：一第一基底，具有一第一側及一第二側；一第一晶片，裝設於該第一基底的該第一側上；一成形材料，形成於該第一基底的該第一側的至少一部分上；一應力補償層，形成於該第一基底的該第二側上， 其中該應力補償層的厚度為，其中 CTEMolding 為該成形材料的熱膨脹係數，EMolding 為該成形材料的楊氏係數，THKMolding 為該成形材料的厚度，CTECompensation 為該應力補償層的熱膨脹係數，ECompensation 為該應力補償層的楊氏係數；以及一第二基底，電性耦接至該第一基底，且位於該第一側上。
  2. 如申請專利範圍第1項所述之半導體裝置，更包括一晶片封裝體，位於該第一晶片上，且電性耦接至該第一基底，該晶片封裝體包括該第二基底及一第二晶片。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該應力補償層包括一成形材料。
  4. 一種半導體裝置，包括：一封裝體，包括一第一積體電路晶片；一第一基底，具有一第一導電特徵部件組，其位於該第一基底的一第一側上，且具有一第二導電特徵部件組，其位於該第一基底的一第二側上，該封裝體耦接至 位於該第一基底的該第一側上的該第一導電特徵部件組中一第一次組；一第二積體電路晶片，電性耦接至位於該第一基底的該第一側上的該第一導電特徵部件組中一第二次組；一成形材料，至少局部封裝該第二積體電路晶片；以及一應力補償層，順沿著該第一基底的該第二側，該應力補償層內具有複數個開口，以至少局部露出位於該第一基底的該第二側上所對應的該第二導電特徵部件組，當該成形材料施加一應力時，該應力補償層施加一反方向的力，其中該應力補償層的厚度為 ，其中CTEMolding 為該成形材料的熱膨 脹係數，EMolding 為該成形材料的楊氏係數，THKMolding 為該成形材料的厚度，CTECompensation 為該應力補償層的熱膨脹係數，ECompensation 為該應力補償層的楊氏係數。
  5. 如申請專利範圍第4項所述之半導體裝置，其中該應力補償層包括液態成形材料或聚醯亞胺。
  6. 一種半導體裝置之製造方法，包括：提供一第一基底，其具有一第一側及相對的一第二側；將一第一晶片貼合至於該第一基底的該第一側；在該第一基底的該第一側上形成一成形材料；以及在該第一基底的該第二側上形成一應力補償層，包 括以來決定該應力補償層一所需厚 度，其中CTEMolding 為該成形材料的熱膨脹係數，EMolding 為該成形材料的楊氏係數，THKMolding 為該成形材料的厚度，CTECompensation 為該應力補償層的熱膨脹係數，ECompensation 為該應力補償層的楊氏係數。
  7. 如申請專利範圍第6項所述之半導體裝置之製造方法，更包括將一晶片封裝體耦接至該第一基底的該第一側，該晶片封裝體包括一第二晶片且該晶片封裝體覆蓋該第一晶片。
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US9502360B2 (en) 2016-11-22
CN103208465A (zh) 2013-07-17
CN108766940A (zh) 2018-11-06
KR20130082421A (ko) 2013-07-19
KR101476883B1 (ko) 2014-12-26
TW201330215A (zh) 2013-07-16

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