CN116314109A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN116314109A
CN116314109A CN202310321429.XA CN202310321429A CN116314109A CN 116314109 A CN116314109 A CN 116314109A CN 202310321429 A CN202310321429 A CN 202310321429A CN 116314109 A CN116314109 A CN 116314109A
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CN
China
Prior art keywords
dielectric
layer
interposer
semiconductor device
interconnect layer
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CN202310321429.XA
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English (en)
Inventor
丁国强
吴集锡
侯上勇
俞笃豪
许家豪
林品佐
陈家新
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN116314109A publication Critical patent/CN116314109A/zh
Pending legal-status Critical Current

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Abstract

本发明的实施例提供一种半导体装置。所述半导体装置包含：电介质插入器、第一互连层、电子组件、多个电导体及多个导电结构。所述电介质插入器具有第一表面及与所述第一表面相对的第二表面。所述第一互连层在所述电介质插入器的所述第一表面之上。所述电子组件在所述第一互连层之上且电连接到所述第一互连层。所述电导体在所述电介质插入器的所述第二表面之上。所述导电结构穿过所述电介质插入器，其中所述导电结构电连接到所述第一互连层及所述电导体。

Description

半导体装置
分案申请信息
本申请是申请日为2017年11月29日、申请号为201711282738.1、发明名称为“半导体装置及其制作方法”的发明专利申请的分案申请。
技术领域
本揭示涉及一种半导体装置。
背景技术
在集成电路的封装中，半导体裸片可通过接合来堆叠，且堆叠式电子组件之间的互连件可通过硅插入器来实施。硅插入器具有高介电常数，且因此经受电流泄漏及RC延迟。另外，硅插入器的厚度的减小由于其材料性质而受限制，且不能最小化半导体装置的整体体积。
发明内容
根据本发明的一实施例，一种半导体结构包括：电介质插入器，其具有第一表面及与所述第一表面相对的第二表面；第一互连层，其在所述电介质插入器的所述第一表面之上；电子组件，其在所述第一互连层之上且电连接到所述第一互连层；多个电导体，其在所述电介质插入器的所述第二表面之上；及多个导电结构，其穿过所述电介质插入器，其中所述导电结构电连接到所述第一互连层及所述电导体。
根据本发明的一实施例，一种半导体结构包括：非半导电电介质插入器，其具有第一表面及与所述第一表面相对的第二表面；第一互连层，其在所述非半导电电介质插入器的所述第一表面之上；电子组件，其在所述第一互连层之上且电连接到所述第一互连层；多个电导体，其在所述非半导电电介质插入器的所述第二表面之上；多个导电结构，其穿过所述非半导电电介质插入器，且电连接到所述第一互连层及所述电导体；及封装衬底，其在所述多个电导体之上且电连接到所述多个电导体。
根据本发明的一实施例，一种制作半导体装置的方法包括：将电介质层沉积于第一载体衬底之上；在所述电介质层的第一表面之上形成第一互连层；将电子组件安置在所述第一互连层之上；将所述电子组件接合到第二载体衬底并从所述电介质层释放所述第一载体衬底；形成穿过所述电介质层且电连接到所述第一互连层的多个导电结构；及在所述电介质层的第二表面之上形成电连接到所述多个导电结构的多个电导体。
附图说明
当结合附图阅读时，从以下详细描述更佳地理解本发明的实施例的方面。应注意，根据工业中的标准实践，各种结构并非是按比例绘制。事实上，为了清楚地论述，可任意增大或减小各种结构的尺寸。
图1是说明根据本发明的一或多个实施例的各种方面的制作半导体装置的方法的流程图。
图2A、图2B、图2C、图2D、图2E、图2F及图2G是根据本发明的一或多个实施例的制作半导体装置的各种操作中的一个操作处的示意图。
图3是根据本发明的一或多个实施例的半导体装置的示意图。
图4是根据本发明的一或多个实施例的半导体装置的示意图。
图5是说明根据本发明的一或多个实施例的各种方面的制作半导体装置的方法的流程图。
图6A、图6B及图6C是根据本发明的一或多个实施例的制作半导体装置的各种操作中的一个操作处的示意图。
图7是根据本发明的一或多个实施例的半导体装置的示意图。
具体实施方式
以下揭示内容提供用于实施所提供的标的物的不同特征件的许多不同实施例或实例。下文描述元件及布置的具体实例以简化本揭示。当然，这些具体实例仅是实例，且不希望具限制性。举例来说，在以下描述中在第二特征件之上或上形成第一特征件可包含其中第一及第二特征件经形成直接接触的实施例，且还可包含其中额外特征件可经形成于第一与第二特征件之间使得第一与第二特征件可能并不直接接触的实施例。另外，在各种实例中，本揭示可重复元件符号及/或字母。此重复是为了简化及清楚的目的且其本身并不指示所论述的各种实施例及/或配置之间的关系。
此外，为了便于描述，本文可使用空间相对术语，例如“在…下方”、“在…下面”、“下”、“在…上面”、“上部”、“上”及类似物来描述如图中所说明的一个元件或特征件与另一(另外)元件或特征件的关系。空间相对术语希望涵盖装置在使用或操作中除图中所描绘的定向之外的不同定向。设备可以其它方式定向(旋转90度或处于其它定向)，且本文使用的空间相对描述符可同样地因此而解译。
如本文所使用，术语例如“第一”、“第二”及“第三”描述各种元件、组件、区域、层及/或区段，这些元件、组件、区域、层及/或区段不应受这些术语限制。这些术语仅可用于区别一个元件、组件、区域、层或区段与另一元件、组件、区域、层或区段。术语例如“第一”、“第二”及“第三”在用于本文中时不暗含顺序或次序，除非上下文明确指示。
如本文所使用，术语“大约”、“基本上”、“基本”及“约”用于描述及解释小变化。当连同事件或情况一起使用时，术语可指代其中事件或情况恰恰发生的例子以及其中事件或情况近似接近地发生的例子。举例来说，当连同数值一起使用时，术语可指代小于或等于那个数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％。举例来说，如果两个数值之间的差值小于或等于所述值的平均值的±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％，那么可认为两个数值“基本上”相同或相等。举例来说，“基本上”平行可指代相对于0°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或小于或等于±0.05°。举例来说，“基本上”垂直可指代相对于90°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或小于或等于±0.05°。
还可包含其它特征或过程。举例来说，可包含测试结构以协助3D封装或3DIC装置的验证测试。测试结构可包含(例如)形成于重新分布层中或衬底上的测试垫，所述衬底允许测试3D封装或3DIC、使用探针及/或探针板及类似物。可对中间结构以及最终结构执行验证测试。另外，本文揭示的结构及方法可连同并入已知良好裸片的中间验证来增加良率并降低成本的测试方法学一起使用。
在本发明的一或多个实施例中，包含非半导电电介质插入器的半导体装置用于互连安置在其两个相对表面之上的两个或两个以上电子组件。非半导电电介质插入器具有低介电常数，这帮助减轻电流泄漏及RC延迟。具有低介电常数，那么非半导电电介质插入器的厚度可减小，且不会在安置在非半导电电介质插入器的两个相对侧上的电子组件之间引起干扰，且因此，半导体装置的整体体积可减小。
图1是说明根据本发明的一或多个实施例的各种方面的制作半导体装置的方法的流程图。方法100以操作110开始，其中将电介质层沉积在第一载体衬底之上。方法100继续进行操作120，其中在电介质层的第一表面之上形成第一互连层。方法100继续进行操作130，其中在第一互连层之上安置电子组件。方法100继续进行操作140，其中将电子组件接合到第二载体衬底，且从电介质层释放第一载体衬底。方法100继续进行操作150，其中形成穿过电介质层且电连接到第一互连层的多个导电结构。方法100继续进行操作160，其中在电介质层的第二表面之上形成电连接到多个导电结构的多个电导体。
方法100仅是实例，且不希望将本揭示限制在权利要求书中明确陈述的内容之外。可在方法100之前、期间及之后提供额外操作，且针对方法的额外实施例，可替换、取消或移动所描述的一些操作。
图2A、图2B、图2C、图2D、图2E、图2F及图2G是根据本发明的一或多个实施例的制作半导体装置的各种操作中的一个操作处的示意图。如图2A中所描绘，电介质层20经沉积于第一载体衬底10之上。第一载体衬底10经配置为用于形成电介质层20及其它结构层的临时载体衬底，且随后将被移除。在一些实施例中，第一载体衬底10可包含(但不限于)毯晶片。电介质层20包含第一表面201及与第一表面201相对的第二表面202。在一些实施例中，电介质层20由非半导电材料制成。在一些实施例中，电介质层20经配置为加固层，以增强半导体装置的稳健性。在一些实施例中，电介质层20经配置为非半导电电介质插入器，其可替换例如硅插入器的半导体插入器。在一些实施例中，电介质层20的介电常数小于例如硅插入器的半导体插入器的介电常数。在一些实施例中，电介质层20的介电常数在从约1到约10的范围内。作为实例，电介质层20的介电常数在从约3到约8的范围内，在从约3到约7的范围内，在从约3到约6的范围内，在从约3到约5的范围内或在从约3到约4的范围内。在一些实施例中，电介质层20的弹性模量不同于例如硅插入器的半导体插入器的弹性模量。作为实例，电介质层20的弹性模量大于例如硅插入器的半导体插入器的弹性模量。在一些实施例中，电介质层20的厚度小于例如硅插入器的半导体插入器的厚度，半导体插入器的厚度大于50微米。作为实例，电介质层20的厚度在从约5微米到约30微米的范围内，在从约10微米到约25微米的范围内，在从约10微米到约20微米的范围内或在从约10微米到约15微米的范围内。在一些实施例中，电介质层20可例如通过化学气相沉积(CVD)、物理气相沉积(PVD)、旋涂、分配或其它合适的操作形成于第一载体衬底10之上。在一些实施例中，电介质层20包含无机电介质材料，例如氧化硅、氮化硅、氮氧化硅、其组合或其它合适的无机电介质材料。在一些实施例中，电介质层20包含有机电介质材料，例如聚酰亚胺、聚甲基丙烯酸甲酯(PMMA)、聚苯并恶唑(PBO)、其组合或其它合适的有机电介质材料。在一些实施例中，电介质层20是单层电介质层，其可包含上述无机电介质材料或有机电介质材料。
如图2B中所描绘，第一互连层30形成于电介质层20的第一表面201之上。在一些实施例中，第一互连层30可包含一或多个重新分布层(RDL)、一或多个路由层或类似物。在一些实施例中，第一互连层30可包含绝缘层31、32及穿过绝缘层31、32的导电层33。
如图2C中所描绘，电子组件40经安置于第一互连层30之上且电连接到第一互连层30。在一些实施例中，电子组件40可包含一或多个半导体裸片、一或多个半导体封装或其它有源或无源电子组件。在一些实施例中，电子组件40使用电连接器42(例如导电凸块、导电膏、导电球或类似物)电连接到第一互连层30。在一些实施例中，底料填充层44可经插入于电子组件40与第一互连层30之间且环绕电连接器42。在一些实施例中，囊封剂46(例如模制化合物)可形成于第一互连层30之上以围封电子组件40的一部分。在一些实施例中，囊封剂46可围封电子组件40的一部分，例如电子组件40的边缘。在一些实施例中，囊封剂46可进一步围封电子组件40的上表面。
如图2D中所描绘，电子组件40接合到第二载体衬底12。在一些实施例中，第二载体衬底12经配置为临时载体衬底，其用于支撑电介质层20、第一互连层30及电子组件40使得其它层或组件可形成于电介质层20的第二表面202之上。在一些实施例中，第二载体衬底12可包含(但不限于)毯晶片。在一些实施例中，电子组件40使用粘着层14接合到第二载体衬底12。在将电子组件40接合到第二载体衬底12之后，可从电介质层20的第一表面201释放第一载体衬底10。
如图2E中所描绘，形成穿过电介质层20且电连接到第一互连层30的多个导电结构50。在一些实施例中，钝化层52可形成于电介质层20的第二表面202之上，且导电结构50可进一步穿透钝化层52。在一些实施例中，导电结构50的厚度基本上等于电介质层20的厚度。在一些实施例中，导电结构的厚度在从约5微米到约30微米的范围内。
如图2F中所描绘，多个电导体60形成于电介质层20的第二表面202之上且分别电连接到导电结构50。在一些实施例中，多个接合垫62可分别形成于电导体60与导电结构50之间。在一些实施例中，接合垫62可(但不限于)由掩模层64(例如焊料掩模)界定。在一些实施例中，电导体60可包含堆叠到彼此的第一导电材料601及第二导电材料602。作为实例，第一导电材料601可包含铜，且第二导电材料602可包含锡。
如图2G中所描绘，第二载体衬底12从电子组件40释放以形成本发明的一些实施例的半导体装置1。
在本发明的一些实施例中，半导体装置1使用电介质层20作为电介质插入器以互连第一表面201之上的电子组件40及第二表面202之上的电导体60。与半导体插入器相比，电介质插入器可包含以下优点。电介质插入器具有低成本。电介质插入器更薄，这使互连距离变短以改进电性能。电介质插入器具有低介电常数，这帮助减轻安置于插入器的两个相对表面上的电子组件之间的电流泄漏及RC延迟。具有低介电常数，电介质插入器的厚度可减小，而不会在安置在插入器的两个相对表面上的电子组件之间引起干扰，且因此，半导体装置1的整体体积可减小。电介质插入器比半导体插入器更灵活，且因此可帮助释放应力且减小分层风险。
图3是根据本发明的一或多个实施例的半导体装置的示意图。如图3中所描绘，与图2G的半导体装置1相比，半导体装置1'的电介质层20可包含多层电介质层，其可包含堆叠在彼此上的两个或两个以上电介质膜21及22。多层电介质层的膜21及22中的每一者可个别地包含无机电介质材料或有机电介质材料。作为实例，电介质膜21可包含无机电介质材料，例如氧化硅、氮化硅、氮氧化硅、其组合或其它合适的无机电介质材料。其它电介质膜22可包含有机电介质材料，例如聚酰亚胺、聚甲基丙烯酸甲酯(PMMA)、聚苯并恶唑(PBO)、其组合或其它合适的有机电介质材料。在一些实施例中，电介质膜21可包含有机电介质材料，而电介质膜22可包含无机电介质材料。在一些实施例中，多层电介质层20的介电常数小于例如硅插入器的半导体插入器的介电常数。在一些实施例中，电介质层20的介电常数在从约1到约10的范围内。作为实例，多层电介质层20的介电常数在从约3到约8的范围内，在从约3到约7的范围内，在从约3到约6的范围内，在从约3到约5的范围内或在从约3到约4的范围内。在一些实施例中，多层电介质层20的弹性模量不同于例如硅插入器的半导体插入器的弹性模量。作为实例，电介质层20的弹性模量大于例如硅插入器的半导体插入器的弹性模量。在一些实施例中，多层电介质层20的厚度小于例如硅插入器的半导体插入器的厚度，半导体插入器的厚度大于50微米。作为实例，电介质层20的厚度在从约5微米到约30微米的范围内，在从约10微米到约25微米的范围内，在从约10微米到约20微米的范围内，或在从约10微米到约15微米的范围内。
在本发明的一些实施例中，半导体装置1'使用多层电介质层20作为电介质插入器以互连第一表面201之上的电子组件40与第二表面202之上的电导体60。与半导体插入器相比，电介质插入器可包含以下优点。电介质插入器具有低成本。电介质插入器更薄，这使互连距离变短以改进电性能。电介质插入器具有低介电常数，这帮助减轻安置于插入器的两个相对表面上的电子组件之间的电流泄漏及RC延迟。具有低介电常数，电介质插入器的厚度可减小，而不会在安置在插入器的两个相对表面上的电子组件之间引起干扰，且因此，半导体装置1'的整体体积可减小。电介质插入器比半导体插入器更灵活，且因此可帮助释放应力且减小分层风险。多层电介质层20可进一步经配置以补偿邻近结构层之间的非匹配(例如CTE非匹配或应力非匹配)，且因此可缓和翘曲问题。
本揭示的半导体装置及其制作方法不限于上文提及的实施例，且可具有其它不同实施例。为简化描述，且为便于在本发明的实施例中的每一者之间作比较，使用相同元件符号标记以下实施例中的每一者中的相同组件。为了使其更容易比较实施例之间的差异，以下描述将详细描述不同实施例之中的相异点，且将不再冗余地描述相同特征。
图4是根据本发明的一或多个实施例的半导体装置的示意图。如图4中所描绘，与图2G的半导体装置1相比，半导体装置2可包含衬底上晶片上芯片(COWOS)封装结构，其可进一步包含电导体60之上的且电连接到电导体60的封装衬底70。在一些实施例中，电路可形成于封装衬底70中。在一些实施例中，半导体装置2可进一步包含封装衬底70之上的且电连接到封装置衬底70的且与电导体60相对的多个第二电导体72。第二电导体72可通过封装衬底70、电导体60、导电结构50及第一互连层30电连接到电子组件40。在一些实施例中，第二电导体72经配置以将电子组件40电连接到另一电子组件(例如印刷电路板(PCB))。在一些实施例中，第二电导体72可包含(但不限于)导电凸块、导电膏、导电球或类似物。在一些实施例中，电介质层20可为如图2A到2G中描述的单层电介质层。在一些实施例中，电介质层20可为如图3中描述的多层电介质层。
在本发明的一些实施例中，半导体装置2使用电介质层20作为电介质插入器以互连第一表面201之上的电子组件40与第二表面202之上的电导体60。与半导体插入器相比，电介质插入器可包含以下优点。电介质插入器具有低成本。电介质插入器更薄，这使互连距离变短以改进电性能。电介质插入器具有低介电常数，这帮助减轻安置于插入器的两个相对表面上的电子组件之间的电流泄漏及RC延迟。具有低介电常数，那么电介质插入器的厚度可减小，且不会在安置在插入器的两个相对表面上的电子组件之间引起干扰，且因此，半导体装置2的整体体积可减小。电介质插入器比半导体插入器更灵活，且因此可帮助释放应力且减小分层风险。
图5是说明根据本发明的一或多个实施例的各种方面的制作半导体装置的方法的流程图。方法200以操作110开始，其中将电介质层沉积在第一载体衬底之上。方法继续进行操作120，其中在电介质层的第一表面之上形成第一互连层。方法继续进行操作130，其中在第一互连层之上安置电子组件。方法继续进行操作140，其中将电子组件接合到第二载体衬底，且从电介质层释放第一载体衬底。方法继续进行操作150，其中形成穿过电介质层且电连接到第一互连层的多个导电结构。方法继续操作155，其中在电介质层的第二表面之上形成第二互连层。方法继续进行操作160，其中在电介质层的第二表面之上形成电连接到多个导电结构的多个电导体。
方法200仅是实例，且不希望将本揭示限制在权利要求书中明确陈述的内容之外。可在方法200之前、期间及之后提供额外操作，且针对方法的额外实施例，可替换、取消或移动所描述的一些操作。
图6A、图6B及图6C是根据本发明的一或多个实施例的制作半导体装置的各种操作中的一个操作处的示意图。在一些实施例中，可在图2E之后实施图6A、图6B及图6C的半导体装置的制作。如图6A中所描绘，第二互连层80形成于电介质层20的第二表面202之上且电连接到导电结构50。在电导体60形成之前形成第二互连层80。在一些实施例中，第二互连层80可包含一或多个重新分布层(RDL)、一或多个路由层或类似物。在一些实施例中，第二互连层80可包含一或多个绝缘层81及穿过绝缘层81的一或多个导电层82。
如图6B中所描绘，在一些实施例中，另一钝化层84可形成于第二互连层80之上。在一些实施例中，钝化层84暴露第二互连层80的一部分。多个电导体60形成于第二互连层80之上且通过第二互连层80电连接到导电结构50。在一些实施例中，多个接合垫62可形成于电导体60与第二互连层80之间。在一些实施例中，接合垫62可(但不限于)由掩模层64(例如焊料掩模)界定。在一些实施例中，电导体60可包含堆叠到彼此的第一导电材料601及第二导电材料602。作为实例，第一导电材料601可包含铜，且第二导电材料602可包含锡。
如图6C中所描绘，第二载体衬底12从电子组件40释放以形成本发明的一些实施例的半导体装置3。
在本发明的一些实施例中，半导体装置3使用电介质层20作为电介质插入器以互连第一表面201之上的电子组件40与第二表面202之上的电导体60。与半导体插入器相比，电介质插入器可包含以下优点。电介质插入器具有低成本。电介质插入器更薄，这使互连距离变短以改进电性能。电介质插入器具有低介电常数，这帮助减轻安置于插入器的两个相对表面上的电子组件之间的电流泄漏及RC延迟。具有低介电常数，那么电介质插入器的厚度可减小，且不会在安置在插入器的两个相对表面上的电子组件之间引起干扰，且因此，半导体装置3的整体体积可减小。电介质插入器比半导体插入器更灵活，且因此可帮助释放应力且减小分层风险。在一些实施例中，第二互连层80可经配置以重新分布电路布局。在一些实施例中，电介质层20可为如图2A到2G中描述的单层电介质层。在一些实施例中，电介质层20可为如图3中描述的多层电介质层。
图7是根据本发明的一或多个实施例的半导体装置的示意图。如图7中所描绘，与图6C的半导体装置3相比，半导体装置4可包含衬底上晶片上芯片(COWOS)封装结构，其可进一步包含电导体60之上的且电连接到电导体60的封装衬底70。在一些实施例中，电路可形成于封装衬底70中。在一些实施例中，半导体装置4可进一步包含封装衬底70之上的且电连接到封装置衬底70的且与电导体60相对的多个第二电导体72。第二电导体72可通过封装衬底70、电导体60、导电结构50及第一互连层30电连接到电子组件40。在一些实施例中，第二电导体72经配置以将电子组件40电连接到另一电子组件(例如印刷电路板(PCB))。在一些实施例中，第二电导体72可包含(但不限于)导电凸块、导电膏、导电球或类似物。在一些实施例中，电介质层20可为如图2A到2G中描述的单层电介质层。在一些实施例中，电介质层20可为如图3中描述的多层电介质层。
在本发明的一些实施例中，半导体装置4使用电介质层20作为电介质插入器以互连第一表面201之上的电子组件40与第二表面202之上的电导体60。与半导体插入器相比，电介质插入器可包含以下优点。电介质插入器具有低成本。电介质插入器更薄，这使互连距离变短以改进电性能。电介质插入器具有低介电常数，这帮助减轻安置于插入器的两个相对表面上的电子组件之间的电流泄漏及RC延迟。具有低介电常数，电介质插入器的厚度可减小，而不会在安置在插入器的两个相对表面上的电子组件之间引起干扰，且因此，半导体装置4的整体体积可减小。电介质插入器比半导体插入器更灵活，且因此可帮助释放应力且减小分层风险。在一些实施例中，第二互连层80可经配置以重新分布电路布局，且从第二电导体72释放应力。
在本发明的一或多个实施例中，非半导电电介质插入器用于互连安置在其两个相对表面之上的两个或两个以上电子组件。与半导体插入器相比，非半导电电介质插入器具有低介电常数，这帮助减轻电流泄漏及RC延迟。具有低介电常数，非半导电电介质插入器的厚度可减小，而不会在安置在非半导电电介质插入器的两个相对侧上的电子组件之间引起干扰，且因此，半导体装置的整体体积可减小。在本发明的一些实施例中，非半导电电介质插入器比半导体插入器更灵活，且因此帮助减小分层风险。在本发明的一些实施例中，非半导电电介质插入器可为多层的，其可经配置以补偿邻近结构层之间的非匹配(例如CTE非匹配或应力非匹配)，且因此可缓和翘曲问题。
在一个示范性方面中，半导体装置包含电介质插入器、第一互连层、电子组件、多个电导体及多个导电结构。所述电介质插入器具有第一表面及与所述第一表面相对的第二表面。所述第一互连层在所述电介质插入器的所述第一表面之上。所述电子组件在所述第一互连层之上且电连接到所述第一互连层。所述电导体在所述电介质插入器的所述第二表面之上。所述导电结构穿过所述电介质插入器，其中所述导电结构电连接到所述第一互连层及所述电导体。
在另一方面中，半导体装置包含非半导电电介质插入器、第一互连层、电子组件、多个电导体、多个导电结构及封装衬底。所述非半导电电介质插入器具有第一表面及与所述第一表面相对的第二表面。所述第一互连层在所述非半导电电介质插入器的所述第一表面之上。所述电子组件在所述第一互连层之上且电连接到所述第一互连层。所述电导体在所述非半导电电介质插入器的所述第二表面之上。所述导电结构穿过所述电介质插入器，且电连接到所述第一互连层及所述电导体。所述封装衬底在所述多个电导体之上且电连接到所述多个电导体。
在又另一方面中，一种制作半导体装置的方法包含：将电介质层沉积于第一载体衬底之上；在所述电介质层的第一表面之上形成第一互连层；将电子组件安置在所述第一互连层之上；将所述电子组件接合到第二载体衬底并从所述电介质层释放所述第一载体衬底；形成穿过所述电介质层且电连接所述第一互连层的多个导电结构；及在所述电介质层的第二表面之上形成电连接到所述多个导电结构的多个电导体。
前述内容概述若干实施例的结构使得所属领域的技术人员可更佳地理解本揭示的方面。所属领域的技术人员应了解，他们可容易地使用本揭示作为设计或修改用于实施本文介绍的实施例的相同目的及/或实现本文介绍的实施例的相同优点的其它过程及结构的基础。所属领域的技术人员还应意识到，此类等效构造不背离本揭示的精神及范围，且他们可在不背离本揭示的精神及范围的情况下在本文中做出各种变化、替代、及更改。

Claims (10)

1.一种半导体装置，其包括：
电介质插入器，其具有第一表面及与所述第一表面相对的第二表面；
第一互连层，其在所述电介质插入器的所述第一表面之上，其中所述第一互连层包括重新分布层；
电子组件，其在所述第一互连层之上且电连接到所述第一互连层；
电连接器，其在所述重新分布层与所述电子组件之间且电连接到所述重新分布层及所述电子组件；
电导体，其在所述电介质插入器的所述第二表面之上；
导电结构，其穿过所述电介质插入器，其中所述导电结构电连接到所述第一互连层及所述电导体；
第二互连层，其在所述电介质插入器的所述第二表面之上；及
钝化层，其在所述电介质插入器与所述第二互连层之间，所述导电结构穿过所述钝化层。
2.根据权利要求1所述的半导体装置，其中所述导电结构包含梯形横截面形状。
3.根据权利要求1所述的半导体装置，其中所述电介质插入器的厚度在从5微米到30微米的范围内。
4.根据权利要求1所述的半导体装置，其中所述电介质插入器包括无机电介质材料。
5.根据权利要求4所述的半导体装置，其中所述无机电介质材料包括氧化硅、氮化硅、氮氧化硅或其组合。
6.根据权利要求1所述的半导体装置，其中所述电介质插入器包括有机电介质材料。
7.根据权利要求6所述的半导体装置，其中所述有机电介质材料包括聚酰亚胺、聚甲基丙烯酸甲酯PMMA、聚苯并恶唑PBO或其组合。
8.根据权利要求1所述的半导体装置，其中所述电介质插入器是多层式插入器。
9.根据权利要求1所述的半导体装置，其中所述电导体通过所述第二互连层电连接到所述导电结构。
10.一种半导体装置，其包括：
电介质层，其具有第一表面及与所述第一表面相对的第二表面，其中所述电介质层包括堆叠在彼此上的多个电介质膜，且所述电介质层的介电常数在从1到10的范围内；
第一互连层，其在所述电介质层的所述第一表面之上，其中所述第一互连层包括重新分布层；
电子组件，其在所述第一互连层之上；
电连接器，其在所述重新分布层与所述电子组件之间且电连接到所述重新分布层及所述电子组件；
电导体，其在所述电介质层的所述第二表面之上；
导电结构，其穿过所述电介质层的所述多个电介质膜，且电连接到所述第一互连层及所述电导体，所述导电结构具有接近所述第一互连层的第三表面及接近所述电导体的第四表面，且所述第四表面的宽度比所述第三表面的宽度宽；及
第二互连层，其在所述电介质层的所述第二表面之上，其中所述第二互连层通过钝化层与所述电介质层分离，所述导电结构穿过所述钝化层并将所述第二互连层电连接到所述第一互连层。
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