TW201227901A - Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask - Google Patents

Abstract

A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.

Description

201227901 VI. INSTRUCTIONS: [Priority Claims] This application is part of the continuation of US Application No. 12/47 1,1 80, filed May 22, 2009, and claims the aforementioned basic application in accordance with Articles of the US Patent Law. Priority of the case. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to semiconductor devices, and more particularly to a self-confinement of conductive bumps during reflow soldering without solder masking. Semiconductor device and method. [Prior Art] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices differ in the number and density of electrical components. Discrete semiconductor devices typically comprise a type of electrical component such as a 'LED', a small signal transistor, a resistor, a capacitor, an inductor, and a power metal oxide semiconductor field effect transistor (10) (4)) . Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of the sinusoidal sinusoidal bar + conductor device include a microcontroller, a microprocessor, a charge surface 爹 device, a solar cell, and a digital micromirror device (DMD). Semiconductor devices can perform a wide range of functions, such as signal processing, high speed computing, transmitting and receiving electromagnetic signals [control electronics, converting sunlight into electricity, and producing visible projections for television displays. Semiconductor devices can be found in the fields of entertainment, communication, power conversion, electric knife replacement, network, and computer in 201227901 and 4 expense products. Fengniu conductors can also be found in military, civil, automotive, industrial batches such as the use of control and office equipment. The semiconductor device utilizes the electrical characteristics of a semiconductor material such as a semiconductor. The atomic structure of the semiconductor material allows it to conduct a Thunder. A conductivity can be controlled by the application of an electric or base current or by the doping of the X-ray. The doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device. Semiconductor devices include active and passive electrical structures. Active structures containing bipolar and field effect transistors control the flow of current. By changing the degree of doping and the level at which the electric field or base current is applied, the transistor does not boost or limit the flow of current. Passive structures containing resistors, capacitors, and inductors produce a relationship between voltage and current necessary to perform various t-gas functions. The passive and active structures are electrically connected to form a circuit that enables the semiconductor device to perform high speed calculations and other useful functions. Semiconductor devices are typically fabricated using two complex processes, namely front-end manufacturing and back-end manufacturing, each involving hundreds of steps. Front end manufacturing involves the formation of a plurality of grains on the surface of a semiconductor wafer. Each die is typically the same and contains circuitry formed by electrically connecting the active and passive components. Back-end manufacturing involves singulating individual dies from wafer fabrication and packaging the dies to provide structural support and environmental isolation. One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume lower power, are more efficient, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller 201227901 footprint, which is desirable for smaller end products. Smaller grain sizes can be achieved by producing grain improvements with smaller and higher density active and passive components in the front end process. The backend process can be modified by electrical interconnects and packaging materials to create a semiconductor device package with a smaller footprint. 1 is a diagram depicting a portion of a flip-chip type semiconductor device 1 having interconnects 12 that are metallurgically and electrically connected between bump pads 14 and line conductors 20 using a germanium mask 15. As shown in Fig. 2, a circular solder mask or alignment opening (SR0) 16 is formed over the substrate 18 to expose the line conductors 20. The line conductor 20 is a straight conductor having an optional bump pad for mating to the interconnector 2. The SR0 1 6 system confines the conductive bump material to the bump pads of the line conductor 20 during reflow and prevents molten bump material from escaping onto the line conductors, which may cause electrical shorts to adjacent structures. The sr system is made larger than the line conductor or bump pad. The sr 〇 16 is generally circular in shape and made as small as possible to reduce the pitch of the line conductors 2 增 and increase the winding density. In a typical design rule, the minimum escape of the line conductor 20 is limited by the sr〇16 must be at least the base diameter (D) of the interconnect 丨2 plus a solder mask alignment tolerance. (SRT) The same big truth. In addition, due to the limitations of the solder mask application process, the smallest aperture (L, ligament) of the solder mask material is required in adjacent openings. More specifically, the minimum escape spacing is defined as P = D + 2 * SRT + L. In one embodiment, 〇 is 1 微米 micron (μηι) ′ SRT is ΙΟμηι, and L is 60 μηι, therefore, the minimum escape pitch is 100 + 2* 10 + 60 = 80 μm. 6 201227901 Figures 3a and 3b show top and cross-sectional views of another conventional configuration in which the line conductors 30 are wound between the line conductors 32 and 34 on the substrate 40 and the bumps 36 and 38. Bumps 36 and 38 electrically connect semiconductor die 42 to substrate 40. Solder mask 44 covers bump pads 46 and 48. The minimum escape spacing of the line conductors 30 is defined by p = D / 2 + SRT + L + w / 2, where D is the bump base diameter, SRT is the solder mask alignment tolerance, and W is the line The route is wide and L is the hole spacing between the SR〇 and the adjacent structure. In one embodiment, D is 1 〇〇 _, SRT is ι 〇 μηη, w is 3 〇 _, and L is 60 μηη. The minimum escape spacing of the line conductors 3〇·34 is 100/2+1 (Η60 + 30/2 = 135 μηη. Due to the increased demand for high winding density), a smaller escape spacing is required. There is a need to minimize the escape spacing of the line conductors to achieve higher winding densities. Thus, in one embodiment, the present invention is a method of fabricating a semiconductor device that includes the steps of providing a grain bump a semiconductor die of a bulk pad; providing a substrate having a conductive trace, having an interconnecting location, depositing a conductive bump material on the interconnect location or the die bump, mounting the semiconductor die to the Substrate such that the conductive bump material is disposed between the die bump pad and the interconnect location; the conductive bump material is reflowed without a solder mask around the die bump pad or interconnect location to An interconnect structure is formed between the semiconductor die and the substrate; and an encapsulation material is deposited between the semiconductor die and the substrate. The conductive bump material is self-limited in the die pad pad or interconnection position. In another embodiment, the invention is a method of fabricating a semiconductor device, comprising the steps of: providing a first semiconductor structure having a first interconnect location; providing a second having a second interconnect location a semiconductor structure, - depositing a conductive bump material between the first and second interconnect locations - forming an interconnect structure from the conductive bump material without a tantalum mask around the first and second interconnect locations Encapsulating the first and second semiconductor structures between the first and first semiconductor structures. The conductive bump material is self-limited in the first and second interconnection locations. In another embodiment, the invention is a method of fabricating a semiconductor device comprising the steps of: providing a first semiconductor structure having a first interconnect location; providing a second semiconductor structure having a second interconnect location; Depositing a conductive bump material over the interconnect location or the second interconnect location; and forming an interconnect structure from the conductive bump material under the first and second interconnect locations without a solder mask to bond the first And a second semiconductor structure. In another embodiment, the invention is a semiconductor device comprising a first semiconductor structure having a first interconnection location and a second semiconductor structure having a second interconnection location. Formed between the first and second semiconductor structures without a solder mask around the first and second interconnect locations. An encapsulation material is deposited between the first and second semiconductor structures. The invention is described in the following description with reference to the drawings, wherein the same reference numerals refer to the same or similar elements. Although the invention is described in accordance with the best mode for the purpose of the invention, 8 201227901 The skilled artisan will understand that the present invention is intended to cover alternatives, modifications, and equivalents, which are included in the spirit and scope of the invention as defined by the appended claims. Its equivalent. Semiconductor devices are typically fabricated using two complex processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a Ba particle on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, resistors, and transformers produce a relationship between voltage and current necessary to perform circuit functions. The passive and active components are formed on the surface of the semiconductor wafer by a series of process steps including doping, deposition, lithography, lithography, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process changes the conductivity of the semiconductor material in the active device, thereby converting the semiconductor material into an insulator, a conductor, or dynamically changing the conductivity of the semiconductor material in response to an electric field or base current. The transistor contains regions of varying type and extent that are optionally Z to enable the transistor to promote or limit current flow when an electric or base current is applied. Active and passive components are formed from layers of material having different electrical properties. The layers can be formed by a variety of deposition techniques that are determined in part by the type of material being deposited. For example, thin film deposition can include chemical vapor deposition (CVD) 'physical vapor deposition (PVD), electrolytic forging, and electroless plating processes. Each layer is typically patterned to form an active member: 201227901 Broken member or portion of the electrical connection between the components. (Example/1 layers may be used to pattern (10) the rows of the material, which are deposited on the layer to be patterned. Qian Guang removes the pattern from the light = printing solvent to remove the resist pattern. Part 1: The lower part of the layer to be patterned. The rest of the photoresist is removed leaving a patterned layer. Alternatively, certain types of materials are patterned using direct plating techniques such as electroless plating and electroplating by depositing the material directly into regions or voids formed by previous deposition/etch processes. Depositing a film of material over an existing pattern may magnify the pattern below and produce a surface that is not flat. Active and passive components that produce smaller, denser packages require a flat surface. Planarization can be used to remove material from the rounded surface and produce a flat surface. The planarization system uses the surface of the polished (iv) optical wafer. The abrasive material and the rot are chemically etched during polishing. . Add to the surface of the wafer. The combination of the mechanical action of the abrasive and the rotative action of the chemical can remove any irregular surface configuration, resulting in a uniform, flat surface. “Back-end manufacturing refers to cutting or simply cutting a finished wafer into individual dies and then encapsulating the dies to provide structural support and environmental isolation. For single-cut dies, along the non-functional area of the wafer (called Cutting or dicing the wafer. Cutting the wafer using a laser cutting tool or a strip. After a single dicing, the individual dies are mounted on a package substrate that includes pins. Or contact pads for interconnection with other system components. The contacts formed on the semiconductor die are then rigidly bonded to the contact pads in the package. The electrical connections may be by solder bumps, stud bumps, conductive paste or bond wires. ebGnd) is formed by depositing a skirt 10 201227901 material or other molding material on the package to provide physical support and electrical isolation, and then inserting the package into an electrical system, and enabling the function of the semiconductor device Other system components utilize β. FIG. 4 depicts an electronic device 5 having a plurality of wafer carrier substrates or printed circuit boards (pCBs) 52 mounted on a surface thereof. Depending on the application, the electronic device 5G may have a type A semiconductor package or a plurality of semiconductor packages of different types. Different types of semiconductor packages are shown for purposes of illustration in Figure 4. The electronic device 50 can be a separate system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device 5 can be a sub-component of a larger system. For example, the electronic device 5 can be a mobile phone, a personal digital assistant (PDA), a digital video camera (DVC), or other electronic communication device. Alternatively, the electronic device 50 can be a pluggable, display card in a computer, a network interface card or other signal processing card. The semiconductor package can include a microprocessor, a memory, and a special application integrated circuit. (ASIC), logic circuit, analog circuit, RF circuit 'discrete device or its: semiconductor die or electrical component. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be Shortened to achieve higher density. ', in Figure 4, PCB 52 provides a general substrate for mounting on the semiconductor package Structural support and electrical interconnection. The conductive signal line 54 is formed on a surface of the pCB 52 or on the surface by a metal deposition process using steaming, electrolytic plating, electroless electric forging, screen printing or potting. Signal line 54 provides electrical communication between each of the semiconductor package, mounted components, 11 201227901, and other external system components. Line 54 also provides power and ground connections to each semiconductor package. A semiconductor device has two package levels. The first level package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate carrier. The second level of package involves the intermediate carrier mechanism. And electrically attached to the PCB. In other embodiments, a semiconductor device may have only the first level of packaging, wherein the die is directly mechanically and electrically mounted to the PCB. For purposes of illustration, several types of 帛 one layer, stage packages including wire bond package 56 and flip chip 58 are shown on pcB 52. In addition, a ball grid array (BGA) 6 〇, a bump wafer carrier (Bcc) 62, a double row package (DIP) 64, a platform grid array (LGA) 66, a multi-chip module (MCM) 68, A four-sided flat leadless package (QFN) 7" and a four-level package with four sides of a flat package 72 are shown mounted on the μ. Any combination of semiconductor packages and other electronic components configured in any combination of the first and second level package types may be coupled to PCB 52, depending on system requirements. In some embodiments 'electronic device 5' includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. Manufacturers can incorporate prefabricated components into electronic devices and systems by combining them on a single-substrate—or multiple semiconductor packages. Since semiconductor packages include complex functions, electronic devices can be fabricated using less expensive components and streamlined processes. The resulting device is less likely to fail and has a lower manufacturing cost' thereby reducing consumer costs.

5a-5d shows an exemplary semiconductor package. Figure 5a depicts further details of the installation of 12 201227901 DIP64 on PCB 52. The semiconductor die includes an active region including an analog or digital circuit, and the analog or digital circuit is implemented as an active device, a passive device, a conductive layer, and a dielectric layer formed in the die and according to the die Electrically designed and electrically interconnected. For example, the circuit can include a plurality of transistors, diodes, inductors, capacitors, resistors, and other devices formed in the active region of the semiconductor die 74. The contact pad 76 is one or more layers of a conductive material such as aluminum (A", copper (Cu), tin (Sn), nickel (Ni), gold (Au) or silver (Ag), and is electrically connected to the semiconductor crystal. The circuit element of the grain 74. During the assembly of the mp ,, the semiconductor die 74 is mounted to an intermediate carrier 78 using a metal eutectic layer or an adhesive material such as a thermal epoxy. The package main system contains An insulating encapsulating material such as a polymer or ceramic. The wires and bonding wires 82 provide electrical interconnection between the semiconductor die 74 and the pCB 52. The encapsulation material 84 is deposited over the package for environmental protection to prevent Moisture particles enter the package and contaminate the die 74 or bond wire 82. The μ figure depicts a further detail of the bcc 62 mounted on the pCB 52. The semiconductor die 88 is filled with a primer (4) 咐(1)) Or an epoxy adhesive material 92 is mounted over the carrier 9. The bonding wire 94 provides a first level of package interconnection between the contact % and 98. The molding compound, the package _ _ deposited in The semiconductor die 88 and the wire bond are provided above, and are cut and electrically isolated. The bonding (4) is formed on a surface of the PCB 52 by a suitable metal deposition process such as electroplating or electroless plating to avoid oxidation. The contact pads 102 are electrically connected to one of the PCBs 52. a plurality of conductive signal lines 54. Bumps 104

13 S 201227901 is formed between the contact pads 98 of the BCC 62 and the contact pads ι of the pCB 52. In Fig. 5c, the semiconductor die 58 is mounted face down to the intermediate carrier 1〇6 in a flip-chip type first level package. The active region 2 (10) of the semiconductor die 58 includes analog or digital circuitry that is implemented as an active device, a passive device, a conductive layer, and a dielectric layer formed in accordance with the electrical design of the die. For example, the circuit can include one or more of a transistor body, an inductor, a capacitor, a resistor, and other circuitry within the active region ι8. The semiconductor die 58 is electrically and mechanically connected to the carrier 1 透过 6 through the bumps i 1 . The BGA 60 is electrically and mechanically connected to the PCB 52 by bumps m in a BGA type second level package. Semiconductor die 58 is electrically coupled to conductive signal line 54 in PCB 52 via bumps, wires 114 and bumps 112. a molding compound or encapsulating material 116, deposited over the semiconductor die 58 and the carrier 106 to provide physical support and electrical isolation to the device. The flip-chip semiconductor device provides active from the semiconductor die 58 A short conductive path to the conductive traces on the PCB 52 to reduce signal propagation distance, reduce capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 can be directly and mechanically and electrically connected to the pCB 52 using a Ba-type first level package without an intermediate carrier. In another embodiment, the active region 1 〇 8 of the semiconductor die 58 is mounted directly down to the PCB 117, i.e., directly down without the intermediate carrier, as shown in Figure 5d. The block pad ln is formed on the active region 108 by a vapor deposition, electrolytic plating, electroless plating, screen printing or other suitable metal sinking process. The bump pads iu are connected to the active and passive circuits by conductive traces in the active region 108. The bump 塾 111 may be Al, Sn, Ni, Au, Ag or Cu. - the conductive bump material is deposited by a vapor deposition, electrolytic plating, electroless plating, ball drop or screen printing process on the bump pad n 成 ^ bump material can be A Sn, Ni, Au, Ag, lead (Pb), Bi, Cu, tantalum, and combinations thereof, have an optional flux material. For example, the bump material can be eutectic Sn/Pb, high lead solder or lead free solder. The bump material is bonded to the die bumps 160 by a suitable attachment or bonding process. In one embodiment, the bump material is soldered back and forth to form a ball or bump U7 by heating the material beyond its melting point. In some applications, the bumps P are subjected to secondary reflow to improve electrical contact to the bumps & lu. The flip-chip semiconductor device provides a short conductive path from the main conductive traces on the semiconductor die 58 to (4) reduce the capacitance and achieve overall better circuit performance. 6a and 6b are plan views showing a portion of a flip chip type semiconductor die 120 having a die bump pad 122 and a cross section i line wire m being - having a body type (4) formed on a substrate or a PCB 13G. It is called the straight conductor of the bump 塾126. Figure 7^7b shows further details of the substrate bump 塾(3): the line conductor m. The substrate projections (four) 126 may be circular as shown in Figure 7a or rounded as shown in Figure 7b. The sides of the substrate bumps 126 may be collinear with the line conductors. The conductive bump material is deposited over the die bump pads 122 or 15 201227901 substrate bump pads 126 using an evaporation, electrolytic plating, electroless 'mine, ball drop, or screen printing process. The bump material may be A1, Sn, Ni, Au,

Ag Pb Bi Cu solder and combinations thereof have an optional fluxing solvent. For example, the bump material can be eutectic Sn/pb, high lead solder or no ship solder. The bump material is bonded to the die bump pads 122 and the substrate bump pads 126 using a suitable attachment or bonding process. In one embodiment, the bump material is # reflowed by adding & the material beyond its dazzle to form interconnects 132. In some applications, interconnect 132 is subjected to secondary reflow to improve electrical contact between die bumps 2 and substrate bumps 126. The bump material around the narrow substrate bumps 126 maintains the die arrangement during the retrace. Although the interconnect 132 is shown as being connected to the line conductor 124 as a bump on the conductor (BOL)' the interconnect may also be formed over the bump on the substrate (four) 'which has the same dimensions as the die bump pad 122 An order of magnitude or larger. An optional primer fill material 138 is deposited between the semiconductor crystal & 12 and the substrate 130. In applications with high wire density, it is desirable to minimize the escape spacing of the line conductors 124. The escape spacing between the line guides and lines 124 can be reduced by eliminating the blister mask for reflow restrictions, i.e., by rubbing the bump material under the no-solder mask. A solder mask 14() may be formed over the portion of the substrate m. However, the tantalum mask 14 is not formed over the substrate bump pads 126 of the line conductors 124 for reflow restrictions. In other words, the portion of the wire conductor 124 that is designed to mate with the bump material does not have any SR0 of the solder mask. Since no SR0 is formed around the die bump 塾122 or the substrate bump pad 126, the line wire m can be formed with a fine pitch, that is, the line wire m can be set to be closer to a 201227901 or疋 is closer to the nearby structure. Under the solderless mask 14 ,, the spacing between the line conductors 124 is given as p = D + pLT + w / 2, where d is the interconnected substrate diameter ' PLT is the die set tolerance, and w is the line Width of Wire 124 In one embodiment, given the bump base diameter of 丨〇〇μηη, the PLT of 1 and the line width of 30 μm, the minimum escape pitch of line conductor 124 is 125 μm. The solder-free bump formation eliminates the need for tape spacing, SRT, and minimum resolvable SR〇 of the solder mask material between adjacent openings as seen in the prior art. When the bump material is reflowed without a solder mask to metallurgically and electrically connect the die bump pads 122 to the substrate bump pads 126, wetting and surface tension are such that the bump material remains self-contained and It is held in the space between the die bump pad 1 22 and the substrate bump pad 126 and the substrate 13 紧邻 in the immediate vicinity of the line conductor 124 and substantially in the coverage area of the bump. In order to achieve the desired self-limiting nature, the bump material may be immersed in a solubilizing solvent prior to being placed on the die bump pad 122 or the substrate bump pad 126 to selectively cause the bump material to be The area of contact is more humid than the area around the line conductor 124. The molten bump material is maintained confined within the area substantially defined by the bump pads due to the wettability of the fluxing solvent. The bump material does not spill into the less humid areas. A thin oxide layer or other insulating layer can be formed over the area where the bump material is not intended to make the area less humid. Therefore, there is no need for a solder mask 140 around the die bumps 12 2 or the substrate bump pads 126. In another embodiment, a composite interconnect 144 is formed between the die bump pads 122 and the substrate bump pads 126 to achieve the desired bump material 17 201227901 self-limiting. The composite interconnect 144 includes a non-shockable substrate 146 made of cu, Au, ruthenium, and pb, and a fusible cover M8 made of solder, Sn, or copper, as in the circle 8. Shown. The amount of soluble bump material relative to the non-glazable substrate material is selected to ensure self-limiting by surface tension. During reflow, the fusible base material is self-constrained around the 4 non-fusible base material. The fusible bump material around the insoluble substrate also maintains the grain placement during reflow. Generally. The height of the composite interconnect 144 is the same as or smaller than the diameter of the bump. In some cases, the height of the composite interconnect 144 is greater than the diameter of the interconnect. In an embodiment, given a bump base diameter of (10)_, the non-tetrazed substrate 146 is approximately 45 μηη in height, and the soluble cap 148 is approximately 35 μηη in height. The molten bump material is maintained Substantially limited to the area defined by the bump pads, since the amount of bump material deposited to form the composite bumps 144 (including the non-fusible substrate 146 and the fusible i Μ 8) is selected such that The surface tension is sufficient to substantially retain the bump material within the footprint of the bump pad and to avoid spilling into undesired adjacent or nearby regions. Therefore, the solder mask 140 is not required around the die bump pad 122 or the substrate bump pad 26, which reduces the line conductor pitch and increases the wire density. Figures 9a and 9b depict top and cross-sectional views of another embodiment of a flip chip type semiconductor die 150 having a die bump pad i52. Similar to Figures 7a and 7b, the line conductor 154 is a straight conductor having an integral bump pad 156 formed on a substrate or pcB 16A. In this embodiment, the bump pads 156 are configured in a plurality of columns or offset columns. Thus, the alternating line 18 201227901 way conductor 154 includes an elbow for winding to the bump pad 156. The conductive bump material is deposited on the die bump 塾M2 or the substrate bump pad 156 by an evaporation, electrolytic plating, electroless plating, ball dropping or screen printing process. The bump material may be an arsenic, a dysprosium, a Δ-, a solder, and a combination thereof having an optional fluxing solvent. For example, the bump material can be a eutectic, high lead solder or a lead free solder. The bump material is bonded to the die bump pad 152 and the substrate bump pad 156 using a suitable attachment or bonding process. In a real example, the & block material system II is reflowed by heating the material beyond its refining point to form bumps or interconnects 162. In some applications, interconnect 162 is subjected to secondary reflow to improve electrical contact between die bump pads 152 and substrate bump pads 156. The bump material around the narrow substrate bump (four) 156 retains the beta of the aa pellet during reflow. Although the mutual $i 62 is shown as being connected to the line conductor 1 54 and is BOL, the & block material may also be reflowed over the bump 上 on the substrate (10), which is of the same order of magnitude as the die bump pad 152 or It is a larger area. An optional primer fill material 168 is deposited between the semiconductor die 150 and the substrate 160. Minimizing the escape spacing is desirable in applications where the winding density is applied. In order to reduce the spacing between the line conductors 154, the bump material is reflowed under a protective mask. The escape spacing between the line conductors 154 can be reduced by eliminating the solder mask for solder reflow restrictions, i.e., by reflowing the bump material under a solder free mask. A solder 17 can be formed over the portion of the substrate 16G. ^, the solder mask is not formed on the substrate bumps (4) 156 of 19 201227901 of the line conductors 154 for solder reflow restrictions. In other words, the portion of the line conductor 1 54 that is designed to mate with the bump material does not have the SRO of the solder mask 170. Since no sr〇 is formed around the die bump pad 152 or the substrate bump pad 156, the line wires 154 can be formed with a fine pitch, that is, the line wires 54 can be disposed adjacent to each other. structure. The spacing between the line conductors 154 under the solderless mask 170 is given as P = D/2 + PLT + W/2 , where D is the base diameter of the bumps 162, pLT is the grain set tolerance, and W Is the width of the line conductor 1 54. In one embodiment, 'giving a bump diameter of 1〇〇μηι, a PLT of ι〇μη, and a line line width of 3〇μηι, the minimum escape pitch of the line conductor 154 is 75μπ^ the bump of the solderless mask The block formation eliminates the need to consider the hole spacing, Srt, and minimum resolvable SRO of the solder mask material between adjacent openings as seen in the prior art. When the bump material is reflowed under a solderless mask to metallurgically and electrically connect the die bump pads 52 of the semiconductor die 150 to the substrate bump pads 156 of the wire bond 54, wetting and surface tension The bump is self-contained and remains in the portion of the die bump pad 52 and the substrate bump pad 56 and the substrate 160 that is adjacent to the line conductor 54 and substantially in the footprint of the bump pad. Within the space between the shares. In order to achieve the desired self-limiting nature, the bump material may be immersed in a fluxing solvent prior to being placed on the die bump pad 152 or the substrate bump pad 156 to selectively cause the bump material to be selected. The area contacted is more humid than the area around the line conductor 154. Due to the wettability of the fluxing solvent, the molten bump material remains substantially confined within the area defined by the bump pad boundary 20 201227901. The bump material does not spill into the less humid areas. — A thin oxide layer or other insulating layer can be formed over the area where the bump material is not intended to make the area less humid. Therefore, a tantalum mask 17 is not required around the die bump pad m or the substrate bump 156. In another embodiment, a composite interconnect is formed between the die bumps 152 and the substrate bump pads 156 to achieve the desired self-limiting bump material. Similar to Figure 8, the composite interconnect comprises a non-refinable substrate made of CU, Au, such as, state or Pb, and a fusible cover made of solder, solder or solder. The height or amount of the intumescent bump material (4) at the insoluble substrate material is selected to ensure self-limiting by surface tension. The soluble substrate material is self-contained around the non-fusible substrate material during reflow. The fusible bump material around the non-fusible substrate also maintains the placement of the grains during reflow. In general, the height of the composite is the same as or smaller than the diameter of the bump. In some cases, the height of the composite interconnect is greater than the diameter of the interconnect. In the embodiment - the bump substrate of 1 () is given a direct control, the infusible substrate is about 45 μm in the scent, and the fusible cover is about 35 μm in height! The molten bump material maintains substantial confinement in the region defined by the bumps because of the amount of bump material deposited to form the composite bumps (including = fusible substrate and fusible cover) It is selected such that the resulting surface tension is sufficient to substantially retain the bump material within the footprint of the bump pad and to avoid spilling into undesired adjacent or nearby regions. Therefore, no solder mask 170 is required around the die bump pad 152 or the substrate bump pad 156, which reduces the line conductor pitch and increases the wire density. 21 201227901 Figure 1 0 15 is a description of embodiments having various interconnect structures that can be applied to the sr〇-free interconnect structure as described in Figure 6.9. - For example, a "substrate (4) 222 of "cutting, gallium, conformation, or carbon cut" is provided for the structural (four) semiconductor wafer 220. A plurality of semiconductor dies or members, also referred to as 224, are formed on wafer 22 and separated by scribe lines 226 as described above. Figure i〇b shows a cross-sectional view of a portion of a semiconductor wafer 22A. The mother semiconductor wafer 224 has a back surface 228 and an active surface 23A including an analog or digital circuit implemented to be formed within the die and electrically interconnected according to electrical design and function of the die Active device, passive device, conductive layer and dielectric layer. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in the active surface 23A to implement analog circuits or digital circuits such as digital signal processors (DSPs), ASICs, memories, or Other signal processing circuits. Semiconductor f-particles 224 may also include integrated passive devices (IpD), such as inductors, capacitors, and resistors, for use in RF signal processing. In the embodiment, the semiconductor die 224 is a flip chip type semiconductor die. - Conductive layer 232 is formed over active surface 230 by pVD, CVD, electroplating, electrowinning, or other suitable metal deposition process. The conductive layer 232 may be A, Cu, Sn, Ni, Au,

Ag, or one or more layers of other suitable electrically conductive materials. The conductive layer operates to electrically connect to the contacts on the active surface, or the contacts of the crystal or the pad. Figure 10c shows a portion of a semiconductor wafer 220 having an interconnect structure 22 201227901 formed over a contact pad 232. A conductive bump material 234 is deposited over the contact pads 232 by a vapor deposition, electrolytic plating, electroless plating, ball dropping, or screen printing process. The bump material 234 can be A, Sn, Ni, Au, Ag, Pb, Bi, C:u, solder, and combinations thereof, with an optional fluxing solvent. For example, bump material 234 can be eutectic Sn/Pb, high lead solder or lead free solder. The bump material 234 is substantially compliant and undergoes plastic deformation greater than about 25 μηη under a force corresponding to a vertical load of about 2 gram. The bump material 234 is bonded to the contact pads 232 by a suitable attachment or bonding process. For example, bump material 234 can be compression bonded to contact pad 232. The bump material 234 can also be reflowed by heating the material beyond its melting point to form a ball or bump 236, as shown in Figure 1〇d. In some applications, the bumps are soldered twice to improve the electrical connection to the contact pads 232. The bump 2% represents a type of interconnect structure that can be formed over contact pads 232. The interconnect structure can also use stud bumps, microbumps, or other electrical interconnects. Figure 1A shows another embodiment of an interconnect structure formed by a composite bump 238 over a contact pad 232 that includes a non-meltable or indecomposable portion 240 and a fusible or Decomposable part 242. The fusible or decomposable trait and the non-meltable or non-decomposable trait are defined for the bump 238 with respect to the reflow condition. The non-meltable portion "o may be Au, Cu, Ni, high lead solder, or a lead tin alloy. The fusible:: part 242 may be Sn, a lead-free alloy, a Sn_Ag alloy °n-Ag- Cu alloy, Sn-Ag-copper (ln) alloy, eutectic solder, tin and Ag, Cu or alloy, or other relatively low temperature melting solder. In the embodiment, give: 23 201227901 a contact pad 232 The width or diameter of the 不可μιη, the non-meltable portion 24 is about 45 μm and the fusible portion 242 is about 350 claws. Figure 1〇f shows another embodiment of the interconnect structure, which is formed Above the contact pad 232 is a bump 244 over the conductive post 246. The bump 244 is fusible or decomposable, and the conductive post 246 is non-meltable or non-decomposable. The fusible or decomposable trait and The non-meltable or non-decomposable properties are defined in relation to the reflow conditions. The bumps 244 may be Sn, lead-free alloys,

Sn-Ag alloy, Sn-Ag-Cu alloy, Sn-Ag-In alloy, eutectic solder, alloy of tin and Ag, Cu or Pb, or other relatively low temperature melting solder. The conductive pillars 246 may be Au, Cu, Ni, high lead solder, or lead tin alloy. In one embodiment, the conductive pillar 246 is a Cu pillar and the bump 244 is a solder cap. Given the width or diameter of a contact pad 232 ΙΟΟμπι, the height of the conductive post 246 is approximately 45 μm, and the height of the bump 244 is approximately 35 μm. FIG. 1 shows another embodiment of an interconnect structure formed over bump 232 and having bump material 248 having an aperture 250. Similar to bump material 234, bump material 248 is soft and deformable under reflow conditions 'has low yield strength and high elongation to failure»bumps 250 It is formed by surface treatment of the electric ore and is shown exaggerated in the drawings for the purpose of illustration. The level of the bumps 250 is typically on the order of about 1-25 μm. The bumps may also be formed on the bumps 236, the composite bumps 238, and the bumps 244. In FIG. 10h, the semiconductor wafer 220 is individually diced into individual semiconductor dies 224 through a dicing street 226 using a saw blade or laser cutting tool 252. 201224 201227901 FIG. 1a shows a substrate or PCB 254 having conductive lines 256. » The substrate 254 can be a single sided FR5 laminate or a double sided BT-resin laminate. The semiconductor die 224 is arranged such that the bump material 234 is aligned with the interconnect locations on the conductive traces 256, see Figures i9a-19g. Alternatively, bump material 234 can be aligned with conductive pads or other interconnect locations formed on substrate 254. The bump material 234 is wider than the conductive traces 256. In one embodiment, the bump material 234 has a width less than ΙΟΟμηι for a bump pitch of 150 μm, and the conductive trace or pad 256 has a width of 35 μm. Conductive lines 256 can be applied to the SRO-free interconnect structure as described in Figures 6-9. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 234 over the conductive traces 256. This force F can be applied at a high temperature. Due to the compliant nature of the bump material 234, the bump material deforms or protrudes around the top and side surfaces of the conductive trace 256 and is referred to as BOL. In particular, at a force f corresponding to a vertical load of about 2 gram, the application of pressure causes the bump material 234 to undergo plastic deformation greater than about 25 μm and cover the top and side surfaces of the conductive trace, as in Figure lib Shown in it. The bump material 234 can also be metallurgically connected to the conductive traces 256 by physically contacting the bump material with the conductive traces and then reflowing the bump material at a reflow temperature. By making the conductive traces 256 narrower than the bump material 234, the pitch of the conductive traces can be reduced to increase the filament density and the number of turns. The narrower conductive traces 256 reduce the force F required to deform the bump material 234 around the conductive traces. For example, the necessary force F may be such that the bump material abuts 30 to 50% of the convexity 25 201227901. smaller

Dynamic or grain floating. The force pressure F required for the deformation of the conductive material or the pad of the block material is fine-spaced interconnect and small grain dimension 4 coplanarity and uniform Z-direction deformation; 5 ancient Figure 11c shows the formation of semiconductor grains A bump 236 over the contact pad 232 of 224. The semiconductor die 224 is arranged to align the bumps 236 with the interconnect locations on the conductive traces 256. Alternatively, the bumps 236 can be aligned with conductive turns or other interconnect locations formed on the substrate 254. Bump 236 is wider than conductive line 256. Conductive lines 256 can be applied to the SRO-free interconnect structure as described in Figure 6-9. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bumps 236 onto the conductive traces 256. This force ρ can be applied at a high temperature. Due to the compliant nature of the bumps 236, the bumps deform or protrude around the top and side surfaces of the conductive traces 256. In particular, the application of pressure causes the bump material 236 to plastically deform and cover the top and side surfaces of the conductive traces 256. Bumps 236 can also be metallurgically connected to conductive traces 256 by physically contacting the bumps with the conductive traces at reflow temperatures. By making the conductive traces 256 narrower than the bumps 236, the spacing of the conductive traces can be reduced to increase the winding density and the number of I/Os. The narrower conductive traces 256 reduce the force F required to deform the bumps 236 around the conductive traces. For example, the necessary force F may be 30-50% of the force required to deform a bump against a conductive line or pad that is wider than the bump. The lower pressure F is useful for 26 201227901 fine pitch interconnects and small die retention in a single-capacity tolerance and for achieving uniform Z-direction deformation and high reliability interconnect bonding. In addition, deforming the bump 236 around the conductive line 256 mechanically locks the bump to the line to avoid grain movement or grain floating during reflow. FIG. Composite bumps 238 on the contact pads of the particles 224. The semiconductor die 224 is arranged such that the composite bumps 238 and the interconnect locations on the conductive traces 256 are aligned. Alternatively, the composite bumps 238 can be aligned with conductive pads or other interconnect locations formed on the substrate 254. The composite bumps 238 are wider than the conductive traces 256. The conductive traces 256 are (4) unconnected structures as described in @6_9. A pressure or force F is applied to the back surface of the semiconductor die 224 to press the refinable portions 42 onto the conductive traces 256. This force F can be applied at high temperatures. Due to the compliant nature of the fusible material 242, the fusible portion is deformed or protruded around the top surface and the side surface of the guide rails, and the pressure is applied to make the stunable portion 242 is plastically deformed and covers the top surface and the side surface of the conductive line % 256. The composite bump = 8 can also be delayed to the conductive trace 256 by metallurgical remote 5 i by contacting the fusible portion with the conductive trace at the reflow temperature. The non-fusible portion 240 does not melt or deform during application of pressure or temperature, and maintains its height and shape as perpendicular to one of the semiconductor die 224 and the substrate 254. The additional displacement between the bobbin day granule 224 and the substrate 254 provides a greater coplanar tolerance between the mating surfaces. A large number (e.g., 201227901, if thousands) of composite bumps 238 on the semiconductor die 224 during the reflow process are attached to interconnect locations on the conductive traces 256 of the substrate 254. Some of the bumps 238 may not be properly connected to the conductive traces 256, particularly when the die 224 is twisted. Recall that the composite bump 238 is wider than the conductive trace 256. Under application of a suitable force, the smectible portion 242 is deformed or protrudes around the top and side surfaces of the conductive trace 256 and mechanically locks the composite bump 238 to the conductive trace. The mechanical tight connection is formed by the nature of the fusible portion 242, which is softer and more compliant than the conductive trace 250, and thus deforms over the top surface of the tantalum conductive trace and over the conductive trace Around the side surfaces to obtain a larger contact surface area. The mechanical tight connection between the composite bumps 238 and the conductive traces 256 maintains the bumps on the conductive traces during reflow, i.e., the bumps and conductive traces do not lose contact. Thus, the mating bump 238 is coupled to the conductive trace 256 to reduce the bump interconnect failure. 1 shows the conductive pillars 246 and bumps 244 formed over the contact pads 232 of the semiconductor die 224. Semiconductor die 224 is positioned to align bumps 244 with interconnect locations on conductive traces 256. Alternatively, bumps 244 can be aligned with conductive pads or other interconnect locations formed on substrate 254. Bumps 244 are wider than conductive lines 256. Conductive lines 256 can be applied to the SRO-free interconnect structure as described in Figures 6-9. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bumps 244 onto the conductive traces 256. This force F can be applied at high temperatures. Due to the compliant nature of the bumps 244, the bumps deform or protrude around the top and side surfaces of the conductive traces 256. In particular, the application of pressure 28 201227901 adds plastic deformation of the bumps 244 and covers the top and side surfaces of the conductive traces 256. Conductive posts 246 and bumps 244 may also be metallurgically connected to conductive traces 256 by physically contacting the bumps with the conductive traces at a reflow temperature. The conductive post 246 does not smear or deform during application of pressure or temperature and maintains its height and shape to become a vertical gap between the semiconductor die 224 and the substrate 254. This additional displacement between semiconductor die 224 and substrate 254 provides a greater coplanar tolerance between the mated surfaces. The wider bumps 244 and the narrower conductive traces 256 have similar low pressure and mechanical locking characteristics and advantages as described above for the bump material 234 and the bumps 236. Figure 11f shows bump material 248 with bumps 250 formed over contact pads 232 of semiconductor die 224. Semiconductor die 224 is disposed such that bump material 248 is interconnected on conductive trace 256. alignment. Alternatively, the bump material 248 can be aligned with conductive pads or other interconnect locations formed on the substrate 254. The bump material 248 is wider than the conductive trace 256. A > 1 force or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 248 onto the conductive trace 256. This force F can be applied at high/inside. Due to the compliant nature of the bump material 248, the bumps are deformed or canineed around the top and side surfaces of the conductive traces 256. In particular, the force of the force is such that the bump material 248 is plastically deformed and covers the top and side surfaces of the conductive line 256. In addition, bumps 250 are metallurgically connected to conductive traces 256. The size of the bumps 250 is of the order of about 1-25 μm. Figure 11g shows the substrate or PCB 258 having an angled or sloped side 29 201227901 side trapezoidal conductive line 260. A bump material 261 is formed over the contact pads 232 of the semiconductor wafer 224. The semiconductor die 224 is arranged to align the bump locations on the bump material 261 and the conductive traces 260. Alternatively, the bump material 261 can be aligned with conductive pads or other interconnect locations formed on the substrate 258. The bump material 261 is wider than the conductive trace 260. Conductive line 260 can be applied to an SR-free interconnect structure as described in Figures 6-9. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 261 over the conductive traces 26A. This force F can be applied at a high temperature. Due to the compliant nature of the bump material 261, the bump material deforms or protrudes around the top and side surfaces of the conductive traces 26A. In particular, the application of pressure causes the bump material 261 to be plastically deformed under force F to cover the top surface of the conductive trace 260 and the inclined side surface. The bump material 261 can also be metallurgically bonded to the conductive traces 260 by physically contacting the bump material with the conductive traces and then reflowing the bump material at a reflow temperature. Figures 12a-12d show a BOL embodiment of a semiconductor die 224 and a bump 262 having an infusible or indecomposable portion 264 and a fusible or decomposable portion 266. The non-meltable part can be made of Au, Cu, Ni, high lead solder, or lead-tin alloy. The fusible portion 266 can be Sn, a shipless alloy, a Sn_Ag alloy, a SnAg core =, a Sn-Ag-In alloy, a eutectic solder, an alloy of tin and Ag, Cu or eta, or other relative Low temperature melting solder. The non-fusible portion 264 forms a larger portion of the composite bump 262 than the fusible portion 266. The insoluble portion 264 is attached to the contact boring blade 23 of the semiconductor die 224. The semiconductor die 224 is disposed such that the composite bump 262 is interconnected with the conductive trace 268 formed on the substrate 270. The position is aligned, as shown in Figure 12a. The composite bumps 262 are tapered along the conductive traces 268, i.e., the composite bumps have a wedge shape that is longer along the length of the conductive traces 268 and narrower across the conductive traces. The tapered features of the composite bumps 262 appear along the length of the conductive traces 268. The drawing in Figure 12a shows that the shorter features or the narrowed tapered turns are collinear with the conductive traces 268. The drawing in Figure 12b perpendicular to Figure 12a shows the longer features of the wedge-shaped composite bump 262. The shorter features of the composite bumps 262 are wider than the conductive traces 268. The fusible portion 266 is decomposed around the conductive traces 268 during pressure application and/or by thermal reflow, i.e., as shown in Figures 12c and 12d. The non-fusible portion 264 does not melt or deform during reflow and maintains its shape and shape. The non-fusible portion 264 can be sized to provide a gap distance between the semiconductor die 224 and the substrate 270. A process such as Cu OSP can be applied to the substrate 270. Conductive line 268 can be applied to an SRO-free interconnect structure as described in Figures 6-9. During the retracement process, a large number (e.g., thousands) of composite bumps 262 on semiconductor die 224 are attached to interconnect locations on substrate 270 ❾ conductive traces 268. Some of the crypts 262 can not be properly connected to the conductive traces 268', particularly when the semiconductor die m is distorted. Recall that the composite bump 262 is more conductive than the conductive trace 268t. Under application-appropriate force, the portion 266 of the meta-soluble portion is deformed or protruded around the top surface and the side surface of the conductive line 268' and mechanically locks the composite convex i-ghost 262 to the 31 201227901 conductive line. The S-mechanical tight connection is formed by the nature of the sleek portion 266, which is softer and more compliant than the conductive trace 268, and thus deforms around the top and side surfaces of the conductive trace to obtain Large contact area. The wedge shape of the composite bump 262 increases the contact area between the bump and the conductive trace, for example, increasing along the longer characteristic of Figures 12b and 12d without sacrificing the shorter along Figures 12a and 12c. The spacing of the features in the direction. The mechanically tight connection between the composite bumps 262 and the conductive traces 268 maintains the bumps on the conductive traces during reflow, i.e., the bumps and conductive traces do not lose contact. Thus, the composite bumps 262 that are coupled to the conductive traces 268 reduce the failure of the bump interconnects. Figures 13a-13d show a BOL embodiment of a semiconductor die 224 in which bump material 274 is formed over contact pad 232, similar to Figure 10c. In Figure 13a, the bump material 274 is substantially conformable and undergoes a plastic deformation of greater than about 25 μηη under a force corresponding to a vertical load of about 200 grams. The bump material 274 is wider than the conductive traces 276 on the substrate 278. A plurality of bumps 280 are formed on the conductive traces 276 at an approximate order of magnitude. The semiconductor die 224 is arranged to align the bump locations on the bump material 274 and the conductive traces 276. Alternatively, bump material 274 can be aligned with conductive pads or other interconnect locations formed on substrate 278. - Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 274 over the conductive traces 276 and bumps 28, as shown in Figure 13b. This force F can be applied at high temperatures. Due to the compliant nature of the bump material μ, the bump material is deformed or protrudes around the top and side surfaces of the conductive traces 32 201227901 and the bumps 280. In particular, the application of pressure causes the bump material 274 to plastically deform and cover the top and side surfaces of the conductive traces 276 and the plastic flow of the bumps 28 of the core bump material 274 at the top surface of the bump material and conductive traces 276. A macroscopic mechanical close connection point is created between the side surface and the bump 280. The plastic flow of the bump material 274 occurs around the top and side surfaces of the conductive traces 276 and around the bumps 280, but does not extend excessively over the substrate 278, which can cause electrical shorts and other defects. The mechanical tight connection between the bump material and the top surface and the side surface of the conductive line 276 and the bump 28 系 does not significantly increase the bonding force t, and there is a large contact between the individual surfaces. A strong connection to the area. The mechanical tight connection between the bump material and the top surface and side surfaces of the conductive traces and the bumps 28〇 also reduces lateral grain movement during subsequent processes such as packaging. Figure 1 3c shows an alternative - BOL embodiment in which the bump material 274 is 2% narrower than the conductive trace. Pressure or force is applied to the back surface 228 of the semiconductor die to press the bump material 274 onto the conductive trace 2% and the bump. The force F can be high—'rT 厶/ <chuanbei;! (the essence of 3⁄4' the bump material is deformed or protrudes above the top surface of the conductive line 2% and the bump 280. In particular, the application of pressure The bump material 274 is plastically deformed and covers the top surface and the bump of the conductive trace 276. The plastic flow of the bump material 274 creates a giant between the bump material and the conductive trace 276 = surface and protrusion '280 The mechanical close connection point between the bump material and the top surface of the conductive line 276 and the bump 28 〇 is provided without a significant increase in the bonding force, providing a 33 201227901 individual A robust connection between the surfaces with a large contact area. The mechanical tight connection between the bump material and the top surface of the conductive trace 276 and the bump 28 亦 also reduces lateral grain during subsequent processes such as packaging. Figure 13d shows another embodiment of the POL in which bump material 274 is formed over an edge of conductive trace 276, i.e., a portion of the bump material is over the conductive trace and a portion of the bump Material is not Above the conductive traces, a pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 274 onto the conductive traces 276 and the bumps 28A. The force F can be applied at elevated temperatures. Due to the compliant nature of the bump material 274, the & block material deforms or protrudes above the top and side surfaces of the conductive traces 276 and over the bumps 280. In particular, the application of pressure causes the bump material 274 to be plastically deformed. And covering the top surface and the side surface of the conductive line 276 and the bump 280. The plastic flow of the bump material 274 is a giant mechanical machine between the bump material and the conductive surface 276 (four) surface and the side surface and the bump 28 〇 Tightly connected. The mechanically tight connection between the bump material and the top surface and side surfaces of the conductive traces and the bumps 280 is provided without significantly increasing the bonding force - with individual large contact between the surfaces A robust connection of the area. The mechanical f-bonding between the bump material and the top and side surfaces of the conductive trace 276 and the point of the bump is reduced in the lateral grain shift during subsequent processes such as packaging. 14a-14c show an embodiment of a semiconductor die 224, which is similar to the pattern 丨〇c' bump material 284 formed over the contact pad 232. - the tip 286 is from the bump material 284 The body extends into a stepped projection 34 201227901 block in which the tip 286 is narrower than the body of the bump material 284, i.e., as shown in Figure 14a. The semiconductor die 224 is disposed such that the bump material 284 and the substrate 290 are disposed. The interconnections on the conductive traces 288 are aligned. More specifically, the tips 286 are disposed on the center of the interconnect locations on the conductive traces 288. Alternatively, bump material 284 and tip 286 can be aligned with conductive pads or other interconnect locations formed on substrate 290. The bump material 284 is wider than the conductive traces 288 on the substrate 290. Conductive line 288 is generally compliant and undergoes plastic deformation greater than about 25 [mu]m under a force corresponding to a vertical load of about 2 gram. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the tip 284 over the conductive traces 288. This force F can be applied at high temperatures. Due to the compliant nature of the conductive traces 288, the conductive traces are deformed around the tip 286, as shown in Figure 14b. In particular, the application of pressure causes the conductive traces 288 to plastically deform and cover the top and side surfaces of the tip 286. Figure 14c shows another BOL embodiment in which a circular bump material 294 is formed over contact pads 232. A tip 296 extends from the body of the bump material 294 to form a stud bump, wherein the tip is larger than the body of the bump material 294. The semiconductor die 224 is configured to align the bump material 294 with the interconnect locations on the conductive traces 298 on the substrate 300. More specifically, the tip 296 is disposed on the center of the interconnecting location on the conductive trace 298. Alternatively, bump material 294 and tip 296 can be aligned with conductive pads or other interconnect locations formed on substrate 300. The bump material 294 is wider than the conductive traces 298 on the substrate 300. 35 201227901 Conductive line 298 is generally compliant and undergoes plastic deformation greater than about 25 μηη under a force corresponding to a vertical load of about 2 gram. - A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the tip 296 onto the conductive trace 298. This force F can be applied at high temperatures. Due to the compliant nature of the conductive traces 298, the conductive traces are deformed around the tips 296. In particular, the application of pressure causes the conductive traces 298 to plastically deform and cover the top and side surfaces of the tip 296. The conductive traces described in Figures 11a-11g, 12a-12d and 13a-13d may also be compliant materials as described in Figures 14a-14c. Figures 15a-15b show a BOL embodiment of a semiconductor die 224 in which a bump material 304 is formed over the contact pad 232, similar to Figure 11c. The bump material 304 is substantially conformable' and undergoes a plastic deformation greater than about 25 μπι under a force corresponding to a vertical load of about 200 grams. The bump material 304 is wider than the conductive traces 306 on the substrate 308. A conductive via 310 having an opening 312 and a conductive sidewall 314 is formed through the conductive trace 306, i.e., as shown in Figure 15a, the conductive trace 3 〇 6 can be applied as shown in Figures 6-9. The interconnection structure without SRO is described. The semiconductor die 224 is arranged to align the bump locations on the bump material 304 and the conductive traces 306. See Figures 19a-i9g. Alternatively, bump material 304 can be aligned with conductive or other interconnect locations formed on substrate 308. A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 304 over the conductive traces 306 and into the openings 3 12 of the conductive vias 30. This force f can be applied at high temperatures. Due to the compliant nature of the bump material 304, the bump material is deformed or protruded around the top and side surfaces of the conductive traces 306 and into the opening 312 of the conductive via 310, as in Figure 15b. Shown. In particular, the application of pressure causes the bump material 3〇4 to plastically deform and cover the top and side surfaces of the conductive line 306 and into the opening 312 of the conductive via 31〇. Therefore, the bump material 3〇4 is electrically connected to the conductive traces 3〇6 and the conductive sidewalls 314 for use in the z-direction vertical interconnection through the substrate 3〇8. The plastic flow of the bump material 304 creates a mechanical tight connection between the bump material and the top and side surfaces of the conductive traces 3〇6 and the openings si] of the conductive vias 31〇. The mechanical tight connection between the bump material and the top and side surfaces of the conductive traces and the opening 312 of the conductive via 310 provides a large contact area between the individual surfaces without significantly increasing the bonding force Strong connection. The mechanical tight connection between the bump material and the top and side surfaces of the conductive traces 306 and the openings of the conductive vias 31 also reduces lateral grain movement during subsequent processes such as packaging. Since the conductive via 31 and the bump material 3〇4 are formed together within the interconnection position, the total substrate interconnection area is reduced. In the BOL embodiments of FIGS. 11a-Ug, -(3), 13a_13d, 14a_Uc&A -, by making the conductive lines narrower than the interconnect structure, the pitch of the conductive lines can be reduced to increase the wire density and the number of 1/0. . A narrower conductive path reduces the force required to deform the interconnect structure around the conductive trace. For example, the necessary force F may be such that a bump abuts a conductive line or pad that is wider than the four. The required force is 3〇·5〇%. The lower pressure F is useful for fine-pitch interconnects and small-grain coplanarity within a finger-to-tolerance tolerance and for achieving uniform slanting deformation and high reliability interconnect combinations. Deforming the interconnect structure around the conductive trace mechanically locks the bump to the trace to avoid grain movement or grain floating during reflow. Figures 16a-16c illustrate a mold underfill (MUF) process to deposit the package material > around the bumps between the semiconductor die and the substrate. Figure 16a shows the use of the semiconductor die 224! The bump material 234 of lb is mounted to the substrate 254' and is disposed between the upper mold support 316 and the lower mold support 318 of the chase mold 32A. The other semiconductor die and substrate combination of Uaiig, i2ai2d, 13a-1 3d, 14a-14c and 15a-15b may also be disposed on the upper mold support 316 and the lower mold support 318 of the groove mold 32A. between. The upper mold leg 316 is comprised of a compressible leaving film 322. In Figure 16b, the upper mold support member 316 and the lower mold support member 318 are placed together to enclose the semiconductor die 224 and the substrate 254 having an open space over the substrate and between the semiconductor die and the substrate. between. The shrinkable release film 322 is bonded to the back surface and the side surface of the semiconductor die 224 to block the formation of the encapsulating material on the surface. The liquid-filled package material is infused into the mouth 326. In the side of the groove mold 320, an optional vacuum assist 328 draws from the opposite sides, the encapsulating material fills evenly into the open space above the substrate 254, and the opening between the semiconductor die 224 and the substrate 254. space. The encapsulating material β, a ruthenium polymer composite (for example, an epoxy acrylate having a filler of epoxy resin γ2 with a filler), or a polysiloxane having a suitable filler. The encapsulating material 324 is non-conductive and environmentally protected. The conductor device is protected from external elements and contaminants. The compressible material 322 prevents the encapsulating material 324 from flowing over the back surface of the semiconductor die 224 and around the side surfaces. The encapsulating material 324 is cured. The back surface 228 and side surfaces of the semiconductor wafer 224 remain exposed from the package material η#. Figure 16c shows an embodiment of MUF and overfilling of the mold (centangles 1?), i.e., without the compressible material 322. The semiconductor die 224 and the substrate 254 are disposed between the upper mold support and the lower mold support 318 of the groove mold 32A. The upper mold support 3i6 and the lower wedge support 3 18 are placed together to enclose the semiconductor die 224 and the substrate 254 having an open space above the substrate, around the semiconductor die, and Between the semiconductor die and the substrate. The encapsulating material 324 in a liquid state is injected into the - side of the groove mold 320 by the nozzle 326, and an optional vacuum assist 328 is sucked from the opposite side to uniformly fill the encapsulating material in the semiconductor. An open space around the die 224 and above the substrate and an open space between the semiconductor die 224 and the substrate 254. The encapsulating material 324 is cured. Figure π shows another embodiment of depositing an encapsulation material around the semiconductor die 224 and in the gap between the semiconductor die, bit 224 and substrate 254. The semiconductor die 224 and the substrate 254 are surrounded by a barrier ((1) 33 。. The encapsulation material 332 is dispensed from the nozzle 334 into the barrier 33〇 in a liquid state to open the p-bow on the substrate 254· η" η + 丨, 1 叼 valve dime and the open space between the semiconductor die 224 and the substrate 254. The amount of encapsulation material dispensed from the nozzle 334 is controlled to cover the back of the semiconductor crystal 'grain 224 The surface 228 or the side surface is filled under the barrier 33G. The encapsulation material 332 is cured. 39 201227901 Figure 18 shows the semiconductor die 224 and the substrate 254 after the MUF process of Figures 16a, 16c and 17. The encapsulation material 324 is evenly Between the substrate 254 and the bump material 234 between the semiconductor die 224 and the substrate 254. Figures 19a-1 9g show top views of various conductive trace layouts on the substrate or PCB 340. Figure 19a The conductive trace 342 is a conductor formed on the substrate 340 having an integral bump pad or interconnect location 344. The sides of the substrate bump pad 344 may be collinear with the conductive traces 342. Conventional techniques Medium, a solder alignment opening (SR0) is usually Was formed over the interconnect location to limit the bump material during reflow. The Sr〇 increases interconnect spacing and reduces the number of I/Os. In contrast, the mask layer 346 can be formed on a portion of the substrate 340. Above; however, the mask layer is not formed around the substrate bump pads 344 of the conductive traces 342. In other words, the portions of the conductive traces 342 that are designed to mate with the bump material are not originally used in Any SRO of the bump-limited mask layer 346 during reflow. The semiconductor aB particles 224 are disposed over the substrate 340, and the bump material is aligned with the substrate bump 344. The bump material is consumed by the bump material Contacting the bump pad body and then reflowing the bump material for electrical and metallurgical bonding to the substrate bump pad 344 at a reflow temperature. In another embodiment, a conductive bump material utilizes an evaporation An electrolysis electric clock, an electroless electric key, a ball drop or screen printing process is deposited on the substrate bump pad 344. The bump material may be

Au Ag, Pb, B!, Cu, solder, and combinations thereof, have an optional fluxing solvent. For example, the bump material can be a eutectic _, a high lead solder 40 201227901 material, or a shipless solder. The bump material # &丨_ λ. τ τ 寸 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你 你In an embodiment, the bump material is soldered back and forth by heating the material beyond its melting point to form bumps or interconnects 348, as shown in Figure 19b. In some applications, bumps 348 are subjected to secondary reflow to change the electrical contact to the substrate bumps. The bump material around the narrow substrate bump pad 344 maintains the position of the die during reflow. In applications with high wire density, it is desirable to minimize the escape spacing of the conductive traces 342. The escape spacing between the conductive traces 342 can be reduced by eliminating the masking layer for reflow soldering purposes, i.e., by soldering the bump material without the mask layer. Since no SR is formed around the die bump pad 232 or the substrate bump pad 344, the conductive traces 342 can be formed with a fine pitch, that is, the conductive traces 342 can be placed closer together or Close to the nearby structure. Below the substrate bump pad 344, there is no SRO, and the spacing between the conductive lines 342 is given as P = D + PLT + W / 2 ' where D is the base diameter of the bump 348, and plt is the die set tolerance' And W is the width of the conductive line 342. In one embodiment, given the bump base diameter of ΙΟΟμιη, the PLT of ΐ〇μπι, and the line width of 30 μm, the minimum escape pitch of the conductive trace 342 is 125 pm. The maskless bump formation eliminates the need to consider the hole spacing of the mask material between adjacent openings as seen in the prior art, solder mask alignment tolerance (SRT), and minimally resolvable SRO. When the bump material is reflowed without the mask layer to metallurgically and electrically connect the die bump pads 232 to the substrate bump pads 344, the wetting and surface tension system 41 201227901 maintains the bump material self-limiting And being held in the space between the die bumps 232 and the substrate bump pads 344 and the portions of the substrate 340 that are in close proximity to the conductive traces 342 and substantially in the footprint of the bump pads. To achieve the desired self-limiting nature, the bump material can be immersed in a fluxing solvent prior to placement on the die bumps 232 or substrate bump pads 344 to selectively cause the bump material to The area of contact is more wet than the area around the conductive line 34. The refining bump material is maintained confined to a region substantially defined by the bump pads due to the wettability of the fluxing solvent. The bump material does not spill into the less humid areas. A thin oxide layer or other insulating layer may be formed over the area where the bump material is not intended to make the area less humid. Therefore, there is no need for a mask layer 34〇 around the die bump pad 2 3 2 or the substrate bump pad 344. Figure 19c shows another embodiment in which parallel conductive traces 352 are straight conductors, wherein an integral rectangular bump pad or interconnect location 354 is formed on substrate 350, similar to Figure 7b. In this example, the substrate bump pads 354 are wider than the conductive traces 352, but less than the mating bump width. The sides of the substrate bump pads 3m may be parallel to the conductive traces 352. The mask layer 356 can be formed over a portion of the substrate 350; however, the mask layer is not formed around the substrate bump pads 354 of the conductive traces 352. In other words, the portion of the conductive trace 352 that is designed to mate with the bump material does not have any sr turns that would otherwise be used for the bump layer 356 that was bump-limited during reflow. Figure 19d shows another embodiment of conductive traces 36A and 362 arranged in an array of a plurality of columns, wherein an offset integral bump pad or interconnect location 364 is formed over substrate 366 for maximum interconnection. The escaped winding is 42 201227901 degrees and capacity. The alternating conductive traces 360 and 362 comprise an elbow for winding to the bump 364. The side layer of each substrate bump 364 and the conductive lines 360 and 362 are collinear. The mask layer 368 can be formed over a portion of the substrate 366. However, the mask layer 368 is not formed on the conductive line 360. And the periphery of the substrate bump 364 of 362. In other words, the portions of conductive traces 360 and 362 that are designed to mate with the bump material do not have any SR turns that would otherwise be used for bump-limited masking 368 during reflow. Figure 19e shows another embodiment of conductive traces 370 and 372 arranged in an array of a plurality of columns, wherein an offset integral bump pad or interconnect location 374 is formed over substrate 376 for maximum interconnection Dispersed Winding Density and Capacity The alternating conductive lines 37A and 372 comprise an elbow for winding to the bump pad 374. In this example, the substrate bump pads 374 are circular and wider than the conductive traces 370 and 372, but less than the width of the mating interconnect bump material. A mask layer 378 can be formed over a portion of the substrate 376, however, the mask layer 378 is not formed around the substrate bump pads 374 of the conductive traces 37A and 372. In other words, the portions of the conductive traces 37A and 372 that are designed to mate with the bump material do not have any of the mask layers 378 that would otherwise be used for bump limiting during reflow. Figure 19f shows the conductive traces 38 and 382 in an array of multiple columns, and the integrated bump pads or interconnect locations 384 that are biased in another embodiment are formed on the substrate 386 for maximum mutual The winding density and capacity of Lian Yi San. The alternating conductive lines & 382 comprise an elbow for winding to & block 384. In this example, the substrate bumps 384 are rectangular and wider than the conductive traces 38...82, but less than the width of the mating interconnect bumps 43 201227901 block material. Mask layer 388 can be formed over a portion of substrate 386, however, mask layer 388 is not formed around substrate bump pads 384 of conductive traces 38A and 382. In other words, the portions of the conductive traces 38A and 382 that are designed to mate with the bump material do not have any SR0 that would otherwise be used for the bump layer 388 that was bump-limited during reflow. As an example of an interconnect process, semiconductor die 224 is disposed over substrate 366 and bump material 234 is aligned with substrate bump pad 364 of Figure 19d. The bump material 234 is pressed by the bump material or by the bump material and the bump as described in FIGS. 11a-llg, 12a-12d, 13a-13d, 14a-14c, and 15a-15b The pad is in physical contact and then reflowed to the bump material at a reflow temperature for electrical and metallurgical bonding to the substrate bump pad 364. In another embodiment, a conductive bump material utilizes an evaporation, electrolysis A process of electroplating, electroless plating, ball dropping or screen printing is deposited over the substrate bump pads 364. The bump material may be Ba Bu Sn ' Ni,

Au, Ag' Pb, Bi, Cu, solder, and combinations thereof have an optional fluxing agent T. For example, the bump material can be eutectic Sn/pb, high lead solder, or error free solder. The bump material is bonded to the substrate bump pad 364 by a suitable attachment or bonding process. In one embodiment, the bump material: is reflowed by the addition of the material beyond its dazzle to form bumps or interconnects 390, as shown in Figure 19g. In some applications, the bumps are subjected to secondary reflow to improve the electrical contact to the substrate bumps (10). The narrow bumps (4) 364 around the bumps are maintained in the back: grain placement. Bump material 234 or bumps 390 may also be formed on the substrate bump pad configuration of Figure 2: 201227901. In high wire density applications, it is desirable to minimize the escape spacing of the conductive traces 360 and 362 of Figures 19a-9g or other conductive trace configurations. The escape spacing between the conductive traces 360 and 362 can be reduced by eliminating the masking layer for reflow soldering purposes, i.e., by reflow solder bump material without the mask layer. Since no SRO is formed around the die bump pad 232 or the substrate bump pad 364, the conductive traces 36 and 362 can be formed with a fine pitch, that is, the conductive traces 36 and 362 can be placed relatively Together or closer to the nearby structure. Below the substrate bump pad 364, there is no SRO, and the spacing between the conductive lines 360 and 362 is given as P = D / 2 + PLT + W / 2, which is the base diameter of the bump 390, and the PLT is crystal. The particles are set to tolerance and W is the width of conductive lines 360 and 362. In the conventional example, the bump base diameter of 1 ΟΟ μηη, the PLT of 1 μm, and the line width of 30 μm are given, and the minimum escape pitch of the conductive lines 36 〇 and 362 is 125 μm. The maskless bump formation eliminates the need to consider the aperture spacing, SRT, and minimum resolvable SRO of the masking material between adjacent openings as seen in the prior art. When the s-bump material is reflowed without the mask layer to metallurgically and electrically connect the die bumps 232 to the substrate bump pads 364, the wetting and surface tension are such that the bump material remains self-contained and It is held in the space between the die bump pad 232 and the substrate bump pad 364 and the substrate 366 in the immediate vicinity of the conductive traces 360 and 362 and substantially in the footprint of the bump pad. In order to achieve the desired self-limiting nature, the bump material may be immersed in a flux 45 squirrel pad 232 or substrate bump pad 3 64 to selectively cause the bump to be placed on the die bump pad 232 or the substrate bump pad 3 64. The area in contact with the material is more humid than the area around conductive lines 360 and 362. The molten bump material is maintained confined within the area substantially defined by the bump pads due to the wettability of the fluxing solvent. The bump material does not spill into the less humid areas. A thin oxide layer or other insulating layer may be formed over the area where the bump material is not intended to make the area less humid. Therefore, a mask layer 368 is not required around the die bump pad 332 or the substrate bump pad 364. In Figure 20a, a mask layer 392 is deposited over a portion of conductive traces 394 and 396. However, the mask layer 392 is not formed over the integral bump pad 398. Therefore, each bump pad 398 on the substrate 4 has no SRO. A non-wet mask patch 4 〇 2 is formed on the substrate 4 且 and in the voids in the array of integral bump 塾 298, that is, in adjacent bumps 塾between. The mask patch 402 can also be formed on the semiconductor die 2 24 and in the voids within the array of die bump pads 298. More generally, the 5's mysterious patch patch is formed adjacent to the integral & block in any configuration to avoid spillage into less humid areas. The semiconductor die 224 is disposed over the substrate 4 and the bump material is aligned with the substrate bump pad 398. The bump material is pressed by the bump material or by using the bump material and the bump pad as described in FIGS. 11a-llg, 12a-12d, 13a-13d, 14a-14c, and i5a-15b The bump material is then contacted and then re-welded at a reflow temperature for electrical and metallurgical bonding to the substrate bump pads 398. In another embodiment, a conductive bump material is deposited on the die by a vapor deposition, electrolytic forging, electroless ore, ball drop, or screen printing process 46 201227901 Above the block pad 398. The block material may be Sn Ni Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional fluxing solvent. For example, the bump material may be eutectic Sn/Pb, tantalum lead, or lead-free solder. The bump material is bonded to the integral bump pad 398 using a suitable attachment or bonding process. In a real & example, the bismuth bump material is reflowed by heating the material beyond its melting point to form a ball or bump 4, 4, as shown in the chamber. In some applications, bumps 404 are subjected to secondary reflow to improve electrical contact to body-type bump pads 398. The bumps can also be compression-bonded to the integral bumps 398. Bumps 404 are representative of the type of interconnect structure that can be formed over the body bump pads 398. The interconnect structure can also use stud bumps, microbumps, or other electrical interconnects. Minimizing the escape spacing is desirable in applications where the winding density is applied. In order to reduce the spacing between the conductive traces 394 and 396, the bump material is reflowed without the mask layer around the integral bump pads 398. The escape spacing between the conductive traces 394 and 396 can be achieved by eliminating the mask layer for reflow soldering purposes and the associated SRO around the integral bump pad, that is, by having no mask layer back. Solder bump material is reduced. The mask layer 392 can be formed over portions of the conductive traces 394 and 396 and the substrate 4 away from the integral bump pads 398; however, the mask layer 392 is not formed around the integral bump pads 398. . In other words, the portions of conductive traces 394 and 396 that are designed to mate with the bump material do not have any sr turns that would otherwise be used for bump-limited masking layer 392 during reflow. In addition, the mask patch 402 is formed on the substrate 4〇〇 and integrated in one body.

In the array of the type of bump pads 398, the life in the array is in the work gap. The mask patch 402 is a non-wet material. The mask patch 402 can be thought of. Λ 疋 The same material is not masked 392 and applied during the same processing step, or during different processing steps for different materials. The mask complement "〇2 can be formed by selective oxidation, electric clock, or other treatment of the lines or turns in the array of integrated bumps. The bulk material flows to the body-shaped convex (four) 398 and prevents the conductive bump material from seeping into the adjacent structure. The bump material is covered with a mask provided in the gap of the array of integral bump pads 398>; 2 When reflowing, the wetting and surface tension are such that the bump material is confined and held in the grain bump pad 232 and the integrated bump pad 398 and the substrate 400 in close proximity to the conductive traces 394 and 396 and substantially in the integrated type. In the space between the portions of the footprint of the bump pad 398. To achieve the desired properties, the bump material can be placed before the die bumps t* 232 <-body bumps 塾 398 ± Immersed in a glazing agent to selectively wet the area where the bump material is in contact with the surrounding area of the conductive traces 394 and 396. The molten bump material is due to the wettability of the auxiliaries And the maintenance is limited to the area bounded by the bump pad. The block material does not spill into the less wetted area. An oxide layer or other insulating layer may be formed over the area where the bump material is not intended to make the area less humid. Therefore, the grain convex The mask layer 392 is not required around the block pad 232 or the integral bump pad 398. Since the SRO is not formed around the die bump pad 232 or the integral bump pad 398, the conductive traces 394 and 396 can be thinner. The pitch is formed, that is, the 'conductive line can be set closer to the adjacent structure without contacting 48 201227901 and forming an electrical short. Assuming the same ^ 394 ^ 綷枓 綷枓 alignment design rule, the conductive line

The spacing between 6 is given as the thickness of the base of the D 疋 bump 404, and the w ^ 疋 isoelectric lines 394 and 396 are seen again. In the example, '仏宏1', the diameter of the bump of 10^m and the line width of 20μm, the small escape pitch of the conductive line 394 96 is 65μη. The s-high bump formation system is free of lightning. The θ η luminescence needs to be tested to the hole spacing of the holes of the mask material between adjacent openings as seen in the prior art, and the minimum resolvable SRO 〇 Figure 2i A stacked package (pGp) is shown in which the semiconductor crystal grains are stacked on the semiconductor crystal by using the die attach adhesive 41. The semiconductor die 4 〇 6 and 408 八 丨丨 θ 士 and 408 刀 have an active surface comprising an analog or digital circuit, the analog or digital circuit being implemented to be formed within the die and based on the die Design and function call interconnect active devices, passive devices, conductive layers and dielectric μ. For example, the circuit can include one or more transistors, diodes, and JLs to form a circuit component within the active surface to implement an analog circuit or a digital ray, said .t (W-bit circuit 'eg Dsp, Asic, memory or other signal processing circuit. Lane MH t electric yak conductor dies 406 and 408 may also contain IPDs such as inductors, capacitors and gongs and TTJh electrical states, For use in RF signal processing, the semiconductor die 406 is mounted to form using any of the embodiments of Figures Ua_Ug, ~(3), i3a i3d, 15a-15b, using bump material 416 formed on contact pads 418. Conductive line 412 on substrate 414. Conductive line 412 can be applied to an SRO-free interconnect structure as described in Figure 半导体. The semiconductor die is electrically connected to the contact formed on substrate 414 by wire bonds. 42. The opposite of the bonding wire (2) 49 201227901 is known to be bonded to the contact 塾 4 2 4 on the semiconductor die 4 〇 6. The mask layer 426 is formed over the substrate 414 and the opening exceeds the coverage of the semiconductor die 406 Zone. Although the mask layer 426 is during reflow The bump material 416 is not limited to the conductive traces 412, which can function as a barrier to avoid migration of the encapsulation material 428 to the contact pads 42 or bond wires 422 during the MUF. The encapsulation material 428 is similar to Figure 6a "6c" Deposited between the semiconductor b particles 408 and the substrate 414. The mask layer 426 blocks the muf package material 428 from reaching the junction 42 and the bond wires 422, which may cause defects. The mask layer 426 allows for larger semiconductor grains. The risk is placed on a particular substrate without the encapsulation material 428 flowing over the contact pads 42. Although one or more embodiments of the present invention have been explained in detail, those skilled in the art will recognize Modifications and adaptations of the embodiments may be made without departing from the scope of the invention as set forth in the following claims. FIG. 1 depicts a semiconductor die and substrate. A cross-sectional view of a conventional interconnection between line conductors; FIG. 2 is a top plan view of a conventional interconnection formed over a line conductor through a solder mask opening; ^ Figures 3a-3b are depicted in Using a solder mask A conventional line conductor configuration between soldered interconnects; a PCB depicting a different type of package for women's wear to the surface; FIGS. 5a-5d depict further semiconductor package 50 201227901 mounted to the pCB 6a-6b is a semiconductor device having interconnects soldered back to the line conductors without a solder mask; Figures 7a-7b show further details of the bump pads along the line conductors; Figure 8 is a An interconnected interconnect having a non-fusible substrate and a fusible cover; Figures 9a-9b depict an alternate embodiment of a semiconductor device having interconnects soldered back on a line conductor without a solder mask; 10a-1 Oh depicts various interconnect structures formed over a semiconductor die for bonding to conductive traces on a substrate; FIG. 11 a-11 g depicting the semiconductor die and bonding to the conductive traces Figure 12a-12d depicts a semiconductor die having a wedge-shaped interconnect structure bonded to the conductive traces; Figures 13a-13d depict the semiconductor die and interconnections bonded to the conductive traces Another structure Figures 14a-14c depict stepped bumps and stud bump interconnect structures bonded to the conductive traces; Figures 15a-15b depict conductive traces having conductive vias; Figures 16a-16c depict The die pad between the semiconductor die and the substrate is filled; FIG. 17 depicts another die underfill between the semiconductor die and the substrate; FIG. 18 depicts the semiconductor die after the die pad is filled. And the substrate; 51 201227901 Figures 19a-19g show, describe the various configurations of the electrical circuit with open solder alignment; Figures 2a-20b depict the solder alignment on the conductive traces (4); and Figure 21 depicts P〇P with masking screen packaging material. #帛 During the mold underfill filling [Main component symbol description] 10 flip chip type semiconductor device 12 interconnection 14 bump 塾 15 solder mask 16 solder mask or alignment opening 18 substrate 20 line wire 30 line wire 32 line Wire 34 Line Conductor 36 Bump 38 Bump 40 Substrate 42 Semiconductor Die 44 Solder Mask 46 Bump Pad 52 201227901 48 Bump Pad 50 Electronics 52 Printed Circuit Board 54 Line 56 Wire Bonded Package 58 Flip Chip 60 Ball Grid Grid array 62 bump wafer carrier 64 double row package 66 platform grid array 68 multi wafer module 70 quad flat no-lead package 72 quad flat package 74 semiconductor die 76 contact pad 78 intermediate carrier 80 wire 82 wire bonding 84 package Material 88 Semiconductor die 90 Carrier 92 Bottom fill or epoxy adhesive material 94 Bond wire 96 Contact pad 53 201227901 98 Contact pad 100 Molding compound or encapsulating material 102 Contact pad 104 Bump 106 Intermediate carrier 108 Active region 110 Bump 111 bump pad 112 bump 114 signal line

115 PCB 116 Molding compound or encapsulant 117 Ball or bump 120 Flip-chip type semiconductor die 122 Grain bump pad 1 24 Line wire 126 Bump pad

130 Substrate or PCB 132 Interconnect 138 Underfill Filler 140 Solder Mask 144 Composite Bump 146 Non-Fuseable Substrate 148 Fusible Cover 54 201227901 150 152 154 156 160 162 168 170 220 222 324 226 228 230 232 234 236 238 240 242 244 246 248 Flip-chip type semiconductor grain grain bumps 塾 line conductor bump pads

Substrate or PCB Interconnect Primer Filler Solder Mask Semiconductor Wafer Body Substrate Material Semiconductor Die or Member Cut Surface Back Surface Active Surface Conductive Layer Bump Material Ball or Bump Composite Bump Non-meltable Part Fusible Partial bump conductive stud bump material bump 55 250 201227901 252 254 256 258 260 261 262 264 266 268 270 274 276 27 8 280 284 286 288 290 294 296 298 300 304 Saw blade or laser cutting tool substrate conductive circuit substrate or PCB conductive line bump material composite bump non-meltable or non-decomposable part fusible or decomposable part of conductive circuit substrate bump material conductive circuit substrate bump bump material tip conductive circuit substrate bump material tip conductive line Substrate bump material 56 201227901 306 308 310 312 314 318 318 320 322 324 326 328 330 332 334 340 342 344 346 348 350 352 354 Conductive circuit substrate conductive through hole opening conductive sidewall above mold support lower mold support groove mold Compressible release film packaging material nozzle auxiliary barrier packaging material nozzle base Conductive circuit substrate bump 塾 mask layer bump or interconnect substrate conductive circuit substrate bump pad mask layer £ 57 356 201227901 360 conductive line 362 conductive line 364 substrate bump 塾 366 substrate 368 mask layer 370 conductive line 372 conductive Line 374 Substrate bump pad 376 Substrate 378 Mask layer 380 Conductive line 382 Conductive line 384 Substrate bump pad 386 Substrate 388 Mask layer 390 Bump or interconnect 392 Mask layer 394 Conductive line 396 Conductive line 398 Bump pad 400 Substrate 402 Mask Patch 404 Ball or Bump 405 Stack Package 58 201227901 406 Semiconductor Die 408 Semiconductor Die 410 Die Attachment Adhesive 412 Conductive Line 414 Substrate 416 Bump Material 418 Contact Pad 420 Contact Pad 422 Bond Wire 424 Contact pad 426 mask layer 428 encapsulation material 59

Claims (1)

201227901 VII. Patent application scope: 1. A method for manufacturing a semiconductor device, comprising: providing a semiconductor die having a die bump pad; providing a substrate having a conductive trace, the conductive trace having an interconnection position; Depositing a conductive bump material on the land or the die bump; mounting the semiconductor die to the substrate such that the conductive bump material is disposed between the die bump pad and the interconnecting location; Reducing the conductive bump material without a solder mask around the grain bump pad or interconnecting location to form an interconnect structure between the semiconductor die and the substrate, wherein the conductive bump material is self-limited to the die bump a pad or interconnect location; and depositing an encapsulation material between the semiconductor die and the substrate. 2. The method of claim 4, wherein the step of immersing the conductive bump material in the fluxing solvent to increase wettability. 3. If you apply for a patent! The method further includes forming an insulating layer over the area around the bump bump or interconnect location such that the domain is less wet than the die bump pad and interconnect locations. (For example, in the method of claiming the range of μ, the step _ is included in one of the conductive bump materials accumulated between the s-thin grain bump pad and the interconnecting bit 1 so that the surface tension maintains the conductive 曰Hi 〒 凸 凸 自我 自我 自我 自我 自我 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 5. 3 The molten portion and the non-meltable portion. 6. The method of claim 1, wherein the interconnecting structure (60 201227901 includes a conductive pillar and a convex formed on the conductive pillar) 7. A method of fabricating a semiconductor device, comprising: providing a first semiconductor having a first interconnect location to provide a second semiconductor having a second interconnect location at the first and second interconnect locations Depositing a conductive bump material between the first and second interconnect locations; forming an interconnect structure from the conductive bumps under the solder mask to bond the first and the first structures, wherein the conductive bumps Material is from position; and self &amp; The first and second interconnects deposit an encapsulation material between the first and second semiconductor community conductor structures. Electroconvex = the method of claim 7 of the patent, the step further comprising immersing the lead material in (4) The solvent may be increased by H. 9. The method of claim 7 - the interconnection position or the second interconnection position, the second method of forming an insulating layer on the region of the region The first interconnection location is less humid. 10. As described in the patent application scope 7 in the first and the first-inter-, ... method, the further step includes selecting the amount of the interconnection position of the long-distance, so that the table (4) The material of the bumps in the coverage area of the first and second interconnection locations is substantially self-limited to 11. The scope of the patent application scope 7 covers the first interconnection position or the first mutual Far/method, wherein the interconnect structure is 12. σφ, _ 飞 一 一 互连 互连 互连 互连 互连 互连 。 。 。 。 。 。 。 。 U U 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊, wherein the interconnect structure is 61 201227901 1 3. If the patent application scope is 7th Ganzi — The method of the present invention, wherein the interconnect structure is a conductive pillar and a bump formed on the conductive pillar. M. A method of fabricating a semiconductor device, comprising: providing a first interconnect a first semiconductor structure of the defective device; k for a second semiconductor structure having a second interconnect position; at a first interconnect location or a second interconnect material, interconnected location Depositing a conductive bump and forming an interconnect structure from the conductive bump material at the first and second interconnect locations and under the gate/solder mask to form a interconnect structure, and A second semiconductor structure. 1 5. The scope of claim 4, &lt; 沄, further comprising depositing an encapsulating material between the first and second semiconductor structures. 16_, as claimed in the scope of &lt;RTIgt; </ RTI> <RTIgt; </ RTI> further comprising immersing the electrically conductive bump material in a fluxing solvent to increase wettability. 17. The method of claim 5, further comprising forming an insulating layer over the area around the interconnecting location or the second interconnecting location such that the region is more than the first-to-two interconnected location Not wet. 1 8. As stated in the scope of the patent application, the — — 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人An amount of 'to make the surface tension only m knife is difficult to self-limiting 5 Hai conductive bump material. 1 9. The method of claim 14, wherein the interconnect structure covers a top surface and a side of the first interconnecting location or the first interconnecting location surface. 20. The method of claim 5, wherein the interconnect structure 62 201227901 comprises a fusible portion and a non-fusible portion. A semiconductor device comprising: a first semiconductor structure having a first interconnection location; a second semiconductor structure having a first interconnection location; and a non-weld spinning around the first interconnection location The solid structure further forms an interconnect structure between the second semiconductor structures and a package material deposited between the first and second semiconductor structures. 22. As claimed in claim 21 In the semiconductor device, 1 scoop includes an insulating layer formed on a region around the first interconnection position &lt; _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 匕 » The first and first interconnection locations of the 堞 忒 are less humid. 23. The semiconductor device of claim 21, wherein the interconnection structure covers the first interconnection, the enemy is weak, φ u The top surface and the side surface of the first interconnecting location. 24. The semiconductor device of claim 21, wherein the interconnect structure comprises a fusible portion and a non-fusible portion. Apply for the scope of patent 21 Conductor means, wherein the interconnect structure comprising conductive lines and the prongs forming a bump on the conductive pillars eight, FIG formula: (summarized as follows p) 63