KR20120067266A - Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask - Google Patents

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask Download PDF

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KR20120067266A
KR20120067266A KR1020110024067A KR20110024067A KR20120067266A KR 20120067266 A KR20120067266 A KR 20120067266A KR 1020110024067 A KR1020110024067 A KR 1020110024067A KR 20110024067 A KR20110024067 A KR 20110024067A KR 20120067266 A KR20120067266 A KR 20120067266A
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South Korea
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interconnect
bump
conductive
die
bump material
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KR1020110024067A
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Korean (ko)
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KR101979024B1 (en
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라젠드라 디. 펜세
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스태츠 칩팩, 엘티디.
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Priority claimed from US12/969,467 external-priority patent/US9029196B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/64—Manufacture or treatment of solid state devices other than semiconductor devices, or of parts thereof, not peculiar to a single device provided for in groups H01L31/00 - H10K99/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The semiconductor device has a semiconductor die with die bump pads. One substrate has a conductive trace with interconnect sites. Conductive bump material is electrodeposited on the interconnect sites or die bump pads. The semiconductor die is mounted over the substrate such that the bump material lies between the die bump pads and the interconnect sites. The bump material is reflowed around the die bump pad or interconnect site without a solder mask to form an interconnect structure between the die and the substrate. The bump material is self-confined within the bump pad or interconnect site. The volume of bump material is selected such that the surface tension maintains the self-confinement of the bump material within the footprint of the die bump pads and interconnect sites. The interconnect structure may have a soluble portion and a non-soluble portion. The encapsulant is electrodeposited between the die and the substrate.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK}

BACKGROUND OF THE INVENTION The present invention generally relates to semiconductor devices, in particular semiconductor devices and methods of self-confining conductive bump materials without solder masks during reflow.

Semiconductor devices are commonly used in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Individual semiconductor devices generally include one of the electrical components, namely light emitting diodes (LEDs), small signal transistors, resistors, capacitors, inductors, and MOS field effect transistors (MOSFETs). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-connect devices (CCDs), solar cells and digital micro-mirror devices (DMDs).

The semiconductor device performs a wide range of functions such as signal processing, high speed computation, transmission and reception of electromagnetic signals, electronic device control, conversion of sunlight into electricity, and the formation of visual projections for television displays. Semiconductor devices are used in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also used in military applications, aviation, automotive, industrial controllers and office equipment.

Semiconductor devices take advantage of the electrical properties of semiconductor materials. The atomic structure of a semiconductor material doubles its electrical conductivity through the application or doping process of an electric field or base current. Doping introduces impurities into the semiconductor material to double or control the conductivity of the semiconductor device.

Semiconductor devices include active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of current. By varying the level of doping and field effect or base current, the transistor facilitates or limits current flow. Passive structures, including resistors, capacitors, and inductors, create a correlation between the voltage and current needed to perform various electrical functions. The active and passive structures are electrically connected to form a circuit, which allows the semiconductor device to perform high speed computations and other useful functions.

Semiconductor devices are typically manufactured using two complex manufacturing processes, a front-end process and a back-end process, each of which potentially involves hundreds of steps. The front-end fabrication involves forming multiple dies on the semiconductor wafer surface. Each die is essentially identical and includes circuitry formed by electrically connecting active and passive components. The back-end fabrication involves singulating each die from the final wafer and packaging the die to provide structural support and environmental separation.

One purpose of semiconductor manufacturing is to manufacture smaller semiconductor devices. Smaller semiconductor devices consume less power, have higher performance, and can be manufactured more efficiently. In addition, small semiconductor devices have a small footprint, which is desirable for smaller end products. Small die size can be achieved by improvements in the front-end process resulting in a die with smaller, higher density active and passive components. Back-end processes can result in semiconductor device packages with smaller footprints by improvements in electrical interconnects and material packaging.

FIG. 1 illustrates a flip chip type semiconductor device 10 having interconnects 12 that are metallically and electrically connected between a bump pad 14 and a trace line 20 using a solder mask 15. have. A circular solder mask or registration opening (SRO) 16 is formed over the substrate 18, as shown in FIG. 2, to expose the trace line 20. Trace line 20 is a straight conductor with an optional bump pad for engaging interconnect 12. The SRO 16 confines the conductive bump material on the bump pads of the trace line 20 during reflow and prevents the leach onto the traces where the molten bump material can cause electrical shorts in adjacent structures. The SRO 16 is made larger than the tray line or bump pad. SRO 16 is typically circular in shape and made as small as possible to reduce the pitch of trace line 20 and increase routing denstity.

In a typical design rule, the minimum escape pitch of trace line 20 should be based on the fact that SRO 16 should be at least as large as the base diameter D plus solder mask registration error (SRT) of interconnect 12. Limited by In addition, a minimum ligament of solder mask material is required between adjacent openings due to the limitations of the solder mask application process. In particular, the minimum escape pitch is defined as P = D + 2 * SRT + L. In one embodiment, if D is 100 μm, SRT is 10 μm, and L is 60 μm, then the minimum escape pitch is 100 + 2 * 10 + 60 = 180 μm.

3A and 3B are top and cross-sectional views of another conventional arrangement having trace lines 30 routed between trace lines 32 and 34 and bumps 36 and 38 on substrate 40. Bumps 36 and 38 electrically connect semiconductor die 42 to substrate 40. Solder mask 44 overlaps bump pads 46 and 48. The minimum escape pitch of trace line 30 is defined as P = D / 2 + SRT + L + W / 2, where W is the trace line width and L is the separation separation between SRO and adjacent structures. In one embodiment, D is 100 μm, SRT is 10 μm, W is 30 μm, and L is 60 μm. The minimum escape pitch of trace lines 30-34 is 100/2 + 10 + 60 + 30/2 = 135 μm. As the demand for high routing density increases, fewer escape pitches are needed.

1 shows a cross section of a typical interconnect formed between a semiconductor die and a trace line on a substrate.
FIG. 2 shows a plan view of a typical interconnect formed over a trace line through a solder mask opening. FIG.
3A-3B illustrate a typical arrangement of trace lines between reflowed interconnects using solder masks.
4 shows a PCB with different types of packages mounted on its surface.
5A-5D show other details of an exemplary semiconductor package mounted on a PCB.
6A-6B illustrate semiconductor devices with interconnects reflowed on a solderless trace.
7A-7B illustrate other details of bump pads along trace lines.
8 illustrates a composite interconnect with an insoluble base and a fusible cap.
9A-9B illustrate another embodiment of a semiconductor device with interconnects reflowed on a trace line without solder mask.
10A-10H illustrate various interconnect structures formed over a semiconductor die for coupling to conductive traces on a substrate.
11A-11G illustrate semiconductor die and interconnect structures coupled to conductive traces.
12A-12D illustrate a semiconductor die having a wedge-shaped interconnect structure coupled to a conductive trace.
13A-13D illustrate another embodiment of a semiconductor die and interconnect structure coupled to a conductive trace.
14A-14C illustrate step bump and stud bump interconnect structures coupled to conductive traces.
15A-15B illustrate conductive traces with conductive vias.
16A-16C illustrate mold underfill between a semiconductor die and a substrate.
17 illustrates another mold underfill between a semiconductor die and a substrate.
18 illustrates a semiconductor die and a substrate after mold underfill.
19A-19G illustrate various arrangements of conductive traces with open solder registration.
20A-20B illustrate open solder registration with patches between conductive traces.
FIG. 21 shows a POP with a masking layer dam to limit the encapsulant during mold underfill. FIG.

There is a need to minimize escape patches on trace lines for higher routing density. Thus, in one embodiment, the present invention is directed to a method of manufacturing a semiconductor device, the method comprising providing a semiconductor die having a die bump pad; Providing a substrate having a conductive trace with interconnect sites; Electrodepositing a conductive bump material on the interconnect site or the die bump pad; Mounting the semiconductor die to the substrate such that the conductive bump material is disposed between the die bump pad and an interconnect site; Reflowing the conductive bump material around the die bump pad or the interconnect site without a solder mask to form an interconnect structure between the semiconductor die and the substrate, wherein the conductive bump material is formed on the die bump pad or the interconnect. Self-confined within the access site; And depositing an encapsulant between the semiconductor die and the substrate.

In another embodiment, the present invention is directed to a method of manufacturing a semiconductor device, the method comprising: providing a first semiconductor structure having a first interconnect site; Providing a second semiconductor structure having a second interconnect site; Electrodepositing a conductive bump material between the first and second interconnect sites; Forming an interconnect structure from the conductive bump material to couple around the first and second interconnect sites without the first and second semiconductor structure solder masks, wherein the conductive bump material is formed on the first and second interconnects. Self-confined within the access site; And depositing an encapsulant between the first and second semiconductor structures.

In another embodiment, the present invention is directed to a method of manufacturing a semiconductor device, the method comprising: providing a first semiconductor structure having a first interconnect site; Providing a second semiconductor structure having a second interconnect site; Electrodepositing a conductive bump material over the first interconnect site or the second interconnect site; And forming an interconnect structure from the conductive bump material to couple the first and second semiconductor structures around the first and second interconnect sites without a solder mask.

In another embodiment, a semiconductor device of the present invention comprises a first semiconductor structure having a first interconnect site; A second semiconductor structure having a second interconnection site; An interconnect structure formed between the first and second semiconductor structures without a solder mask around the first and second interconnect sites; And an encapsulation material electrodeposited between the first and second semiconductor structures.

The invention is described in one or more embodiments of the following description with reference to the drawings in which like reference numerals refer to the same or like elements. Although the invention has been described in terms of the best mode for achieving the object of the invention, those skilled in the art will appreciate that the spirit and scope of the invention as defined by the appended claims and the equivalents supported by the following description and drawings. It will be understood that the intention is to cover substitutions, modifications, and equivalents that may be included in.

Semiconductor devices are generally manufactured using two complex manufacturing processes, namely front-end manufacturing and back-end manufacturing. Front-end fabrication involves forming multiple dies on a semiconductor wafer surface. Each die on the wafer includes active and passive electrical components, which are electrically connected to form a functional electrical circuit. Active active electrical components such as transistors and diodes have the ability to control current flow. Passive electrical components such as capacitors, inductors, resistors, and transformers form the relationship between the voltage and current required to perform electrical circuit functions.

Active and passive components are formed on the semiconductor wafer surface by a series of process steps including doping, electrodeposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process transforms the electrical conductivity of the semiconductor material in the active device, transforms the semiconductor material into an insulator or conductor, or dramatically changes the semiconductor material conductivity in response to an electric field or base current. Transistors include regions of varying degrees and forms of doping arranged as necessary to enable the transistor to promote or limit current flow in response to application of an electric field or base current.

Active and passive components are formed by layers of material having different electrical properties. The layers can be formed by a variety of electrodeposition techniques, in part determined by the type of material to be electrodeposited. For example, thin film electrodeposition includes chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, and electrical connections therebetween.

The layers are patterned using photolithography, which includes electrodepositing a photosensitive material, ie a photoresist, on the patterned layer. One pattern travels from the photomask to the photoresist using light. The portion of the photoresist phantom in contact with light is removed using a solvent and the underlying layer to be patterned is exposed. The remaining portion of the photoresist is removed leaving behind a patterned layer. In addition, some forms of material are patterned by direct electrodeposition of the material into areas or voids formed by advanced electrodeposition / etching processes using techniques such as electroless and electrolytic plating.

Electrodeposition of a thin film of material on an already existing pattern can worsen the underlying pattern and form a non-uniform flat surface. Uniform flat surfaces are required to make smaller, tightly packed active and passive components. Planarization can be used to remove material from the wafer surface and create a uniform flat surface. Planarization involves the process of polishing a wafer surface with a polishing pad. Wear and corrosion chemicals are added to the wafer surface during polishing. The combined mechanical action of the wear and corrosion of the chemical removes any irregular shapes to create a uniform flat surface.

Back-end fabrication refers to packaging the die for structural support and environmental separation after cutting and singulating the final wafer into individual dies. In order to singulate the die, the wafer is lined and broken along the nonfunctional area of the wafer, called saw street or scribe. The wafer is singulated using a laser cutting tool or saw blade. After singulation, each die is mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor die are then connected to contact pads in the package. Electrical connections can be made of solder bumps, stud bumps, conductive pastes or wirebonds. Encapsulant or other molding material is deposited on the package to provide physical support and electrical separation. The final package is then inserted into an electrical system and the functionality of the semiconductor device is made available to other system components.

4 shows an electronic device 50 having a chip carrier substrate or printed circuit board (PCB) 52 with multiple semiconductor packages mounted on its surface. The electronic device 50 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application. Different forms of semiconductor package are shown in FIG. 4 for illustrative purposes.

The electronic device 50 may be a standalone system that uses a semiconductor package to perform one or more electrical functions. The electronic device 50 may also be a lower part of a larger system. For example, the electronic device 50 may be part of a mobile phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. The electronic device 50 can also be a graphics card, a network interface card or other signal processing card that can be inserted into a computer. The semiconductor package may include a microprocessor, memory, special purpose integrated circuit (ASIC), logic circuit, analog circuit, RF circuit, discrete device, or other semiconductor die or electrical component. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be reduced for higher integration.

In FIG. 4, PCB 52 provides a general substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 54 are formed on the PCB 52 surface or in PCB layers using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal electrodeposition process. Signal trace 54 provides electrical communication between each semiconductor package, mounted components, and other external system components. Trace 54 also provides power and ground connections to each of the semiconductor packages.

In some embodiments, the semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate carrier. Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In another embodiment, the semiconductor device may only have a first level packaging in which the die is mechanically and electrically mounted directly to the PCB.

For purposes of illustration, various forms of first level packaging including wire bond package 56 and flip chip 58 are shown on PCB 52. In addition, ball grid arrays (BGA, 60), bump chip carriers (BCC, 62), dual in-line packages (DIP, 64), land grid arrays (LGA, 66), multi-chip modules (MCM, 68), Several forms of second level packaging, including quad flat non-lead package (QFN) 70 and quad flat package 72, have been shown mounted on PCB 52. Depending on system requirements, any combination of semiconductor packages consisting of any combination of first and second level packaging forms as well as other electronic components may be connected to the PCB 52. In some embodiments, electronic device 50 includes a single attachment semiconductor package, while other embodiments require multiple interconnect packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages have complex functionality, electronic devices can be manufactured using cheaper components and simplified manufacturing processes. The resulting devices have fewer failures and are cheaper to manufacture, resulting in lower costs for the consumer.

5A-5D illustrate exemplary semiconductor packages. 5A shows another detail of the DIP 64 mounted on the PCB 52. Semiconductor die 74 includes an active region formed therein including an active region, a passive element, a conductive layer, and an analog or digital circuit implemented as an insulating layer, and is electrically interconnected according to the electrical design of the die. For example, the circuit includes one or more transistors, diodes, inductors, capacitors, resistors, and other circuit members formed in the semiconductor die 74. The contact pads 76 are one or more layers of conductive materials such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and the semiconductor die 74 Is electrically connected to a circuit member formed in the circuit. During assembly of the DIP 64, the semiconductor die 74 is mounted to the intermediate carrier 78 using a gold-silver process layer or an attachment such as a thermal epoxy or epoxy resin. The package body includes an insulating packaging material such as a polymer or ceramic. Conductor lead 80 and bond wire 82 provide an electrical connection between semiconductor die 74 and PCB 52. An encapsulant 84 is electrodeposited on the package for environmental protection by preventing moisture and particles from penetrating into the package and preventing contamination of the semiconductor die 74 or bond wire 82.

5B shows another detail of the BCC 62 mounted on the PCB 52. The semiconductor die 88 is mounted over the carrier 90 using an underfill or epoxy-resin attachment material 92. Bond wire 94 provides a first level packaging interconnect between contact pads 96 and 98. A molding compound or encapsulant 100 is electrodeposited over the semiconductor die 88 and bond wire 94 to provide physical support and electrical isolation of the device. Contact pads 102 are formed on the PCB 52 surface for oxidation prevention using suitable metal electrodeposition processes such as electrolytic plating or electroless plating. The contact pads 102 are electrically connected to one or more conducting signal traces 54 of the PCB 52. A bump 104 is formed between the contact pads 98 of the BCC 62 and the contact pads 102 of the PCB 52.

In FIG. 5C, the semiconductor die 58 is mounted in contact with the intermediate carrier 106 in a flip chip shaped first level packaging state. The active region 108 of the semiconductor die 58 includes analog and digital circuits implemented as active elements, passive elements, conductive layers, and insulating layers formed in accordance with the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit members in the active region 108. Semiconductor die 58 is electrically and mechanically connected to carrier 106 through bump 110.

BGA 60 is electrically and mechanically connected to PCB 52 in BGA type second level packaging using bumps 112. Semiconductor die 58 is electrically connected to conductive signal trace 54 of PCB 52 through bump 110, signal line 114, and bump 112. A molding compound or encapsulant 116 is deposited over the semiconductor die 58 and the carrier 106 to provide physical support and electrical isolation of the device. Flip chip semiconductor devices provide short electrical conduction paths from active devices on semiconductor die 58 to conducting tracks on PCB 52 to reduce signal propagation distance, provide lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 may be mechanically and electrically directly connected to the PCB 52 using flip chip type first level packaging without the intermediate carrier 106.

In another embodiment, the active region 108 of the semiconductor die 58 is mounted in direct contact with the PCB 115 directly, ie without an intermediate carrier, as shown in FIG. 5D. Bump pads 111 are formed on the active region 108 using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal electrodeposition processes. The bump pads 111 are connected to the active and passive circuits by conducting tracks in the active region 108. The bump pad 111 may be Al, Sn, Ni, Au, Ag, or Cu. The electrically conductive bump material is electrodeposited on the bump pad 111 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof with optional flux solution. For example, the bump material may be eutectic Sn / Pb, high-lead solder or lead-free solder. The bump material is bonded to die bump pad 160 using an appropriate attachment or bonding process. In one embodiment, the bump material is heated and reflowed above its melting point to form a spherical ball or bump 117. In some applications, bump 117 is reflowed twice to improve electrical contact to bump pad 111. Flip chip semiconductor devices provide short electrical conduction paths from active devices on semiconductor die 58 to conducting tracks on PCB 115 to reduce signal propagation, provide lower capacitance, and improve overall circuit performance.

 6A and 6B show a plan view and a cross section of a portion of a semiconductor die 120 in the form of a flip chip with bump pads 122. Trace line 124 is a straight conductor with integrated bump pads 126 formed on a substrate or PCB 130. 7A and 7B show other details of substrate bump pad 126 along trace line 124. The substrate bump pad 126 may be round as in FIG. 7A or rectangular as in FIG. 7B. Sides of the substrate bump pad 126 may be collinear with the trace line 124.

 The electrically conductive bump material is electrodeposited on die bump pad 122 or substrate bump pad 126 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder with a selective flux solution and combinations thereof. For example, the bump material may be process Sn / Pb, high-lead-solder or lead-free solder. The bump material is bonded to die bump pad 122 and substrate bump pad 126 using a suitable attach or bond process. In one embodiment, the bump material is reflowed by heating the bump material above its melting point to form the interconnect 132. In some applications, interconnect 132 is reflowed twice to improve electrical contact between die bump pad 122 and substrate bump pad 126. Bump material around the narrow substrate bump pad 126 maintains the die position during reflow. Although interconnect 132 is shown connected to trace line 124 as a bump-on-lead (BOL), the interconnect also has a substrate 130 having the same or larger area as die bump pad 122. It can be formed on the bump on the). An optional underfill material 138 is electrodeposited between the semiconductor die 120 and the substrate 130.

 In high routing density applications, it is desirable to minimize the escape pitch of conductive traces 124. The escape pitch between the conductive traces 124 can be reduced by removing the masking layer for reflow receiving purposes, ie by reflowing the bump material without the masking layer. The solder mask 140 may be formed on a portion of the substrate 130. However, solder mask 140 is not formed over substrate bump pads 126 of trace line 124 to accommodate reflow. That is, no SRO of the solder mask 140 exists in the portion of the trace line 124 that is designed to engage the bump material. Since no SRO is formed around the die bump pad 122 or the substrate bump pad 126, the trace line 124 can be formed at a finer pitch, that is, the trace line 124 is in close proximity to the structure. Or can be placed in the neighborhood. In the absence of solder mask 140, the pitch between trace lines 124 is given by P = D + PLT + W / 2, where D is the base diameter of interconnect 132, PLT is the position error, and W is the width of trace line 124. In one embodiment, given a bump base diameter of 100 μm, a PLT of 10 μm, and a trace line width of 30 μm, the minimum escape pitch of trace line 124 is 125 μm. Mask-less bump formation eliminates the need for explanation of the relocation space, SRT, and minimum resolvable SRO of the solder mask material between adjacent openings, as can be seen in the prior art.

When the bump material is reflowed to connect the die bump pad 122 metallographically and electrically to the substrate bump pad 126 without a solder mask, wetting and surface tension may cause the bump material to self-cone. Maintained in a confinement state and retained in a portion of the substrate 130 immediately adjacent to the trace line 124 in the space between the die pump pad 122 and the substrate bump pad 126 and in the footprint of the bump pad. Let's do it.

In order to achieve the desired self-confinement properties, the bump material may be formed by using the die bump pad 122 or the substrate bump pad (to make the area in contact with the bump material more selective than the surrounding area of the trace line 124). 126) may be impregnated with the flux solution before being placed. The molten bump material remains limited within the area defined by the bump pads due to the wetting properties of the flux solution. The bump material does not proceed to areas that are less wettable. An oxide layer or other insulating layer of the thin film may be formed over an area that the bump material was not intended to make less wet. For this reason, solder mask 140 is not needed around die pump pad 122 or substrate bump pad 126.

In another embodiment, a composite interconnect 144 is formed between die bump pad 122 and substrate bump pad 126 to achieve the desired self-confinement of bump material. . Composite interconnect 144 includes a non-soluble base 146 made of Cu, Au, Sn, Ni, and Pb, and a soluble cap 148 made of solder, Sn, or indium, as shown in FIG. Include. The volume of soluble bump material in relation to the insoluble base material is chosen to ensure self-containment by surface tension. During reflow, the soluble base material self-contains around the non-soluble base material. Soluble bump material around the insoluble base also maintains die position during reflow. In general, the height of composite interconnect 144 is equal to or less than the bump diameter. In some cases, the height of composite interconnect 144 is greater than the interconnect diameter. In some embodiments, given the bump base diameter of 100 μm, the height of the non-soluble base 146 is about 45 μm, and the height of the soluble cap 148 is about 35 μm. The molten bump material remains confined within the areas defined in the bump pads, so that the reaction surface tension is sufficient to maintain the bump material in the bump pad footprint and to prevent unintended progression to adjacent or neighboring areas. This is because the volume of electrodeposited bump material is selected to form a composite bump 144 that includes 146 and soluble cap 148. Thus, solder mask 140 is not needed around die bump pad 122 or substrate bump pad 126, which reduces trace line pitch and increases routing density.

9A and 9B show plan and cross-section views of other embodiments with flip chip shaped semiconductor die 150 with die bump pads 152. Trace line 154 is a straight conductor with integrated bump pads 156 formed on a substrate or PCB 160 similar to FIGS. 7A and 7B. In this embodiment, bump pads 156 are arranged in multiple or offset rows. Thus, alternating trace lines 154 include elbows for routing to bump pads 156.

Electrically conductive bump material is electrodeposited on die bump pad 152 or substrate bump pad 156 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder with a selective flux solution and combinations thereof. For example, the bump material may be process Sn / Pb, high-lead-solder or lead-free solder. Bump material is coupled to die bump pad 152 and substrate bump pad 156 using a suitable attach or bond process. In one embodiment, the bump material is reflowed by heating the bump material above its melting point to form the bump or interconnect 162. In some applications, interconnect 162 is reflowed twice to improve electrical contact between die bump pad 152 and substrate bump pad 156. Bump material around the narrow substrate bump pad 156 maintains the die position during reflow. Although interconnect 162 is shown as being connected to trace line 154 as a BOL, the bump material may also be formed over a bump on substrate 160 having the same or larger area as die bump pad 152. . An optional underfill material 168 is electrodeposited between the semiconductor die 150 and the substrate 160.

In high routing density applications, it is desirable to minimize the escape pitch. The bump material is reflowed without a solder mask to reduce the pitch between conductive trace lines 154. The escape pitch between the trace lines 154 can be reduced by removing the solder mask for solder reflow acceptance purposes, ie by reflowing the bump material without the solder mask. The solder mask 170 may be formed on a portion of the substrate 160. However, solder mask 170 is not formed over substrate bump pad 156 of trace line 154 to accommodate solder reflow. That is, no SRO of the solder mask 170 exists in the portion of the trace line 154 that is designed to engage the bump material. Since no SRO is formed around the die bump pad 152 or the substrate bump pad 156, the trace line 154 can be formed at a finer pitch, that is, the trace line 154 is close to the adjacent structure. Can be set.

In the absence of solder mask 170, the pitch between trace lines 154 is given by P = D / 2 + PLT + W / 2, where D is the base diameter of bump 162 and PLT is the die position error. And W is the width of trace line 154. In one embodiment, given a bump diameter of 100 μm, a PLT of 10 μm, and a trace line width of 30 μm, the minimum escape pitch of trace line 154 is 75 μm. Mask-less bump formation eliminates the need for explanation of the restitution space, the SRT, and the minimum resolvable SRO of the mask material between adjacent openings, as can be seen in the prior art.

When the bump material is reflowed to connect the die bump pads 152 of the semiconductor die 150 to the substrate bump pads 156 of the trace line 154 metallically and electrically without a solder mask, wetting ( wetting and surface tension keep the bump material in a self-confinment state and trace line 154 in the space between the die pump pad 152 and the substrate bump pad 156 and in the footprint of the bump pad. Is held in a portion of the substrate 160 immediately adjacent.

In order to achieve the desired self-confinement properties, the bump material may be formed by using the die bump pad 152 or the substrate bump pad (to make the area in contact with the bump material more selective than the surrounding area of the trace line 154). 156 may be impregnated with the flux solution before being placed. The molten bump material remains limited within the area defined by the bump pads due to the wetting properties of the flux solution. The bump material does not proceed to areas that are less wettable. An oxide layer or other insulating layer of the thin film may be formed over an area that the bump material was not intended to make less wet. For this reason, a solder mask 170 is not needed around the die pump pad 152 or the substrate bump pad 156.

In another embodiment, a composite interconnect is formed between die bump pad 152 and substrate bump pad 156 to achieve self-containment. Composite interconnects, similar to FIG. 8, include an insoluble base made of Cu, Au, Sn, Ni, or Pb, and a soluble cap made of solder, Sn, or indium. The volume or height of the soluble bump material in relation to the insoluble base material is chosen to ensure self-confinement by surface tension. During reflow, the soluble base material self-contains around the non-soluble base material. Soluble bump material around the insoluble base also maintains die position during reflow. In general, the height of the composite interconnect is less than or equal to the bump diameter. In some cases, the height of the composite interconnect is greater than the interconnect diameter. In some embodiments, given the bump base diameter of 100 μm, the height of the non-soluble base is about 45 μm, and the height of the soluble cap is about 35 μm. The molten bump material remains confined within the area defined in the bump pad, so that the reaction surface tension is sufficient to maintain the bump material in the bump pad footprint and to prevent unintentional progression to adjacent or neighboring areas. This is because the volume of electrodeposited bump material is selected to form a composite bump 144 that includes 146 and soluble cap 148. Thus, solder mask 170 is not needed around die bump pad 152 or substrate bump pad 156, which reduces trace line pitch and increases routing density.

10-15 illustrate other embodiments with various interconnect structures applicable to an interconnect structure without any SRO as shown in FIGS. 6-9. 10A shows a semiconductor wafer 220 having a base substrate material 222 for structural support such as silicon, germanium, gallium arsenide, indium phosphide or silicon carbide. Multiple semiconductor dies or components 224 separated by saw streets 226 as described above are formed on wafer 220.

10B illustrates a cross section of a portion of the semiconductor wafer 220. Each semiconductor die 224 is an analog and digital circuit implemented with back surface 228 and active, passive, conductive, and insulating layers formed mechanically and electrically interconnected within the die, depending on the electrical design or function of the die. It has an active surface 230 that includes them. For example, the circuit may include one or more transistors, diodes, and other signal members formed in the active surface 130 to implement analog or digital signals, such as a digital signal processor (DSP), ASIC, memory, or other signal processing circuit. It may include. The semiconductor die 224 may also include integrated passive elements (IPDs) such as inductors, capacitors, and resistors for RF signal processing. In one embodiment, the semiconductor die 224 is a flip chip shaped semiconductor die.

An electrically conductive layer 232 is formed over the active surface 230 using a PVD, CVD, electrolytic plating, electroless plating process or other suitable metal electrodeposition process. Conductive layer 232 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable electrically conductive material. Conductive layer 232 acts as a contact pad electrically connected to a circuit on active surface 230.

FIG. 10C illustrates a portion of a semiconductor wafer 220 with interconnect structures formed over contact pads 232. Electrically conductive bump material 234 is electrodeposited over contact pad 232 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material 234 may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder with optional flux solution and combinations thereof. For example, bump material 234 may be process Sn / Pb, high-lead solder or lead-free solder. Bump material 234 is generally compliant and undergoes plastic deformation greater than about 25 μm under force equivalent to a vertical load of about 200 g. Bump material 234 is coupled to contact pad 232 using a suitable attachment or bonding process. For example, bump material 234 may be press bonded to contact pad 232. Bump material 234 may also heat and reflow bump material above its melting point to form a spherical ball or bump 236, as shown in FIG. 10D. In some applications, bump 236 is reflowed twice to improve electrical contact to contact pad 232. Bump 236 represents a form of interconnect structure that may be formed over contact pads 232. The interconnect structure may use stud bumps, micro bumps or other electrical connectors.

10E illustrates another embodiment of an interconnect structure formed on contact pads 232 as a composite bump 238 that includes a non-soluble or non-collapsible portion 240 and a soluble or collapsible portion 242. . Soluble or collapsible and non-soluble or non-collapsible properties are defined for bump 238 for reflow conditions. The insoluble portion 240 may be Au, Cu, Ni, high-lead solder or lead-tin alloy. The soluble portion 242 can be Sn, lead-free alloys, Sn-Ag alloys, Sn-Ag-Cu alloys, Sn-Ag-indium (In) alloys, eutectic solders, tin alloys of Ag, Cu or Pb or other relatively low temperatures. It may be a molten solder. In one embodiment, given the contact pad 232 width or diameter of 100 μm, the non-soluble portion 240 is about 45 μm in height and the soluble portion 242 is about 35 μm in height.

10F illustrates another embodiment of an interconnect structure formed over contact pad 232 as bump 244 over conductive pillar 246. Bump 244 is soluble or collapsible and conductive pillar 246 is insoluble or non-collapseable. Soluble or decayable and insoluble or nondestructive properties are defined for reflow conditions. The bumps 244 may be Sn, lead-free alloys, Sn-Ag alloys, Sn-Ag-Cu alloys, Sn-Ag-In alloys, eutectic solders, Ag alloys of Ag, Cu or Pb, or other relatively low temperatures. It may be a molten solder. Conductive pillars 246 may be Au, Cu, Ni, high-lead solder or lead-tin alloys. In one embodiment, conductive pillar 246 is a Cu pillar and bump 244 is a solder cap. Given that the width or diameter of the contact pad 232 is 100 μm, the conductive pillar 246 height is about 45 μm and the bump 244 height is about 35 μm.

FIG. 10G illustrates another embodiment of an interconnect structure formed over contact pad 232 as bump material 248 with protrusion 250. Bump material 248 has low tensile strength and high elongation to break, similar to bump material 234, and is flexible and deformable under reflow conditions. The protrusion 250 is formed with a plated finish surface and enlarged in the drawings for purposes of illustration. The size of the protrusion 250 is also generally 1-25 μm. The protrusions may also be formed on bumps 236, composite bumps 238 and bumps 244.

In FIG. 10H, the semiconductor wafer 220 is singulated into the individual semiconductor die 224 along the saw street 226 using a saw blade or laser cutting tool 252.

11A shows a substrate or PCB 254 with conductive traces 256. Substrate 254 may be a single side FR5 laminate or a two side BT-resin laminate. Referring to FIGS. 19A-19G, semiconductor die 224 is positioned such that bump material 234 is tucked side by side with the interconnect sites of conductive trace 256. Further, bump material 234 may be arranged side by side with conductive pads or other interconnect sites formed on substrate 254. Bump material 234 is wider than conductive trace 256. In one embodiment, bump material 234 has a width of less than 100 μm and conductive traces or pads 256 have a width of 35 μm for a bump pitch of 150 μm.

Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to compress the bump material 234 into the conductive trace 256. Force F can be applied at a high temperature. Due to the compliant nature of bump material 234, the bump material is deformed or extruded around the top surface and sides of conductive trace 256, as referred to as BOL. In particular, the application of pressure causes the bump material 234 to undergo plastic deformation greater than about 25 μm under a force F corresponding to a vertical load of about 200 g, and as shown in FIG. 11B, the top or side surface of the conductive trace is shown. Cover it. Bump material 234 may also be metallically connected to conductive trace 256 by physically contacting the bump material with the conductive trace and by reflowing the bump material under reflow temperature.

By making the conductive trace 256 narrower than the bump material 234, the conductive trace pitch can be reduced to increase routing density and I / O count. The narrower conductive trace 156 reduces the force F needed to deform the bump material 134 around the conductive trace. For example, the necessary force F may be 30-50% of the force required to deform the bump material for a conductive trace or pad that is wider than the bump material. Lower compression forces F are useful for fine pitch interconnects and small dies in order to maintain coplanarity with special errors and achieve uniform z-direction strain and high reliability interconnect unions. In addition, deforming the bump material 134 around the conductive trace 156 mechanically locks the bump to the trace to prevent die shifting or die floating during reflow.

FIG. 11C shows bumps 236 formed over contact pads 232 of semiconductor die 224. Semiconductor die 224 is positioned such that bump 236 is parallel with the interconnect sites on conductive traces 256. In addition, bump 236 may be side by side with conductive pads or other interconnect sites formed on substrate 254. Bump 236 is wider than conductive trace 256. Conductive traces 256 are applicable to interconnect structures without any SRO as shown in FIGS. 6-9.

Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump 236 to the conductive trace 356. Force F may be applied at a high temperature. Due to the docile nature of the bump 236, the bump is deformed or extruded around the top and sides of the conductive trace 256. In particular, the application of pressure causes the bump 236 to undergo plastic deformation and cover the top and sides of the conductive trace 256. Bump 236 is also metallically connected to conductive trace 256 by physically contacting the conductive trace and the bump under reflow temperature.

By making the conductive trace 256 narrower than the bump 236, the conductive trace pitch can be reduced to increase routing density and I / O count. The narrower conductive trace 256 reduces the force F needed to deform the bump material 234 around the conductive trace. For example, the necessary force F may be 30-50% of the force required to deform the bump material for a conductive trace or pad that is wider than the bump material. Lower compression forces F are useful for fine pitch interconnects and small dies in order to maintain coplanarity within a specific error range and achieve uniform z-direction strain and high reliability interconnect unions. In addition, deforming the bump material 234 around the conductive trace 256 mechanically locks the bump to the trace to prevent shifting of the die or floating of the die during reflow.

11D illustrates compound bump 238 formed over contact pad 232 of semiconductor die 224. The semiconductor die 224 is positioned such that the compound bumps 238 are parallel with the interconnect sites on the conductive traces 256. In addition, composite bump 238 may be parallel with conductive pads or other interconnect sites formed on substrate 254. Compound bump 238 is wider than conductive trace 256. Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to pressurize the fusible portion 242 to the conductive trace 256. Force F may be applied at a high temperature. Due to the mild nature of the soluble portion 242, the soluble portion is deformed or extruded around the top and sides of the conductive trace 256. In particular, the application of pressure causes the soluble portion 242 to undergo plastic deformation and cover the top and side surfaces of the conductive trace 256. Composite bump 238 may also be metallically connected to conductive trace 256 by physically contacting soluble portion 242 with conductive trace under reflow temperature. The insoluble portion 240 does not melt or deform during application of pressure or temperature and maintains its height and vertical standoff between the semiconductor die 224 and the substrate 254. Additional displacements between the semiconductor die 224 and the substrate 254 provide greater coplanarity errors between the mating surfaces.

During the reflow process, a large number (eg, thousands) of composite bumps 238 on semiconductor die 224 are attached to interconnect sites on conductive traces 256 of substrate 254. Some of the bumps 238 fail to properly connect to the conductive traces 256, especially when the die 224 is warped. Recall that compound bump 238 is wider than conductive trace 256. With the appropriate force applied, the soluble portion 242 is deformed or extruded around the top and sides of the conductive trace 256 and mechanically locks the composite bump 238 to the conductive trace. Mechanical interlocking is formed by the nature of the soluble portion 242, which is softer and more compliant than the conductive traces 256, and thus deformations on and around the top surface of the conductive traces for larger contact surface areas. Mechanical interlocking between composite bumps 238 and conductive traces 256 maintains the conductive traces during reflow, i.e., bumps and conductive traces do not lose contact. Thus, composite bump 238 that engages conductive trace 256 reduces bump interconnect failure.

FIG. 11E illustrates conductive pillars 246 and bumps 244 formed over contact pads 232 of semiconductor die 224. Semiconductor die 224 is positioned such that bump 244 is aligned side by side with the interconnection site of conductive trace 256. In addition, bump 244 may be parallel with conductive pads or other interconnect sites formed on substrate 254. Bump 244 is wider than conductive trace 256. Conductive trace 256 is applicable to an interconnect structure without any SRO as shown in FIGS. 6-9.

Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump 244 to the conductive trace 256. Force F may be applied at a high temperature. Due to the docile nature of the bump 244, the bump is deformed or extruded around the top and sides of the conductive trace 256. In particular, the application of pressure causes bump 244 to undergo plastic deformation and cover top and side surfaces of conductive trace 256. The conductive pillars 246 and bumps 244 may also be metallically connected to the conductive traces 256 by physically contacting the bumps with the conductive traces under reflow temperature. The conductive pillar 246 does not melt or deform during the application of pressure or temperature and maintains its height and vertical standoff between the semiconductor die 224 and the substrate 254. Additional displacements between the semiconductor die 224 and the substrate 254 provide greater coplanarity errors between the mating surfaces. The wider bumps 244 and narrower conductive traces 256 have low essential compressive force, mechanical locking features and advantages similar to those described above for the bump material 234 and the bumps 236.

11F shows bump material 248 with protrusions 250 formed over contact pads 232 of semiconductor die 224. The semiconductor die 224 is positioned so that the bump material 248 is aligned side by side with the interconnect sites of the conductive traces 256. In addition, bump material 248 may be side by side with conductive pads or other interconnect sites formed on substrate 254. Bump material 248 is wider than conductive trace 256. Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 248 to the conductive trace 256. Force F may be applied at a high temperature. Due to the docile nature of the bump material 248, the bump is deformed or extruded around the top and sides of the conductive trace 256. In particular, the application of pressure causes the bump material 248 to undergo plastic deformation and cover the top and sides of the conductive trace 256. In addition, the protrusion 250 is metallically connected to the conductive trace 256. The protrusion 250 is about 1-25 μm in size.

FIG. 11G shows PCB 258 with trapezoidal conductive traces 260 with angled or inclined sides. Bump material 261 is formed over the contact pads 232 of the semiconductor die 224. Semiconductor die 224 is positioned such that bump material 261 is aligned side by side with the interconnect sites of conductive traces 260. In addition, bump material 260 may be side by side with conductive pads or other interconnect sites formed on substrate 254. Bump material 261 is wider than conductive trace 260. Conductive trace 260 is applicable to an interconnect structure without any SRO as shown in FIGS. 6-9.

Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 261 to the conductive trace 260. Force F may be applied at a high temperature. Due to the docile nature of bump material 261, bump material is deformed or extruded around the top and sides of conductive trace 260. In particular, the application of pressure causes the bump material 261 to undergo plastic deformation under force F and to cover the top and angled sides of the conductive trace 260. Bump material 261 may also be metallically connected to conductive trace 160 by physically contacting the bump material under conductive temperature and then reflowing the bump material.

12A-12D illustrate a BOL embodiment of an elongated composite bump 262 having a semiconductor die 224, an insoluble or non-collapsible portion 264, and a soluble or collapsible portion 266. The non-soluble portion 264 may be Au, Cu, Ni, high-lead solder or lead-tin alloy. The soluble portion 266 may be Sn, lead-free alloy, Sn-Ag alloy, Sn-Ag-Cu alloy, Sn-Ag-In alloy, process solder, Ag, Cu or Pb tin alloy or other relatively low temperature melt solder. Can be. The non-availability portion 264 constitutes a larger portion of the composite bump 262 than the availability portion 266. The insoluble portion 264 is fixed to the contact pad 232 of the semiconductor die 224.

Semiconductor die 224 is positioned such that composite bump 262 is parallel with interconnect sites on conductive traces 268 formed in substrate 270, as shown in FIG. 12A. Compound bumps 262 taper along conductive traces 268, that is, compound bumps have a wedge shape, which is longer along the length of conductive traces 268 and narrower while crossing the conductive traces. The tapered aspect of compound bump 262 occurs along the length of conductive trace 268. 12A shows a narrower taper that is shorter or collinear with conductive trace 268. 12B, perpendicular to FIG. 12A, shows a longer aspect of the wedge-shaped composite bump 262. The shorter aspect of compound bump 262 is wider than conductive trace 268. The soluble portion 266 collapses around the conductive traces 268 as it reflows with the application of pressure and / or heat, as shown in FIGS. 12C and 12D. The insoluble portion 264 maintains its form and shape without melting or deforming during reflow. The insoluble portion 264 is sized to provide a standoff distance between the semiconductor die 224 and the substrate 270. A finish, such as Cu OSP, may be applied to the substrate 270. Conductive traces 268 are applicable to interconnect structures without any SRO as shown in FIGS. 6-9.

During the reflow process, a large number (eg, thousands) of composite bumps 262 on semiconductor die 224 are attached to interconnect sites on conductive traces 268 of substrate 270. Some of the bumps 262 fail to properly connect to the conductive traces 268, especially when the semiconductor die 224 is warped. Recall that compound bump 262 is wider than conductive trace 268. With appropriate force applied, the soluble portion 266 deforms or extrudes around the top and sides of the conductive trace 268 and mechanically locks the composite bump 262 to the conductive trace. Mechanical interlocking is formed by the nature of the soluble portion 266, which is softer and more compliant than the conductive trace 268, and thus deformations on and around the top surface of the conductive trace for a larger contact surface area. The wedge-shape of compound bump 262 increases the contact area along the longer aspect of FIGS. 12B and 12D without sacrificing the pitch between the bump and the conductive trace, ie, following the shorter aspect of FIGS. 12A and 12C. Mechanical interlocking between composite bumps 262 and conductive traces 268 maintains conductive traces during reflow, i.e., bumps and conductive traces do not lose contact. Thus, composite bump 262 in engagement with conductive trace 268 reduces bump interconnection failure.

13A-13D illustrate a BOL embodiment of a semiconductor die 224 with bump material 274 formed over contact pads 232, similar to FIG. 10C. In FIG. 13A, bump material 274 is generally compliant and undergoes plastic deformation greater than about 25 μm under force equivalent to a vertical load of about 200 g. Bump material 274 is wider than conductive trace 276 on substrate 278. Multiple protrusions 280 are formed on conductive trace 276 to a height of about 1-25 μm.

Semiconductor die 224 is positioned such that bump material 274 is parallel with interconnect sites on conductive traces 276. In addition, the bump material 274 may be side by side with conductive pads or interconnect sites formed in the substrate 278. Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 274 into the conductive trace 276 and the protrusion 280, as shown in FIG. 13B. Force F may be applied at a high temperature. Due to the docile nature of the bump material 274, the bump material is deformed or extruded around the top and sides of the conductive trace 276 and the protrusion 280. In particular, the application of pressure causes the bump material 274 to undergo plastic deformation and cover the top and side surfaces of the conductive trace 276 and the protrusion 280. The plastic flow of bump material 274 creates a macroscopic mechanical interlocking point between the bump material and the top and sides of conductive trace 276 and protrusion 280. Plastic flow of bump material 274 occurs around the top and sides of conductive traces 276 and protrusions 280 but does not extend excessively to substrate 278 which may cause electrical shorts and other defects. Mechanical interlocking between the bump material and the top and sides of the conductive traces 276 and protrusions 80 makes a strong connection through a large contact area between each surface without significantly increasing the bonding force. Mechanical interlocking between the bump material and the top and sides of the conductive traces 276 and the protrusions 280 also reduces lateral die shifting during subsequent manufacturing processes such as encapsulation.

13C illustrates another BOL embodiment with bump material 274 narrower than conductive trace 276. Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 274 into the conductive trace 276 and the protrusion 280. Force F may be applied at a high temperature. Due to the docile nature of the bump material 274, the bump material is deformed or extruded over the top surface of the conductive trace 276 and the protrusion 280. In particular, the application of pressure causes the bump material 274 to undergo plastic deformation and cover the top surface of the conductive trace 276 and the protrusion 280. The plastic flow of the bump material 274 creates a macroscopic mechanical interlocking point between the bump material and the top surface of the conductive trace 276 and the protrusion 280. Mechanical interlocking between the bump material and the top surfaces of the conductive traces 276 and the projections 280 makes a strong connection through a large contact area between each surface without significantly increasing the bonding force. Mechanical interlocking between the bump material and the top surface of the conductive trace 276 and the protrusion 280 also reduces lateral die shifting during subsequent manufacturing processes such as encapsulation.

FIG. 13D illustrates another BOL embodiment with bump material 274 formed over the edge of conductive trace 276, that is, bump material where a portion of the bump material is over the conductive trace and a portion of the bump material is not over the conductive trace. Doing. Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 274 into the conductive trace 276 and the protrusion 280. Force F may be applied at a high temperature. Due to the docile nature of the bump material 274, the bump material is deformed or extruded over the top and sides of the conductive trace 276 and the protrusion 280. In particular, the application of pressure causes the bump material 274 to undergo plastic deformation and cover the top and side surfaces of the conductive trace 276 and the protrusion 280. Plastic flow of bump material 274 creates macroscopic mechanical interlocking between the bump material and the top and sides of conductive trace 276 and protrusion 280. Mechanical interlocking between the bump material and the top and sides of the conductive traces 276 and protrusions 280 creates a strong connection through a large contact area between each surface without significantly increasing the engagement force. Mechanical interlocking between the bump material and the top and sides of the conductive traces 276 and the protrusions 280 also reduces lateral die shifting during subsequent manufacturing processes such as encapsulation.

14A-14C illustrate another BOL embodiment of semiconductor die 224 with bump material 284 formed over contact pads 232, similar to FIG. 10C. As shown in FIG. 14A, tip 286 extends from the body of bump material 284 as a stepped bump with a tip 286 narrower than the body of bump material 284. The semiconductor die 224 is positioned so that the bump material 284 is parallel with the interconnect sites on the conductive traces 288 of the substrate 290. In particular, tip 286 is centered over the interconnect sites of conductive traces 288. In addition, bump material 284 and tip 286 may be parallel with conductive pads or other interconnect sites formed on substrate 290. Bump material 284 is wider than conductive trace 288 on substrate 290.

Conductive traces 288 are generally compliant and undergo plastic deformation greater than about 25 μm under force equivalent to a vertical load of about 200 g. Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the tip 284 to the conductive trace 288. Force F can be applied at a high temperature. Due to the docile nature of the conductive traces 288, the conductive traces deform around the tip 286, as shown in FIG. 14B. In particular, the application of pressure causes the conductive trace 288 to undergo plastic deformation and cover the top and sides of the tip 286.

FIG. 14C shows another BOL embodiment with round bump material 294 formed over contact pads 232. Tip 296 extends from the body of bump material 294 to form a stud bump with a tip narrower than the body of bump material 294. The semiconductor die 224 is positioned such that the bump material 294 is parallel with the interconnect sites on the conductive traces 298 of the substrate 300. In particular, tip 296 is centered over the interconnect site of conductive trace 298. In addition, bump material 294 and tip 296 may be parallel to conductive pads or other interconnect sites formed on substrate 300. Bump material 294 is wider than conductive trace 298 on substrate 300.

Conductive traces 298 are generally compliant and undergo plastic deformation greater than about 25 μm under force equivalent to a vertical load of about 200 g. Pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the tip 296 to the conductive trace 298. Force F can be applied at a high temperature. Due to the docile nature of the conductive traces 298, the conductive traces deform around the tip 296. In particular, the application of pressure causes the conductive trace 298 to undergo plastic deformation and cover the top and sides of the tip 296.

The conductive traces described in FIGS. 11A-11G, 12A-12D and 13A-13D may also be compliant materials, as described in FIGS. 14A-14C.

15A-15B illustrate another BOL embodiment of semiconductor die 224 with bump material 304 formed over contact pads 232, similar to FIG. 10C. Bump material 304 is generally compliant and undergoes plastic deformation greater than about 25 μm under force equivalent to a vertical load of about 200 g. Bump material 304 is wider than conductive trace 306 on substrate 308. Conductive via 310 is formed through conductive trace 306 with opening 312 and conductive sidewall 314 as shown in FIG. 15A.

Semiconductor die 224 is positioned such that bump material 304 is parallel with the interconnect sites on conductive traces 306, see FIGS. 19A-19G. In addition, bump material 304 may be side by side with conductive pads or interconnect sites formed in substrate 308. Pressure or force F is applied to the rear face 228 of the semiconductor die 224 to press the bump material 304 into the conductive trace 306 and the opening 312 of the conductive via 310. Force F may be applied at a high temperature. Due to the docile nature of the bump material 304, the bump material is deformed or extruded around the top and sides of the conductive trace 306 and into the opening 312 of the conductive via 310. . In particular, the application of pressure causes the bump material 304 to undergo plastic deformation and to cover the top and side surfaces of the conductive trace 306 and the opening 312 of the conductive via 310. Bump material 304 is thus electrically connected to conductive trace 306 and conductive sidewall 314 for z-direction vertical interconnection through substrate 308. The plastic flow of bump material 304 creates a mechanical interlocking between the bump material and the top and side surfaces of the conductive trace 306 and the opening 312 of the conductive via 310. Mechanical interlocking between the bump material and the top and side surfaces of the conductive trace 306 and the opening 312 of the conductive via 310 creates a strong connection through a large contact area between each surface without significantly increasing the coupling force. . Mechanical interlocking between the bump material and the top and side surfaces of the conductive trace 306 and the opening 312 of the conductive via 310 also reduces lateral die shifting during subsequent manufacturing processes such as encapsulation. Since the conductive via 310 is formed in the interconnect site with the bump material 304, the overall substrate interconnect area is reduced.

11A-11G, 12A-12D, 13A-13D, 14A-14C, and 15A-15B, the conductive trace pitch is reduced by making the conductive trace narrower than the interconnect structure to reduce routing density and I / O count can be increased. The narrower conductive traces reduce the force F needed to deform the interconnect structure around the conductive traces. For example, the necessary force F may be 30-50% of the force required to deform the bump for a conductive trace or pad that is wider than the bump material. Lower compression forces F are useful for fine pitch interconnects and small dies to maintain coplanarity within a specific error range and achieve uniform -z direction deformation and high reliability interconnect unions. In addition, deforming the interconnect structure around the conductive traces mechanically locks the bumps to the traces to prevent shifting of the die or floating of the die during reflow.

 16A-16C illustrate a mold underfill (MUF) process for electrodepositing the encapsulant around the bump between the semiconductor die and the substrate. FIG. 16A illustrates a semiconductor die 224 mounted to a substrate 254 using the bump material 234 from FIG. 11B and positioned between the upper mold support 316 and the lower mold support 318 of the chase mold 320. It is shown. Other semiconductor die and substrate combinations from FIGS. 11A-11G, 12A-12D, 13A-13D, 14A-14C, and 15A-15B may be applied to the upper mold support 316 and the lower mold support of the chase mold 320. 318 may be located between. The upper mold support 316 includes a compressible release film 322.

In FIG. 16B, the upper mold support 316 and the lower mold support 318 are gathered together to enclose the semiconductor die 224 and the substrate 254 with open space over the substrate and between the semiconductor die and the substrate. The compressible release film 322 is arranged to coincide with the rear surface 228 and side surfaces of the semiconductor die 224 to prevent the formation of encapsulants in these spaces. While the liquid encapsulant 324 is injected into one side of the chase mold 320 using the nozzle 326, an optional vacuum assist 328 draws pressure from the opposite side and opens onto the substrate 254. The space and the open space between the semiconductor die 224 and the substrate 254 are uniformly filled with an encapsulant. Encapsulant 324 may be a polymer composite, such as an epoxy resin filler, an epoxy acrylate filler, or a suitable polymer filler. Encapsulant 324 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. Compressible material 322 prevents encapsulant 324 from flowing over and around the back surface 228 of semiconductor die 224. The encapsulant 324 is cured. The rear and side surfaces of the semiconductor die 224 remain exposed from the encapsulant 324.

FIG. 16C illustrates an embodiment of MUF and mold overfill (MOF), ie without compressible material 322. The semiconductor die 224 and the substrate 254 are positioned between the upper mold support 316 and the lower mold support 318 of the chase mold 320. The upper mold support 316 and the lower mold support 318 are gathered together to enclose the semiconductor die 224 and the substrate 254 with open spaces on the substrate, around the semiconductor die, and between the semiconductor die and the substrate. . While the liquid encapsulant 324 is injected into one side of the chase mold 320 using the nozzle 326, an optional vacuum assist 328 draws pressure from the opposite side and around the semiconductor die 224. The open space on the substrate 254 and the open space between the semiconductor die 224 and the substrate 254 are uniformly filled with an encapsulant. The encapsulant 324 is cured.

FIG. 17 illustrates another embodiment of depositing an encapsulant into a gap around semiconductor die 224 and between semiconductor die 224 and substrate 254. Semiconductor die 224 and substrate 254 are surrounded by dam 330. The encapsulant 332 is dispensed from the nozzle 334 into the dam 330 in a liquid state and filled into an open space on the substrate 254 and an open space between the semiconductor die 224 and the substrate 254. The volume of encapsulant 332 dispensed from the nozzle 334 is controlled to fill the dam 330 without covering the back surface 228 and side surfaces of the semiconductor die 224. The encapsulant 332 is cured.

FIG. 18 shows the semiconductor die 224 and the substrate 254 after the MUF process from FIGS. 16A, 16C, and 17. Encapsulant 324 is evenly distributed over substrate 224 and around bump material 234 between semiconductor die 224 and substrate 254.

19A-19G are top views of various conductive trace layouts on a substrate or PCB 340. In FIG. 19A, conductive trace 342 is a straight conductor with integrated bump pads or interconnect sites 344 formed on substrate 340. The sides of the substrate bump pads 344 may be collinear with the conductive traces 342. In the prior art, solder registration openings (SRO) are generally formed over the interconnect sites to receive bump material during reflow. SRO increases the interconnect pitch and decreases the I / O count. In contrast, masking layer 346 may be formed over a portion of substrate 340, but no masking layer is formed around substrate bump pad 344 of conductive trace 342. That is, the portion of the conductive trace 342 designed to engage the bump material lacks any SRO of the masking layer 346 that can be used for bump reception during reflow.

Semiconductor die 224 is positioned over substrate 340 and the bump material is arranged side by side with substrate bump pad 344. The bump material is electrically and metallicly connected to the substrate bump pad 344 by physically contacting it with the bump pad and then reflowing the bump material under a reflow temperature.

In another embodiment, the electrically conductive bump material is electrodeposited onto the substrate bump pad 344 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder with a selective flux solution and combinations thereof. For example, the bump material may be process Sn / Pb, high-lead solder or lead-free solder. The bump material is bonded to the substrate bump pad 344 using a suitable attach or bond process. In one embodiment, the bump material is reflowed by heating the bump material above its melting point to form the bump or interconnect 348, as shown in FIG. 19B. In some applications, bump 348 is reflowed twice to improve electrical contact with substrate bump pad 344. Bump material around the narrow substrate bump pad 344 maintains the die position during reflow.

In high routing density applications, it is desirable to minimize the escape pitch of conductive traces 342. The escape pitch between the conductive traces 342 can be reduced by removing the masking layer for reflow receiving purposes, ie by reflowing the bump material without the masking layer. Since no SRO is formed around die bump pad 232 or substrate bump pad 344, conductive trace 342 can be formed at a finer pitch, that is, conductive trace 342 is in close proximity to the structure. Or in its neighborhood. With no SRO around the substrate bump pads 344, the pitch between the conductive traces 342 is given by P = D + PLT + W / 2, where D is the base diameter of the bump 348, PLT is the die The position error, and W is the width of the conductive trace 342. In one embodiment, given a bump base diameter of 100 μm, a PLT of 10 μm, and a trace line width of 30 μm, the minimum escape pitch of conductive trace 342 is 125 μm. Mask-less bump formation eliminates the need for explanation of the retardation space of the masking material, solder mask registration error (SRT), and minimum resolvable SRO, as seen in the prior art. Remove it.

When the bump material is reflowed to connect the die bump pad 232 metallographically and electrically to the substrate bump pad 344 without a masking layer, the wetting and surface tension causes the bump material to self-cone. Held in a confinement state and retained in the portion of the substrate 340 immediately adjacent to the conductive trace 342 in the space between the die pump pad 232 and the substrate bump pad 344 and in the footprint of the bump pad. .

In order to achieve the desired self-confinement properties, the bump material may be formed using a die bump pad 232 or a substrate bump pad (ie, to make the area in contact with the bump material more wettable than the surrounding area of the conductive trace 342). 344 may be impregnated with the flux solution before being placed. The molten bump material remains limited within the area defined by the bump pads due to the wetting properties of the flux solution. The bump material does not proceed to areas that are less wettable. An oxide layer or other insulating layer of the thin film may be formed over an area that the bump material was not intended to make less wet. For this reason, masking layer 340 is not needed around die pump pad 232 or substrate bump pad 344.

FIG. 19C illustrates another embodiment of a parallel conductive trace 352 as a straight conductor with integrated rectangular bump pads or interconnect sites 354 formed on the substrate 350, similar to FIG. 7B. In this case, the substrate bump pads 354 are wider than the conductive traces 342 and less than the width of the engagement bumps. Sides of the substrate bump pad 354 may be parallel to the conductive trace 352. Although masking layer 356 may be formed over a portion of substrate 350, masking layer is not formed around substrate bump pad 354 of conductive trace 352. That is, the portion of the conductive trace 352 that is designed to engage the bump material lacks any SRO of the masking layer 356 that can be used for bump reception during reflow.

19D illustrates another embodiment of conductive traces 360 and 362 arranged in an array of multi rows with offset integrated bump pads or interconnect sites 364 formed on substrate 366 for maximum interconnect density and capacity. It is shown. Alternate conductive traces 360 and 362 include elbows for routing to bump pads 364. Sides of each substrate bump pad 364 are collinear with the conductive traces 360 and 362. Although masking layer 368 may be formed on a portion of substrate 366, masking layer 368 is not formed around substrate bump pads 364 of conductive traces 360 and 362. That is, portions of the conductive traces 360,362 designed to engage the bump material lack any SRO of the masking layer 368 that can be used for bump reception during reflow.

19E illustrates another embodiment of conductive traces 370 and 372 arranged in an array of multi rows with offset integrated bump pads or interconnect sites 374 formed on substrate 376 for maximum interconnect density and capacity. It is shown. Alternate conductive traces 370 and 372 include elbows for routing to bump pads 374. In this case, the substrate bump pad 374 is rounded and wider than the conductive traces 370, 372, but less than the width of the engagement interconnect bump material. Although masking layer 378 may be formed on a portion of substrate 376, masking layer 378 is not formed around substrate bump pads 374 of conductive traces 370 and 372. That is, portions of the conductive traces 370 and 372 that are designed to engage the bump material lack any SRO of the masking layer 378 that can be used for bump reception during reflow.

 19F illustrates another embodiment of conductive traces 380 and 382 arranged in an array of multi rows with offset integrated bump pads or interconnect sites 384 formed on a substrate 386 for maximum interconnect density and capacity. It is shown. Alternate conductive traces 380 and 382 include elbows for routing to bump pads 384. In this case, the substrate bump pad 384 is rectangular and wider than the conductive traces 380, 382, but less than the width of the engagement interconnect bump material. Masking layer 388 may be formed over a portion of substrate 386, but masking layer 388 is not formed around substrate bump pads 384 of conductive traces 380 and 382. That is, portions of conductive traces 380 and 382 that are designed to engage the bump material lack any SRO of masking layer 388 that can be used for bump reception during reflow.

As an example of an interconnect process, semiconductor die 224 is positioned over substrate 366 and bump material 234 is parallel with substrate bump pad 364 from FIG. 19D. The bump material 234 may be pressurized or physically contacted with the bump pad, as described in FIGS. 11A-11G, 12A-12D, 13A-13D, 14A-14C, and 15A-15B. Reflowing the bump material under the reflow temperature is electrically and metallically coupled to the substrate bump pad 364.

In another embodiment, the electrically conductive bump material is electrodeposited onto the substrate bump pad 364 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder with a selective flux solution and combinations thereof. For example, the bump material may be eutectic Sn / Pb, high-lead solder or lead-free solder. The bump material is bonded to the substrate bump pad 364 using a suitable attach or bond process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form the bump or interconnect 390, as shown in FIG. 19G. In some applications, bump 390 is reflowed twice to improve electrical contact with substrate bump pad 364. Bump material around the narrow substrate bump pad 364 maintains the die position during reflow. Bump material 234 or bump 390 may also be formed on the substrate bump pad structure of FIGS. 19A-19G.

In high routing density applications, it is desirable to minimize the escape pitch of conductive traces 360,362 or other conductive trace configurations of FIGS. 19A-19G. The escape pitch between conductive traces 360 and 362 can be reduced by removing the masking layer for reflow receiving purposes, ie by reflowing the bump material without the masking layer. Since no SRO is formed around the die bump pad 232 or the substrate bump pad 364, the conductive traces 360, 362 can be formed at a finer pitch, that is, the conductive traces 360, 362 are in close proximity to the structure. Or in its neighborhood. With no SRO around the substrate bump pad 364, the pitch between the conductive traces 360, 362 is given by D / 2 + PLT + W / 2, where D is the base diameter of the bump 390, PLT is Die position error, and W is the width of the conductive traces 360,362. In one embodiment, given a bump base diameter of 100 μm, a PLT of 10 μm, and a trace line width of 30 μm, the minimum escape pitch of the conductive traces 360, 362 is 75 μm. Mask-less bump formation eliminates the need for descriptions of the retardation space of the masking material, solder mask registration (SRT), and minimum resolvable SRO, as seen in the prior art. Let's do it.

When the bump material is reflowed to connect the die bump pad 232 metallographically and electrically to the substrate bump pad 364 without a masking layer, the wetting and surface tension may cause the bump material to self-cone. It is held in a confinement state and is retained in the space between the die pump pad 232 and the substrate bump pad 364 and in the portion of the substrate 366 directly adjacent to the conductive traces 360,362 in the bump pad footprint.

In order to achieve the desired self-confinement properties, the bump material may be formed using a die bump pad 232 or a substrate bump pad (ie, to make the area in contact with the bump material more wettable than the surrounding area of the conductive traces 360,362). 364) may be impregnated with the flux solution before being placed. The molten bump material remains limited within the area defined by the bump pads due to the wetting properties of the flux solution. The bump material does not proceed to areas that are less wettable. An oxide layer or other insulating layer of the thin film may be formed over an area that the bump material was not intended to make less wet. For this reason, masking layer 368 is not needed around die pump pad 232 or substrate bump pad 364.

In FIG. 20A, masking layer 392 is electrodeposited over a portion of conductive traces 394 and 396. However, the masking layer 392 is not formed over the integrated bump pads 398. As a result, there is no SRO for each bump pad 398 on the substrate 400. A non-wetting masking patch 402 is formed on the substrate 400 in an intrusive manner within the array of integrated bump pads 398, that is, between adjacent bump pads. Masking patch 402 may also be formed on semiconductor die 224 intrusive within an array of die bump pads 232. In particular, masking patches are formed proximate to the integrated bump pads in some arrangements to prevent progression to less wettable areas.

Semiconductor die 224 is positioned over substrate 400 and the bump material is parallel with substrate bump pad 398. The bump material may be pressurized or physically contact the bump material with the bump pad and then the bump material as described in FIGS. 11A-11G, 12A-12D, 13A-13D, 14A-14C and 15A-15B. Reflow under reflow temperature is electrically and metallically coupled to the substrate bump pad 398.

In another embodiment, electrically conductive bump material is electrodeposited onto die integrated bump pad 398 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder with a selective flux solution and combinations thereof. For example, the bump material may be process Sn / Pb, high-lead solder or lead-free solder. The bump material is bonded to the integrated bump pad 398 using a suitable attach or join process. In one embodiment, the bump material is reflowed by heating the bump material above its melting point to form a spherical ball or bump 404, as shown in FIG. 20B. In some applications, bump 404 is reflowed twice to improve electrical contact with integrated bump pad 398. The bump may also be press coupled to the integrated bump pad 398. Bump 404 represents a form of interconnect structure that may be formed over integrated bump pad 398. The interconnect structure may also be stud bumps, micro bumps or other electrical interconnects.

In high routing density applications, it is desirable to minimize the escape pitch. To reduce the pitch between conductive traces 394 and 396, the bump material is reflowed around the integrated bump pad 398 without a masking layer. The escape pitch between the conductive traces 394 and 396 can be reduced by eliminating the masking layer for reflow acceptance purposes and the associated SRO around the integrated bump pad, ie by reflowing the bump material without the masking layer. Masking layer 392 may be formed over a portion of substrate 400 away from conductive traces 394 and 396 and integrated bump pad 398, but masking layer 392 is not formed around integrated bump pad 298. That is, portions of conductive traces 394 and 396 designed to engage bump material lack any SRO of masking layer 392 that can be used for bump reception during reflow.

In addition, a masking patch 402 is formed on the substrate 400 intrusive within the array of the contact bump pads 398. Masking patch 402 is a non-wetting material. Masking patch 402 may be the same material as masking layer 392 and may be applied during the same process step or may be a different material and during different process steps. Masking patch 402 may be formed by selective oxidation, plating, or other processing of traces or pad portions within an array of integrated bump pads 398. Masking patch 402 restricts bump material flow to integrated bump pad 398 to prevent leaching of conductive bump material into adjacent structures.

When the bump material is reflowed with masking patches 402 intrusively positioned within the array of integrated bump pads 398, the wet and surface tension causes the bump material to die die pad 232 and integrated bump pad. It is defined and retained in the space between the 398 and immediately adjacent the conductive traces 394 and 396 and in the portion of the substrate 400 in the footprint of the integrated bump pad 398.

 In order to achieve the desired confinement properties, the bump material die die pad 232 or integrated bump pad 398 to selectively make the area in contact with the bump material more wetted than the surrounding area of the conductive traces 394 and 396. Can be impregnated with the flux solution prior to being placed in. The molten bump material remains limited within the area defined by the bump pads due to the wetting properties of the flux solution. The bump material does not proceed to areas that are less wettable. An oxide layer or other insulating layer of the thin film may be formed over an area that the bump material was not intended to make less wet. For this reason, masking layer 392 is not needed around die pump pad 232 or integrated bump pad 398.

Since no SRO is formed around die bump pad 232 or integrated bump pad 398, conductive traces 394 and 396 can be formed at finer pitches, i.e., conductive traces without contact and without electrical short formation. May be placed proximate to an adjacent structure. Assuming the same solder registration design rule, the pitch between conductive traces 394 and 396 is given by P = (1.1D + W) / 2, where D is the base diameter of bump 404 and W is the conductive trace 394 and 396. ) Width. In one embodiment, given a bump diameter of 100 μm and a trace line width of 20 μm, the minimum escape pitch of the conductive traces 394, 396 is 65 μm. Bump formation eliminates the need for explanation of the minimum resolvable SRO and the regument space of the masking material between adjacent openings, as can be seen in the prior art.

FIG. 21 shows a package-on-package (PoP) 405 with a semiconductor die 406 loaded onto the semiconductor die 408 using a die attach assist 410. Each of the semiconductor dies 406 and 408 includes an active surface comprising analog and digital circuits formed as active elements, passive elements, conductive layers, and insulating layers that are formed and electrically interconnected within the die in accordance with the electrical design and function of the die. Has For example, the circuit may include one or more transistors, diodes, and other circuit elements formed in an active surface for implementing an analog or digital circuit, such as a DSP, ASIC, memory, or other signal processing circuit. Semiconductor dies 406 and 408 may also include IPDs such as inductor capacitors and resistors for RF signal processing.

Semiconductor die 406 may be formed using bump material 416 formed on contact pad 418 using any embodiment from FIGS. 11A-11G, 12A-12D, 13A-13D, 14A-14C, or 15A-15B. It is mounted to a conductive trace 412 formed on the substrate 414. Conductive trace 412 is applicable to an interconnect structure in which no SRO is present as shown in FIGS. 6-9. The semiconductor die 408 is electrically connected to the contact pads 420 formed on the substrate 414 using bond wires 422. Opposite ends of the bond wires 422 are coupled to the contact pads 424 on the semiconductor die 406.

Masking layer 426 is formed over substrate 414 and opens beyond the footprint of semiconductor die 406. The masking layer 426 does not limit the bump material 416 to the conductive traces 412 during reflow, but the open mask acts as a dam so that the encapsulant 428 may contact the contact pads 420 or bond wires 422 during the MUF. To prevent migration). Encapsulant 428 is electrodeposited between semiconductor die 408 and substrate 414, similar to FIGS. 16A-16C. The masking layer 426 blocks the MUF encapsulant 428 from reaching the contact pads 420 and the bond wires 422, which can result in defects. Masking layer 426 ensures that encapsulant 428 does not fall into contact pad 420 and that a larger semiconductor die is placed on a given substrate.

While one or more embodiments of the invention have been described in detail, those skilled in the art will understand that modifications and adaptations can be made to the embodiments without departing from the scope of the invention as set forth in the following claims.

Claims (25)

Providing a semiconductor die having a die bump pad;
Providing a substrate having a conductive trace with interconnect sites;
Electrodepositing a conductive bump material on the interconnect site or the die bump pad;
Mounting the semiconductor die to the substrate such that the conductive bump material is disposed between the die bump pad and an interconnect site;
Reflowing the conductive bump material around the die bump pad or the interconnect site without a solder mask to form an interconnect structure between the semiconductor die and the substrate, wherein the conductive bump material is in the die bump pad or interconnect site. Self-confined in; And
Electrodepositing an encapsulant between the semiconductor die and the substrate. The method of claim 1,
And impregnating the conductive bump material into a flux solution to increase wettability. The method of claim 1,
Forming an insulating layer on the die bump pad or the peripheral region of the interconnect site to make an area less wet than the die bump pad and the interconnect site. The method of claim 1,
Of conductive bump material electrodeposited between the die bump pad and the interconnect site such that a surface tension maintains a self-confinement of the conductive bump material within the footprint of the die bump pad and the interconnect site. The method of manufacturing a semiconductor device further comprising the step of selecting the amount. The method of claim 1,
And wherein said interconnect structure comprises a soluble portion and a non-soluble portion. The method of claim 1,
The interconnect structure includes a conductive pillar and a bump formed on the conductive pillar. Providing a first semiconductor structure having a first interconnect site;
Providing a second semiconductor structure having a second interconnect site;
Electrodepositing a conductive bump material between the first and second interconnect sites;
Forming an interconnect structure from the conductive bump material to couple around the first and second interconnect sites without the first and second semiconductor structure solder masks, wherein the conductive bump material is formed on the first and second interconnects. Self-confined within the access site; And
Electrodepositing an encapsulant between the first and second semiconductor structures. The method of claim 7, wherein
And impregnating the conductive bump material into a flux solution to increase wettability. The method of claim 7, wherein
Forming an insulating layer on a peripheral region of the first interconnect site or the second interconnect site to make the region less wet than the first and second interconnect sites. . The method of claim 7, wherein
Conductive bumps electrodeposited between the first and second interconnect sites such that surface tension maintains self-confinement of the conductive bump material within the footprint of the first and second interconnect sites The method of manufacturing a semiconductor device further comprising the step of selecting the amount of material. The method of claim 7, wherein
Wherein the interconnect structure covers a top surface and a side surface of the first interconnect site or the second interconnect site. The method of claim 7, wherein
And wherein said interconnect structure comprises a soluble portion and a non-soluble portion. The method of claim 7, wherein
The interconnect structure includes a conductive pillar and a bump formed on the conductive pillar. Providing a first semiconductor structure having a first interconnect site;
Providing a second semiconductor structure having a second interconnect site;
Electrodepositing a conductive bump material over the first interconnect site or the second interconnect site; And
Forming an interconnect structure from the conductive bump material to couple the first and second semiconductor structures around the first and second interconnect sites without a solder mask. The method of claim 14,
And depositing an encapsulant between the first and second semiconductor structures. The method of claim 14,
And impregnating the conductive bump material into a flux solution to increase wettability. The method of claim 14,
Forming an insulating layer on a peripheral region of the first interconnect site or the second interconnect site to make the region less wet than the first and second interconnect sites. . The method of claim 14,
Selecting an amount of conductive bump material deposited on the first interconnect site or the second interconnect site such that surface tension maintains self-confinement of the conductive bump material. Method of manufacturing a semiconductor device. The method of claim 14,
Wherein the interconnect structure covers a top surface and a side surface of the first interconnect site or the second interconnect site. The method of claim 14,
And wherein said interconnect structure comprises a soluble portion and a non-soluble portion. A first semiconductor structure having a first interconnect site;
A second semiconductor structure having a second interconnection site;
An interconnect structure formed between the first and second semiconductor structures without a solder mask around the first and second interconnect sites; And
And a sealing material electrodeposited between the first and second semiconductor structures. The method of claim 21,
And an insulating layer formed on the peripheral region of the first interconnect site or the second interconnect site to make the region less wet than the first and second interconnect sites. The method of claim 21,
The interconnect structure covers a top surface and a side surface of the first interconnect site or the second interconnect site. The method of claim 21,
The interconnect structure includes a soluble portion and a non-soluble portion. The method of claim 21,
And the interconnect structure includes a conductive pillar and a bump formed over the conductive pillar.
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