KR101794353B1 - Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings - Google Patents

Abstract

The semiconductor device has a semiconductor die having a plurality of bumps formed on the surface of the semiconductor die. Multiple conductive traces are formed on the substrate surface with interconnect sites. A masking layer is formed on the substrate surface. The masking layer has a plurality of parallel and elongated openings each of which exposes at least two of the conductive traces and allows flow of the bump material along the length of the plurality of conductive traces in the plurality of elongated openings, Thereby preventing the flow of the bump material through the opened aperture boundary. One of the conductive traces passes under at least two of the elongated openings. The bumps are coupled to the interconnect sites such that the bumps cover the top and sides of the interconnect sites. An encapsulant is electrodeposited between the semiconductor die and the interconnection site of the substrate.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

The present invention relates to a method of forming on a substrate narrow interconnection sites having semiconductor elements, in particular semiconductor elements and elongated mask openings.

Semiconductor devices are commonly used in modern electronics. Semiconductor devices are variable in number and density of electrical components. Discrete semiconductor devices generally include one form of electrical components: light emitting diodes (LEDs), small signal transistors, resistors, capacitors, inductors, and MOS field effect transistors (MOSFETs). Integrated semiconductor devices typically include hundreds to millions of electrical components. Examples of the integrated semiconductor device include a microcontroller, a microprocessor, a charge-coupled device (CCD), a solar cell, and a digital micro-mirror device (DMD).

Semiconductor devices perform a wide range of functions such as signal processing, high-speed computation, sending and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electric arc furnaces, and forming visual projections for television displays. Semiconductor devices are used in the fields of entertainment, communications, power conversion, networks, computers and consumer products. Semiconductor devices are also used in military applications, aviation, automotive, industrial controllers and office equipment.

Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of the semiconductor material doubles its electrical conductivity through the application of an electric field or base current or through a doping process. Doping introduces impurities into the semiconductor material to double or control the conductivity of the semiconductor device.

Semiconductor devices include active and passive electrical structures. The active structure, including bipolar and field effect transistors, controls the flow of current. By doping and varying the level of the field effect or base current, the transistor will either promote or limit current flow. Passive structures, including resistors, capacitors, and inductors, create a correlation between voltage and current required to perform various electrical functions. The active and passive structures are electrically connected to form a circuit, which allows the semiconductor device to perform high-speed calculations and other useful functions.

Semiconductor devices are typically fabricated using two composite manufacturing processes, a front-end process and a back-end process, each potentially involving hundreds of steps. The front-end fabrication includes forming a plurality of dies on a semiconductor wafer surface. Each die is basically the same and includes a circuit formed by electrically connecting active and passive components. The back-end fabrication includes singulating each die from the final wafer and packaging the die to provide structural support and environmental isolation.

One purpose of semiconductor fabrication is to produce smaller semiconductor devices. Smaller semiconductor devices consume less power, have higher performance, and can be manufactured more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller final products. Smaller die sizes can be achieved by improving the front-end process resulting in smaller, high density active and passive die. The back-end process can result in a semiconductor device package with a smaller footprint due to improvements in electrical interconnection and material packaging.

In a typical flip chip type package, the semiconductor die is mounted to the package substrate with the active side of the die in contact with the substrate. Typically, interconnecting the die circuitry to the substrate circuit is accomplished via bumps attached to a plurality of interconnecting pad arrays and coupled to a corresponding complementary array of interconnecting pads, often referred to as capture pads on the substrate.

The areal density of electrical features on integrated circuits is greatly increasing, and semiconductor dies with greater density of circuit features may also have a greater density of sites for interconnections with the package substrate.

The package is connected to a lower circuit such as a printed circuit or a motherboard via a second level interconnect between the package and the lower circuit. The second level interconnect has a larger pitch than the flip chip interconnect, and routing on the substrate is typically unfolded. Large technological advances enable fine line and space configurations. The space between adjacent pads limits the number of traces than can escape from the inner capture pads of the array. Fan-out routing between the capture pads under the die and the package outer pins is typically formed on multiple metal layers within the package substrate. For complex interconnect arrays, a substrate with multiple layers may be required to achieve routing between the die pad and the second level interconnects on the package.

Multiple layer substrates are expensive, and in a conventional flip chip construction, the substrate itself accounts for more than half of the package cost. The high cost of multi-layer substrates has been a limiting factor in the diffusion of flip chip technology in mainstream products. The escape routing pattern typically introduces additional electrical parasitics because the routing includes vias between the interconnect layers in the short run and signal propagation patches of the unshielded interconnect. Electrical parasitics largely limit package performance.

In some typical processes, the flip chip interconnects contact the corresponding interconnect sites on the substrate circuit with bumps or balls of semiconductors or more, and heat the solder bumps themselves or the solder bumps themselves to reflow, It is done by making. In such a process, the molten solder flows from the interconnect site along the metal of the circuit to deplete the solder at its connection site, and when the bump collapses under reflow conditions, the bump contacts the adjacent circuit, Resulting in an electrical failure. To avoid these problems, the solder is formed as an insulating layer overlying the patterned metal layer of the die mounting surface of the substrate, and is con fi need by a solder mask with openings that expose interconnection sites on the lower circuit. The process limitations in patterning the solder mask prevent reliable formation of well-aligned and uniformly sized openings, and thus, when a solder mask is used, the fine circuitry that may be required for finer pitch interconnections Substrates with feature dimensions can not be obtained.

The interconnect pitch in conventional flip chip interconnects is partially limited by the capture pad dimensions on the substrate. Capture pads are typically much wider than connection circuit elements. Recently, flip chip substrate circuit designs have been known in which a reliable interconnect is made on the narrow circuit elements on the substrate, and the two designs referred to here, i.e., the bumps described in U.S. Patent Application Publication No. 20060216860 On-lead (BON) interconnect and a bump-on-lead (BOL) interconnect described in U.S. Patent Application Publication No. 20050110164. When conventional solder masks are used, the limitations in the process for patterning solder masks can limit the pitch reduction even in some BONP or BOL substrate configurations. The bondable surface of the exposed leads can be contaminated or covered by the solder mask residue, resulting in an incomplete solder joint. The engageable surfaces of the leads are inconsistent or partially exposed at the interconnect sites, resulting in unreliable and inconsistent trace structures.

 Conventional flip chip interconnections are made using a melting process that joins the bumps onto the engagement surfaces of corresponding interconnect sites of the patterned metal layer at the die attach side of the substrate. If the site is a capture pad, the interconnect is known as a bump-on-capture pad (BOC) interconnect. In the BOC design, a relatively large capture pad is required to engage the bumps above the semiconductor. In some flip chip interconnects, an insulating material or solder mask is required to conform the solder flow during the interconnect process. The soldermask opening is defined as defining a molten solder contour in the capture pad, i. E. Solder mask confinement, or solder contour is not defined by the mask opening, i. E. Non-solder mask confinement. In the latter case, the solder mask opening is much larger than the capture pad. The capture pad must be large, typically larger than the design size of the mask opening, to ensure that the mask opening is located at the engagement surface of the pad, because the technique of defining the solder mask opening has a wide tolerance range for the solder mask confined bump configuration . For a non-solder mask confined bump configuration, the solder mask opening must be larger than the capture pad. The capture pad width or diameter may be 2-4 times wider than the trace width. The larger width of the capture pad results in a significant loss of routing space on the top substrate layer. In particular, the escape routing pitch is much larger than the finest trace pitch that the substrate technology can provide. A large number of pads must be routed on the lower substrate layers, often by short stubs and via means, below the die footprint, which diverges from the pad of interest.

1-3 illustrate aspects of a conventional flip chip interconnection using a solder mask. Figure 1 is a schematic cross-section of the substrate 12 viewed in a plane parallel to the substrate surface. Some features were shown as transparent. Substrate 12 includes an insulating layer that supports the metal layer of the die attach surface and forms a circuit that lies beneath the solder mask. The circuit includes leads or traces 15 exposed to interconnect sites 19 by openings 18 in solder mask 16, as shown in FIG. Conventional solder masks may have a nominal mask opening diameter in the range of 80-90 占 퐉. The solder mask material is degradable at such pitches, and in particular, the substrates can be manufactured relatively inexpensively with a solder mask having a 90 [micro] m opening and an alignment error of plus or minus 25 [mu] m. In some embodiments, a laminate substrate such as a 4-metal layer laminate manufactured in accordance with standard design rules is used. The trace 15 has a pitch of about 90 microns and the narrow pad is located in an area array of 270 microns providing an effective escape pitch of about 90 microns across the die footprint edge, as indicated by the dashed line 11.

3, the interconnection of the semiconductor die 34 onto the substrate 12 is accomplished by interconnecting the interconnection sites 19 of the narrowed leads or traces 15 patterned on the insulating layer on the die attach side of the substrate 12. [ To directly engage the bumps 35 with the bumps 35. [ In this example, there is no pad, and the solder mask 16 limits the flow of solder within the boundaries of the mask opening 18 and prevents the flow of solder away from the interconnect sites along the solder- . The solder mask also confines the flow of molten solder between the leads during the assembly process. However, the density of the flip chip interconnects in which the solder mask is required is limited by the process capability of the solder mask patterning process.

The underfill material 37 between the active side of the semiconductor die 34 and the solder mask 16 on the substrate 12 protects the interconnects and mechanically stabilizes the assembly. The underfill material 37 may be a curable resin plus filler, which may be a particulate material such as silica or aluminum particles. The special resin and filler as well as some of the filler in the resin provide adequate mechanical and adhesion properties to the underfill material 37 during both the process and in the resulting underfill. The underfill material 37 is applied between the interconnect sites 19 on the substrate 12 and the bumps 35 on the semiconductor die 34 by applying a liquid underfill material to the narrow pads between the die and the substrate near the die edge. After the interconnections are made. The underfill material 37 is allowed to flow through the capillary action space by the capillary action, which is referred to as capillary underfill. The underfill material 37 may also be formed by applying a large amount of underfill material to the active side of the semiconductor die 34 or to the solder mask 16 over the substrate 12 and then moving the die toward the substrate to form bumps 35. [ To the interconnection site 19, which is referred to as a non-flow underfill.

Figures 4 and 5 illustrate aspects of conventional flip chip interconnection without the use of solder masks. Figure 4 is a schematic, partial cross-sectional view of the package assembly viewed in a plane parallel to the substrate surface, along line 4-4 'in Figure 5; Some features were shown as transparent. Fig. 5 is a partial cross-section of the package in Fig. 4 viewed in a plane perpendicular to the plane of the package substrate surface along line 5-5 'in Fig.

4 shows an escape routing pattern of a substrate 42 arranged about a semiconductor die in which the die attach pads are located in a parallel column array near the die. The patterned traces or leads 43 are routed according to a complementary pattern to the array of bumps 45 above the semiconductor die. BOL interconnects are formed on each interconnection site 40 of the narrow leads or traces 43 on the substrate 42 of the complementary array near the die footprint edge, Direct engagement. The leads 43 are formed by patterning the metal layer on the die attach surface of the insulating layer of the substrate 42. [ The electrical interconnection of the semiconductor die 46 is accomplished by joining the bumps 45 formed on the die active side interconnect pads on the interconnect sites 40, as shown in FIG. A portion of the escape trace 43 is routed across the substrate 42 in a row passing between the bumps 45 and toward the interior of the die footprint.

In the absence of a solder mask, a molten bump material is con fi need by a non-collapsible bump with solder on the interconnect site. In addition, the encapsulated resin adhesive is used in a non-flow underfill process to condense the solder flow during the melting phase of the interconnection process. The non-flow underfill material is applied before the semiconductor die 46 and the substrate 42 are gathered together. The non-flowing underfill material is displaced by the approach to the interconnection site 40 of the bump 45 and the opposing faces of the die and substrate. Adhesive material for the non-flowing underfill material can be a fast-gelling attachment material, or other material, that is sufficiently gelled at a gel temperature for a time of one to two seconds.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a conventional flip chip package substrate with a solder mask parallel to the plane of the package substrate surface.
Figure 2 shows a typical flip chip package substrate with a solder mask, perpendicular to the plane of the package substrate surface.
Figure 3 shows a conventional flip chip assembly with a semiconductor die interconnected on a substrate.
4 illustrates flip chip interconnections of a semiconductor die on a substrate in the absence of a solder mask;
Figure 5 illustrates a semiconductor die mounted to a substrate in the absence of a solder mask as shown in Figure 4;
Figure 6 shows a PCB with different types of packages mounted on its surface;
Figures 7a-7c show other details of a representative semiconductor package mounted on a PCB.
8 shows a flip chip package substrate with a solder mask having an elongated opening parallel to the plane of the package substrate surface.
Figure 9 shows the flip chip interconnect of Figure 8 using a solder mask with an elongated opening perpendicular to the plane of the package substrate surface;
10 illustrates a flip chip assembly with semiconductor die interconnected on a substrate, such as in FIGS. 8 and 9. FIG.
11A-11H illustrate various interconnect structures formed over a semiconductor die for coupling to conductive traces on a substrate.
Figures 12A-12G illustrate a semiconductor die and interconnect structure coupled to a conductive trace.
Figures 13A-13D illustrate a semiconductor die with a wedge-shaped interconnect structure coupled to a conductive trace.
Figures 14A-14D illustrate another embodiment of a semiconductor die and interconnect structure coupled to a conductive trace.
Figures 15A-15C illustrate a stepped bump and stud bump interconnect structure coupled to a conductive trace.
16A-16B illustrate a conductive trace with conductive vias.
17A-17C illustrate mold underfills between a semiconductor die and a substrate.
Figure 18 illustrates another mold underfill between a semiconductor die and a substrate.
19 illustrates a semiconductor die and a substrate after mold underfill.
20A-20G illustrate various arrangements of conductive traces with open solder registration;
Figures 21A-21B illustrate an open solder registration with patches between conductive traces.
Figure 22 illustrates a POP with a masking layer dam to limit the encapsulant during mold underfill.

There is a need to minimize the escape pitch of the trace lines for higher routing density. Thus, in one embodiment, the present invention is directed to a method of manufacturing a semiconductor device comprising: providing a semiconductor die having a plurality of bumps formed on a surface of the semiconductor die; Providing a substrate; A plurality of elongated apertures exposing at least two of the conductive traces and allowing flow of the bump material along a length of the plurality of conductive traces within the plurality of elongated apertures, Forming a masking layer on the surface of the substrate to prevent flow of bump material through the openings of the openings; Coupling the bump to the interconnect site such that the bump covers a top surface and a side surface of the interconnect site; And depositing an encapsulant around the bumps between the semiconductor die and the substrate.

In another embodiment, the present invention is directed to a method of manufacturing a semiconductor device, the method comprising: providing a semiconductor die; Providing a substrate; Forming a plurality of conductive traces having interconnect sites on the surface of the substrate; Forming a masking layer over the surface of the substrate, the masking layer including a plurality of elongated apertures exposing at least two of the conductive traces; Forming a plurality of interconnect structures between interconnecting sites of the semiconductor die and the substrate; And electrodepositing an encapsulant between the semiconductor die and the substrate.

In another embodiment, the present invention is directed to a method of manufacturing a semiconductor device, the method comprising: providing a semiconductor die; Providing a substrate; Forming a plurality of conductive traces having interconnect sites on a surface of the substrate; Forming a masking layer over the surface of the substrate, the masking layer including a plurality of elongated openings exposing at least two of the conductive traces; And forming a plurality of the interconnecting structures between the interconnecting sites of the semiconductor die and the substrate such that the interconnecting structures cover the top and sides of the interconnecting sites.

In another embodiment, the present invention provides a semiconductor die comprising: a semiconductor die; A substrate having interconnect sites and having a plurality of conductive traces formed on the surface of the substrate; A masking layer formed over the surface of the substrate, the masking layer including a plurality of elongated openings exposing at least two of the conductive traces; A plurality of interconnect structures formed between the interconnecting sites of the semiconductor die and the substrate; And an encapsulating material electrodeposited between the semiconductor die and the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS The invention is described in more detail in one or more embodiments of the following description with reference to the drawings in which like reference numerals refer to the same or similar elements. Although the present invention is described in terms of the best modes for attaining the objects of the invention, those skilled in the art will recognize that the spirit and scope of the present invention as defined by the appended claims and the equivalents Variations and equivalents that may be included within the scope of the appended claims.

Semiconductor devices are generally fabricated using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end fabrication includes forming a plurality of dies on a semiconductor wafer surface. Each die on the wafer includes active and passive electrical components, which are electrically connected to form a functional electrical circuit. Active electronic components such as transistors and diodes have the ability to control current flow. Passive electrical components such as capacitors, inductors, resistors and transformers form the relationship between voltage and current required to perform electrical circuit functions.

The active and passive components are formed on a semiconductor wafer surface by a series of process steps including doping, electrodeposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process transforms the electrical conductivity of the semiconductor material in the active device, transforms the semiconductor material into an insulator or conductor, or dramatically changes the conductivity of the semiconductor material in response to an electric field or a base current. The transistor includes regions of varying degrees and types of doping arranged to be necessary for the transistor to facilitate or limit current flow in response to application of an electric field or base current.

The active and passive components are formed by layers of material having different electrical properties. The layers can be formed by various electrodeposition techniques, which are determined in part by the type of electrodeposited material. For example, thin film electrodeposition includes chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating processes. Each layer is generally patterned to form active parts, passive parts and portions of the electrical connection therebetween.

The layers are patterned using photolithography, which involves electrodepositing a photosensitive material, i. E., Photoresist, over the patterned layer. One pattern moves from the photomask to the photoresist using light. The portions of the photoresist pattern that are exposed to light are removed using a solvent, and the lower layer to be patterned is exposed. The remainder of the photoresist is removed leaving behind the patterned layer. In addition, some forms of the material are patterned by direct electrodeposition of the material into regions or voids formed by prior electrodeposition / etching processes that utilize techniques such as electroless and electrolytic plating.

Electrodeposition of a thin film of material onto an existing pattern can degrade the underlying pattern and form a non-uniform flat surface. A uniform flat surface is required to make smaller packed active and passive components. Planarization can be used to remove material from the wafer surface and create a uniform flat surface. The planarization includes a step of polishing the wafer surface with a polishing pad. During polishing, wear and corrosion chemicals are added to the wafer surface. The combined mechanical action of chemical abrasion and erosion removes any irregular shapes to create a uniform flat surface.

Back-end fabrication refers to packaging the die for structural support and environmental isolation after cutting and singulating the final wafer into individual die. To singulate the die, the wafer is stripped and crushed along the non-functional area of the wafer, referred to as the saw street or scribe. The wafer is singulated using a laser cutting tool or saw blade. After singulation, each die is mounted on a package substrate comprising pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contact pads in the package. Electrical connections may be made of solder bumps, stud bumps, conductive paste or wire bonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The final package is then inserted into the electrical system and the function of the semiconductor device is exerted to other system components.

Figure 6 shows an electronic device 50 having a chip carrier substrate or printed circuit board (PCB) 52 with a plurality of semiconductor packages mounted on its surface. The electronic device 50 may have one type of semiconductor package or multiple types of semiconductor packages depending on the application. Different types of semiconductor packages are shown in FIG. 6 for illustrative purposes.

The electronic device 50 may be a stand-alone system using a semiconductor package to perform one or more electrical functions. Further, the electronic component 50 may be a sub-component of a larger system. For example, the electronic device 50 may be part of a cell phone, a personal digital assistant (PDA), a digital video camera (DVC), or other electronic communication device. The electronic device 50 may also be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, memory, application specific integrated circuit (ASIC), logic circuit, analog circuit, RF circuit, discrete device or other semiconductor die or electrical component. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between the semiconductor elements must be reduced for higher integration.

In Figure 6, the PCB 52 provides a general substrate for structural support and electrical interconnection of a semiconductor package mounted on a PCB. Conduction signal traces 54 are formed on the PCB 52 or in the PCB layers using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal electrodeposition process. Signal traces 54 provide electrical communication between each semiconductor package, mounted components, and other external system components. The traces 54 also provide power and ground connections to each of the semiconductor packages.

In some embodiments, the semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate carrier. Second level packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In another embodiment, the semiconductor device may only have a first level packaging in which the die is mechanically and electrically mounted directly to the PCB.

For purposes of illustration, various forms of first level packaging, including a wire bond package 56 and a flip chip 58, are shown on the PCB 52. In addition, a ball grid array (BGA) 60, a bump chip carrier (BCC) 62, a dual in-line package (DIP) 64, a land grid array (LGA) 66, (68), a quad flat non-ridged package (QFN) 70 and a quad flat package 72 are shown mounted on the PCB 52 . Depending on the system requirements, any combination of semiconductor packages consisting of any combination of first and second level packaging types as well as other electronic components may be connected to the PCB 52. In some embodiments, the electronic device 50 includes a single attached semiconductor package, while another embodiment requires multiple interconnection packages. By combining one or more semiconductor packages on a single substrate, the manufacturer can incorporate the pre-fabricated components into electronic components and systems. Because semiconductor packages have complex functionality, electronic devices can be fabricated using cheaper components and simplified manufacturing processes. The resulting devices have fewer failures and are cheaper to manufacture, resulting in lower costs for the consumer.

Figures 7A-7C illustrate an exemplary semiconductor package. FIG. 7A shows other details of the DIP 64 mounted on the PCB 52. FIG. Semiconductor die 74 includes an active region, including active elements, passive elements, conductive layers and active regions formed therein, including analog or digital circuits implemented as an insulating layer, and are electrically interconnected according to the electrical design of the die. For example, the circuitry includes one or more transistors, diodes, inductors, capacitors, resistors, and other circuitry formed within the semiconductor die 74. The contact pad 76 is at least one layer made of a conductive material such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold And the like. During assembly of the DIP 64, the semiconductor die 74 is attached to the intermediate carrier 78 using a gold-silver process layer or an adhesive material such as thermal epoxy or epoxy resin. The package body comprises an insulating packaging material such as a polymer or ceramic. Conductor lead 80 and bond wire 82 provide electrical connection between semiconductor die 74 and PCB 52. The encapsulant 84 is electrodeposited on the package for environmental protection by preventing penetration of moisture and particles into the package and by preventing contamination of the semiconductor die 74 or the bond wire 82.

FIG. 7B shows another detail of the BCC 62 mounted on the PCB 52. FIG. The semiconductor die 88 is mounted on the carrier 90 using an underfill or an epoxy-resin attachment material 92. The bond wire 94 provides a first level packaging interconnect between the contact pads 96,98. A molding compound or encapsulant 100 is electrodeposited over semiconductor die 88 and bond wires 94 to provide physical support and electrical isolation of the device. The contact pad 102 is formed on the surface of the PCB 52 for prevention of oxidation using a suitable metal electrodeposition process such as electrolytic plating or electroless plating. The contact pad 102 is electrically connected to one or more of the conductive signal traces 54 of the PCB 52. A bump 104 is formed between the contact pad 98 of the BCC 62 and the contact pad 102 of the PCB 52.

7C, the semiconductor die 58 is mounted tangentially downwardly to the intermediate carrier 106 with flip chip type first level packaging. Active region 108 of semiconductor die 58 includes analog and digital circuits implemented as active elements, passive elements, conductive layers, and insulating layers formed in accordance with the electrical design of the die. For example, the circuitry may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuitry within the active region 108. The semiconductor die 58 is electrically and mechanically connected to the carrier 06 through the bumps 110.

The BGA 60 is electrically and mechanically connected to the PCB 52 with the BGA type second level packaging using the bumps 112. [ The semiconductor die 58 is electrically connected to the conduction signal traces 54 of the PCB 52 through the bumps 110, the signal lines 114 and the bumps 112. A molding compound or encapsulant 116 is deposited over the semiconductor die 58 and the carrier 106 to provide physical support and electrical isolation of the device. The flip chip semiconductor device provides a short electrical conduction path from the active element on the semiconductor die 58 to the conduction track on the PCB 52 to reduce signal propagation distance, provide lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 may be mechanically and electrically connected directly to the PCB 52 using flip chip type first level packaging without the intermediate carrier 106.

In a flip chip type semiconductor die, the interconnection is achieved by connecting the interconnect bumps directly onto narrow interconnection pads or narrow pads instead of conventional capture pads. The flip chip package substrate has a substrate comprising a patterned metal layer on the die attach side of the insulating substrate layer, a metal layer comprising interconnect sites, and a masking layer having openings to the plurality of interconnect sites and traces . The opening has a generally elongated shape that is oriented such that its long dimension spans multiple interconnect sites, traces, and other circuit elements. The shorter dimensions of the elongated openings limit the length exposure of the interconnect sites. Thus, the flow of soluble material that melts during the reflow phase of the interconnect process is limited along the length of the interconnect sites by the mask opening width. The number of interconnect sites where the flow of the molten bump material is so restricted is determined by the length of the mask openings and the number of interconnect sites spanned by the openings. The masking layer allows confinement of the bump material during the remelting stage of the interconnect, but is only within the normal design rules for mask patterning.

Figure 8 shows a schematic cross section or plane of the substrate 120 viewed in a plane parallel to the substrate surface. Some features have been shown to be transparent. Substrate 120 has a patterned insulating layer to support the metal layer of the die attach surface and form a circuit below the masking layer. The circuit may include traces or leads 124 exposed to interconnection sites 126a, 126b, 126c by openings 128a, 128b, 128c elongated in masking layer 130, . The interconnect sites 126a-126c are arranged in an orthogonal array of three columns, each generally parallel to the die edge, as indicated by the dashed line 132.

The elongated openings 128a-128c of the masking layer 130 expose multiple interconnection sites 126a-126c associated with two or more adjacent circuit features. As shown in FIG. 8, each of the elongated openings 128a-128c exposes one of the interconnect sites 126a-126c rows, which can be a row on the interconnect site array. The rows of exposed interconnect sites 126a-126c need not be straight, i.e., openings 128a-128c need not be rectangular. Openings 128a-128c may have a regular or irregular shape. In the case where the elongated openings 128a-128c have a regular polygonal shape such as a square, the elongated openings need not necessarily be oriented parallel to the row or die margin of the interconnect site. Also, some of the leads 124 pass under multiple extension openings 128a-128c.

10C, the flip chip interconnect structure provides a semiconductor die 140 with bumps 142 attached to the die pads and the bumps 142 are connected to interconnect sites (not shown) on the substrate 120 in a high trace density arrangement. (126). The other leads 124 are interconnected at different locations, which can be seen in different cross-sectional views. The narrow dimension widths of the elongated openings 128a-128c limit the flow of the bump material away from the interconnect sites 126a-126c along the wettable leads 124. The width of the elongated mask openings 128a-128c is determined by a design rule for patterning the masking layer. In one embodiment, the nominal mask opening width may be on the order of about 80-90 microns. Further, the nominal mask opening width may be about 100 mu m. The mask material can be disassembled at such a pitch, and in particular, the substrate can be manufactured relatively inexpensively with a masking layer having an opening of 90 mu m and an alignment error of plus or minus 25 mu m. In some embodiments, a laminate substrate such as a 4-metal layer laminate is used.

The required feature size for the masking layer 130 can be made larger because the stretched mask openings 128a-128c span multiple interconnect sites 126a-126c. Alignment of the mask openings 128a-128c with interconnect sites 126a-126c is very relaxed. The risk of partial exposure of the engageable area of the leads 124 at the interconnect sites 126a-126c is practically prevented. The bump material traveling along the circuit feature length at interconnect sites 126a-126c is cone-shaped by the width of mask openings 128a-128c. Since the insulating layer of the substrate 120 is not wetted by the bump material, any flow towards the adjacent circuit features is reduced.

Electrical interconnection may be formed by thermo-mechanically joining the bumps 142 to interconnect sites 126a-126c without melting the bump material. The non-flow underfill material is cured in a gel state. The bump 142 is then melted in the reflow operation to form a reliable interconnect that con fi ne the joint to a relatively small volume and minimizes the risk of bridging to adjacent circuit elements. In some embodiments, a fillet is formed along the peripheral surface and exposes the sidewalls of interconnect sites 126a-126c.

Solder paste may be provided to interconnection sites 126a-126c on leads 124 to provide a soluble medium for interconnection. The paste is dispensed, reflowed, and, if necessary, coined to provide a uniform surface for contact with the bumps 142 by a printing process. The solder paste may be applied during the assembly process, or the substrate may have an appropriately patterned paste prior to assembly. Other approaches that selectively apply solder to interconnect sites 126a-126c include solder-on-lead embodiments such as electroless plating or electrolytic plating. The solder-on-lead configuration provides additional solder volume for interconnects and can provide higher product yield and die standoff.

For interconnection of a semiconductor die having a high melting temperature bump, such as a high-lead solder used in a ceramic substrate, onto an organic substrate, the masking layer limits the flow of the soluble solder paste along the circuit elements near the interconnect site do. The solder paste may be selected to have a low melting temperature such that the organic substrate is not damaged during reflow. In such embodiments, the high-melting point interconnect bumps contact the solder-on-lead sites to form interconnections, and the remelts fuse the solder-on-leads to the bumps. When a non-collapsible bump is used, in addition to the solder-on-lead process, no pre-applied attachment material is required, and the displacement or flow of the solder causes the fact that only a small amount of solder is present in each interconnect Lt; / RTI > The non-collapsible bump prevents collapse of the assembly. In other embodiments, the solder-on-lead configuration may use process solder bumps.

For packages using non-flow underfill techniques, a substrate is provided that has at least one insulating layer and a metal layer on the die attach surface. The metal layer is patterned to provide a trace, or lead, with interconnection sites on the circuit, especially die attach surface. The substrate is supported on a carrier or a stage, for example, in a state in which the surface of the substrate faces the die attach surface contacting with the support. The semiconductor die has bumps attached to die pads on the active side. The bump includes a soluble material in contact with the engagement surface of the lead. A large amount of underfill material, such as an encapsulating resin adhesive, is dispensed onto the die attach surface of the substrate to cover the interconnection sites on the leads on the semiconductor die active side. A pick-and-put tool with a chuck picks up the semiconductor die by contact between the chuck and the die backside. Using a pick-and-place tool, the semiconductor die is positioned in contact with the substrate with the active side of the die facing the die attach surface of the substrate. The semiconductor die and the substrate are aligned and moved toward each other so that the bumps contact the corresponding interconnect sites on the trace or lead of the substrate. A force is applied to press the bump onto the engagement surface of the interconnection site on the lead. The force is sufficient to displace the adhesive from between the engagement surfaces of the interconnect sites on the bump and lead. The bump is deformed by the force to break the oxide film on the contact surface of the bump and / or the interconnection site of the lead. Deformation of the bumps may result in the bubble's soluble material being pressed onto the tops and edges of the interconnect sites. The adhesives at least partially cure by heating to a selected temperature. In this stage, the adhesives require only a partial cure to a sufficient degree to prevent flow of the melt bump material along the interface between the adhesives and the conductive traces. The soluble material of the bumps is melted and re-solidified to form metallurgical interconnections between the bumps and interconnect sites. The adhesives are fully cured to complete the die mounting and fix the electrical interconnections to the engagement surfaces.

If the interconnect is formed by a non-flow underfill process, the non-flow underfill adhesives can be pre-applied to the die surface or at least to the bumps on the die surface instead of the substrate. Adhesive can be stored in a container like a pool, and a significant amount of adherence is carried on the bump as the active side of the die comes in and out of the pool. Using a pick-and-place tool, the die is positioned in contact with the substrate supported with the active side of the die facing the die attach surface of the substrate. The die and substrate are aligned and move relative to each other so that the bumps come into contact with corresponding interconnection sites on the substrate. Such a method is described in U.S. Pat. No. 6,780,682, incorporated herein by reference. Subsequent pressurization, curing and melting processes are carried out as described above.

In some approaches to flip chip interconnection, the metallurgical interconnection first takes place and then the underfill material flows into the space between the semiconductor die and the substrate. The non-flow underfill material is applied before the semiconductor die and substrate are gathered together. The non-flowing underfill material is displaced by the approach to the interconnection site of the bump and the opposing sides of the die and substrate. The non-flowing underfill material may be a non-conductive paste or a fast-gelling adhe- sive that is sufficiently gelled at a gel temperature for a time of 1 to 2 seconds.

Curing of the adhesives can be completed before, simultaneously with, or after melting of the bump material. Typically, adhesives are thermally curable adhesives, and the degree of cure at any phase of the process is controlled by temperature control. Parts can be heated and cured by raising the chuck temperature on the pick-and-put tool or by raising the temperature of the substrate support.

An optional bump structure, such as a composite bump, may be used for the BOL interconnection. The composite bumps have at least two bump parts made of different bump materials, including one that is collapsible under reflow conditions and another that is non-collapsible under reflow conditions. The non-disintegratable portion is attached to a plurality of interconnection sites. Typical materials for the non-disintegratable portion include various solders having a high Pb content. Typical materials for the collapsible portion of the composite bump include process solder. The disintegratable part is joined to the non-disintegratable part, and the contact with the interconnection site is the disintegratable part.

Figs. 11-14 show other embodiments with various interconnect structures applicable to the interconnect structure, as shown in Figs. 8-10. 11 illustrates a semiconductor wafer 220 having a base substrate material 222 for structural support such as silicon, germanium, gallium arsenide, indium phosphide or silicon carbide. A plurality of semiconductor die or parts 224 separated by a saw-street 226 as described above is formed on the wafer 220.

11B shows a cross section of a part of the semiconductor wafer 220. Fig. Each semiconductor die 224 includes a back surface 228 and analog and digital circuits implemented as an active element, a passive element, a conductive layer, and an insulating layer that are electrically interconnected and formed within the die in accordance with the die's electrical design or function Lt; RTI ID = 0.0 > 230 < / RTI > For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed in the active surface 230 to implement analog or digital signals such as a digital signal processor (DSP), ASIC, memory or other signal processing circuitry . The semiconductor die 224 may also include integrated passive devices (IPDs) such as inductors, capacitors, and resistors for RF signal processing. In one embodiment, the semiconductor die 224 is a flip chip type semiconductor die.

An electrically conductive layer 232 is formed over the active surface 230 using PVD, CVD, electroplating, electroless plating, or other suitable metal electrodeposition process. Conductive layer 232 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 232 acts as a contact pad electrically connected to a circuit on active surface 230.

11C illustrates a portion of a semiconductor wafer 220 having an interconnect structure formed over the contact pads 232. [ An electrically conductive bump material 234 is electrodeposited over contact pad 232 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The bump material 234 may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof with a selective flux solution. For example, the bump material 234 may be a process Sn / Pb, a high-lead solder or a lead-free solder. The bump material 234 is generally compliant and undergoes plastic deformation greater than about 25 micrometers under the force equivalent to a vertical load of about 200 grams. The bump material 234 is bonded to the contact pad 232 using a suitable attachment or bonding process. The bump material 234 may be press bonded to the contact pad 232. The bump material 234 may also be heated by reflowing the bump material above its melting point to form a spherical ball or bump 236, as shown in Fig. In some applications, the bumps 236 are reflowed twice to improve electrical contact to the contact pads 232. Bump 236 represents one form of interconnect structure that may be formed on contact pad 232. The interconnect structure may use stud bumps, micro bumps, or other electrical connections.

Figure 11E illustrates another embodiment of an interconnect structure formed over contact pads 232 as composite bumps 238 that include a non-soluble or non-disfantable portion 240 and a soluble or disintegratable portion 242 have. The soluble or non-soluble or non-soluble or non-degradable properties are defined for bumps 238 for the reflow conditions. The non-soluble portion 240 may be Au, Cu, Ni, a high-lead solder or a lead-tin alloy. The soluble portion 242 may be made of one of Sn, a lead-free alloy, a Sn-Ag alloy, a Sn-Ag-Cu alloy, a Sn-Ag-Indium (In) alloy, a process solder, a tin alloy of Ag, Cu or Pb, May be a molten solder. In one embodiment, given a contact pad 232 width or diameter of 100 m, the non-soluble portion 240 is about 45 m high and the soluble portion 242 about 35 m high.

Figure 11F illustrates another embodiment of an interconnect structure formed over contact pads 232 as bumps 244 over conductive pillar 246. [ Bump 244 is soluble or collapsible and conductive pillar 246 is non-soluble or non-collapsible. Soluble or collapsible and non-soluble or non-collapsible properties are defined for reflow conditions. The bumps 244 may be Sn, lead-free alloys, Sn-Ag alloys, Sn-Ag-Cu alloys, Sn-Ag-In alloys, process solders, tin alloys of Ag, Cu or Pb, or other relatively low- have. The conductive pillar 246 may be Au, Cu, Ni, a high-lead solder or a lead-tin alloy. In one embodiment, the conductive pillar 246 is a Cu pillar and the bump 244 is a solder cap. When the width or diameter of the contact pad 232 is given as 100 mu m, the height of the conductive pillar 246 is about 45 mu m and the height of the bump 244 is about 35 mu m.

11G shows another embodiment of the interconnect structure formed on the contact pad 232 as the bump material 248 with the protrusions 250. [ The bump material 248 has a low tensile strength and a high elongation to failure, similar to the bump material 234, and is ductile and deformable under reflow conditions. The protrusions 250 are formed of a plated finishing surface and are enlarged in the drawings for purposes of illustration. The size of the protrusions 250 is also generally about 1-25 占 퐉. The projections may also be formed on the bumps 236, the composite bumps 238, and the bumps 244.

11H semiconductor wafer 220 is singulated with individual semiconductor die 224 along sawtooth 226 using a saw blade or laser cutting tool 252. In FIG.

12A shows a PCB or PCB 254 with conductive traces 256. FIG. Substrate 254 may be a single side FR5 laminate or a 2-side BT-resin laminate. Semiconductor die 224 is positioned such that bump material 234 is aligned with the interconnect sites of conductive traces 256, see Figures 20a-20g. In addition, the bump material 234 may be arranged in parallel with the conductive pads or other interconnection sites formed on the substrate 254. The bump material 234 is wider than the conductive traces 256. In one embodiment, the bump material 234 has a width less than 100 mu m and the conductive trace or pad 256 has a width of 35 mu m for a bump pitch of 150 mu m. Conductive traces are applicable to interconnect structures, as shown in Figures 8-10.

A pressure or force F is applied to the rear surface 228 of the semiconductor die 224 to compress the bump material 234 into the conductive traces 256. The force F can be applied at a high temperature. Due to the shallow nature of the bump material 234, the bump material is deformed or extruded around the top and sides of the conductive trace 256, as referred to as bump-on-lead (BOL). In particular, the application of the pressure causes the bump material 234 to undergo plastic deformation greater than about 25 占 퐉 under a force F corresponding to a vertical load of about 200 grams, and the top or side of the conductive trace, as shown in Figure 12b, Cover. The bump material 234 may also be metallurgically connected to the conductive traces 256 by physically contacting the bump material with the conductive traces and reflowing the bump material under the reflow temperature.

 By making the conductive traces 256 narrower than the bump material 234, the conductive trace pitch can be reduced to increase the routing density and I / O count. The narrower conductive traces 256 reduce the force F required to deform the bump material 234 around the conductive traces. For example, the required force F may be 30-50% of the force required to deform the bump material for a conductive trace or pad wider than the bump material. A lower compressive force (F) is useful for fine pitch interconnections and small dies to maintain uniform co-planarity with a specific error and to achieve uniform unidirectional deformation and high reliability interconnections. In addition, deforming the bump material 234 around the conductive traces 256 mechanically locks the bumps into the traces to prevent die shifting or die floating during reflow.

12C shows bumps 236 formed on the contact pads 232 of the semiconductor die 224. The semiconductor die 224 is positioned such that the bumps 236 are parallel to the interconnect sites on the conductive traces 256. In addition, the bumps 236 may be parallel to the conductive pads or other interconnection sites formed on the substrate 254. The bumps 236 are wider than the conductive traces 256. The conductive traces 256 are applicable to interconnect structures, as shown in Figures 8-10.

A pressure or force F is applied to the rear surface 228 of the semiconductor die 224 to press the bump 236 against the conductive trace 256. The force F can be applied at a high temperature. Due to the shallow nature of the bumps 236, the bumps are deformed or extruded around the top and sides of the conductive traces 256. In particular, application of pressure causes the bumps 236 to undergo plastic deformation and cover the top and sides of the conductive traces 256. The bumps 236 are also metallurgically connected to the conductive traces 256 by physically contacting the bumps with the conductive traces under the reflow temperature.

By making the conductive traces 256 narrower than the bumps 236, the conductive trace pitch can be reduced to increase the routing density and I / O count. The narrower conductive traces 256 reduce the force F required to deform the bump material 234 around the conductive traces. For example, the required force F may be 30-50% of the force required to deform the bump material for a conductive trace or pad wider than the bump material. A lower compressive force (F) is useful for fine pitch interconnections and small dies to maintain coplanarity within a particular tolerance range and achieve coherent z-directional deformation and high reliability interconnections. In addition, deformation of the bump material 234 around the conductive traces 256 mechanically locks the bumps into the traces to prevent die shifting or die floating during reflow.

12D shows the composite bump 238 formed on the contact pad 232 of the semiconductor die 224. The semiconductor die 224 is positioned so that the composite bumps 238 are parallel to the interconnect sites on the conductive traces 256. In addition, the composite bumps 238 may be aligned with conductive pads or other interconnect sites formed on the substrate 254. The composite bumps 328 are wider than the conductive traces 256. The conductive traces 256 are applicable to interconnect structures, as shown in Figures 8-10.

A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the soluble portion 242 against the conductive trace 256. The force F can be applied at a high temperature. Due to the moderate nature of the fusible portion 242, the fusible portion is deformed or extruded around the top and sides of the conductive trace 256. In particular, application of the pressure causes the fusible portion 242 to undergo plastic deformation and cover the top and sides of the conductive trace 256. The composite bump 238 may also be metallurgically connected to the conductive trace 256 by physically contacting the fusible portion 242 with the conductive trace under the reflow temperature. The non-soluble portion 240 is not melted or deformed during application of pressure or temperature and maintains its shape between the semiconductor die 224 and the substrate 254 as its height and vertical standoff. Additional displacement between the semiconductor die 224 and the substrate 254 provides greater coplanar error between the engaging surfaces.

During the reflow process, a large number (e.g., thousands) of composite bumps 238 on the semiconductor die 224 are attached to the interconnect sites on the conductive traces 256 of the substrate 254. Some of the bumps 238 fail to properly connect to the conductive traces 256, especially when the die 224 is twisted. Recall that the composite bump 238 is wider than the conductive trace 256. With the appropriate force applied, the fusible portion 242 is deformed or extruded about the top and sides of the conductive traces 256 and mechanically locks the composite bumps 238 to the conductive traces. Mechanical interlocking is formed by deformation of the conductive traces 256 around and above and around the top surface of the conductive trace to the nature of the soft portion 242 and therefore to a larger contact surface area. Mechanical interlocking between the composite bump 238 and the conductive traces 256 maintains the conductive traces during reflow, i.e., the bumps and conductive traces do not lose contact. Thus, the composite bump 238, which engages the conductive trace 256, reduces bump interconnect defects.

12E shows conductive pillar 246 and bump 244 formed on contact pad 232 of semiconductor die 224. The semiconductor die 224 is positioned so that the bumps 244 are aligned in parallel with the interconnect sites of the conductive traces 256. In addition, the bumps 244 may be aligned with conductive pads or other interconnect sites formed on the substrate 254. The bumps 244 are wider than the conductive traces 256. The conductive traces 256 are applicable to interconnect structures, as shown in Figures 8-10.

A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump 244 against the conductive trace 256. The force F can be applied at a high temperature. Due to the smooth nature of the bumps 244, the bumps are deformed or extruded around the top and sides of the conductive traces 256. In particular, application of pressure causes the bumps 244 to undergo plastic deformation and cover the top and sides of the conductive traces 256. Conductive pillar 246 and bump 244 may also be metallurgically connected to conductive trace 256 by physically contacting the bump with a conductive trace under a reflow temperature. The conductive pillar 246 is not melted or deformed during application of pressure or temperature and maintains its shape between the semiconductor die 224 and the substrate 254 as its height and vertical standoff. The additional displacement between the semiconductor die 324 and the substrate 254 provides greater coplanar error between the engaging surfaces. The wider bump 244 and the narrower conductive trace 256 have lower essential compression forces, mechanical locking features, and advantages similar to those described above for bump material 234 and bump 236.

12F illustrates a bump material 248 with a protrusion 250 formed on the contact pad 232 of the semiconductor die 224. The semiconductor die 224 is positioned so that the bump material 248 is aligned parallel to the interconnect sites of the conductive traces 256. In addition, the bump material 248 may be aligned with a conductive pad or other interconnection site formed on the substrate 254. The bump material 248 is wider than the conductive trace 256. A pressure or force F is applied to the rear surface 228 of the semiconductor die 224 to press the bump material 248 to the conductive trace 256. The force F can be applied at a high temperature. Due to the shallow nature of the bump material 248, the bumps are deformed or extruded around the top and sides of the conductive trace 256. In particular, application of pressure causes the bump material 248 to undergo plastic deformation and cover the top and sides of the conductive trace 256. In addition, the protrusions 250 are metallurgically connected to the conductive traces 256. The protrusion 250 is about 1-25 mu m in size.

12G shows PCB 258 with trapezoidal conductive traces 260 having angled or inclined sides. A bump material 261 is formed on the contact pads 232 of the semiconductor die 224. The semiconductor die 224 is positioned so that the bump material 261 is aligned parallel to the interconnect sites of the conductive traces 260. In addition, the bump material 261 may be aligned with a conductive pad or other interconnection site formed on the substrate 254. The bump material 261 is wider than the conductive trace 260. The conductive traces 260 are applicable to interconnect structures, as shown in Figures 8-10.

A pressure or force F is applied to the back surface 228 of the semiconductor die 224 to press the bump material 261 onto the conductive trace 260. The force F can be applied at a high temperature. Due to the modest nature of the bump material 261, the bump material is deformed or extruded around the top and sides of the conductive trace 260. In particular, application of pressure causes the bump material 261 to undergo plastic deformation under force F and cover the top and angled sides of the conductive trace 260. The bump material 261 may also be metallurgically connected to the conductive trace 260 by physically contacting the bump material with the conductive trace under reflow temperature and then reflowing.

FIGS. 13A-13D illustrate a BOL embodiment of an elongated composite bump 262 having a semiconductor die 224 and a non-soluble or non-collapsible portion 264 and a soluble or disintegratable portion 266. The non-soluble portion 264 may be Au, Cu, Ni, a high-lead solder or a lead-tin alloy. The fusible portion 266 may be made of Sn, a lead-free alloy, a Sn-Ag alloy, a Sn-Ag-Cu alloy, a Sn-Ag-In alloy, a process solder, a tin alloy of Ag, Cu or Pb or other relatively low- . The non-soluble portion 264 constitutes a larger portion of the composite bump 262 than the soluble portion 266. The non-soluble portion 264 is secured to the contact pad 232 of the semiconductor die 224.

The semiconductor die 224 is positioned so that the composite bumps 262 are parallel to the interconnect sites on the conductive traces 268 formed in the substrate 270, as shown in FIG. The composite bumps 262 are tapered along the conductive traces 268, i.e., the composite bumps have a wedge shape, which is longer along the length of the conductive trace 268 and narrower as it traverses the conductive traces. The tapered aspect of the composite bump 262 occurs along the length of the conductive trace 268. FIG. 13A shows a tapered taper that is coplanar with a shorter side or conductive trace 268. FIG. 13B, which is perpendicular to FIG. 13A, shows a longer side view of the wedge-shaped composite bump 262. FIG. The shorter aspect of the composite bump 262 is wider than the conductive trace 268. The fusible portion 266 collapses around the conductive traces 268 as applying pressure and / or reflowing to heat, as shown in Figures 13c and 13d. The non-soluble portion 264 does not melt or deform during reflow and maintains its shape and shape. The non-soluble portion 264 is sized to provide a standoff distance between the semiconductor die 224 and the substrate 270. A finishing material such as a Cu OSP may be applied to the substrate 270. The conductive traces 268 are applicable to interconnect structures, as shown in Figures 98-10.

During the reflow process, a large number (e.g., thousands) of composite bumps 262 on the semiconductor die 224 are attached to the interconnect sites on the conductive traces 268 of the substrate 270. Some of the bumps 262 fail to properly connect to the conductive traces 268, particularly when the semiconductor die 224 is twisted. Recall that the composite bumps 262 are wider than the conductive traces 268. With the appropriate force applied, the fusible portion 266 is deformed or extruded about the top and sides of the conductive traces 268 and mechanically locks the composite bumps 262 to the conductive traces. Mechanical interlocking is formed by deformation of the conductive trace about the top surface and the side surface of the conductive trace to the nature of the soft portion 268, which is softer and more flexible than the conductive trace 268, and thus a larger contact surface area. The wedge-shape of the composite bump 262 increases the contact area along the shorter sides of Figs. 13A and 13C, without sacrificing the pitch between the bumps and the conductive traces, i.e., the longer sides of Figs. 13B and 13D . Mechanical interlocking between the composite bump 262 and the conductive traces 268 maintains the conductive traces during reflow, i.e., the bumps and conductive traces do not lose contact. Thus, the composite bump 262, which engages the conductive traces 268, reduces the bump interconnect failure.

Figs. 14A-14D illustrate a BOL embodiment of a semiconductor die 224 with bump material 274 formed on contact pads 232, similar to Fig. 11C. 14A, bump material 274 is generally compliant and undergoes plastic deformation greater than about 25 microns under a force equivalent to a normal load of about 200 grams. The bump material 274 is wider than the conductive traces 276 on the substrate 278. A plurality of protrusions 280 are formed on the conductive traces 276 at a height of about 1-25 mu m.

The semiconductor die 224 is positioned such that the bump material 274 is aligned with the interconnect sites on the conductive traces 276. The bump material 274 may also be parallel to the conductive pads or interconnection sites formed on the substrate 278. A pressure or force F is applied to the rear surface 228 of the semiconductor die 224 to press the bump material 274 against the conductive traces 276 and the protrusions 280 as shown in Figure 14B. The force F can be applied at a high temperature. Due to the smooth nature of the bump material 274, the bump material is deformed or extruded around the top surfaces and sides of the conductive traces 276 and the protrusions 280. In particular, application of pressure causes the bump material 274 to undergo plastic deformation and cover the top surfaces and sides of the conductive traces 276 and the protrusions 280. [ The plastic flow of the bump material 274 creates a macroscopic mechanical interlocking point between the bump material and the conductive traces 276 and the tops and sides of the protrusions 280. The plastic flow of the bump material 274 occurs around the top and sides of the conductive traces 276 and the protrusions 280 but does not extend excessively to the substrate 278, which can cause electrical shorts and other defects. The mechanical interlocking between the bump material and the top and side surfaces of the conductive traces 276 and the protrusions 280 creates a rigid connection through a large contact area between each surface without significantly increasing the bonding force. The mechanical interlocking between the bump material and the top and side surfaces of the conductive traces 276 and the protrusions 280 also reduces lateral die shifting during subsequent fabrication processes such as the encapsulation process.

14C shows another BOL embodiment with a narrower bump material 274 than the conductive traces 276. FIG. A pressure or force F is applied to the rear surface 228 of the semiconductor die 224 to press the bump material 274 against the conductive traces 276 and the protrusions 280. [ The force F can be applied at a high temperature. The bump material is deformed or extruded over the top surfaces of the conductive traces 276 and the protrusions 280. [ In particular, application of pressure causes the bump material 274 to undergo plastic deformation and cover the top surfaces of the conductive traces 276 and the protrusions 280. The plastic flow of the bump material 274 creates a macroscopic mechanical interlocking point between the bump material and the top surfaces of the conductive traces 276 and the protrusions 280. Mechanical interlocking between the bump material and the top surfaces of the conductive traces 276 and the protrusions 280 creates a rigid connection through a large contact area between each surface without significantly increasing the coupling force. The mechanical interlocking between the bump material and the top surfaces of the conductive traces 276 and the protrusions 280 also reduces lateral die shifting during subsequent fabrication processes such as encapsulation processes.

14D illustrates another BOL embodiment with a bump material 274 formed over the edge of the conductive trace 276, i. E., A bump material with a portion of the bump material above the conductive trace and a portion of the bump material above the conductive trace. . A pressure or force F is applied to the rear surface 228 of the semiconductor die 224 to press the bump material 274 against the conductive traces 276 and the protrusions 280. [ The force F can be applied at a high temperature. The bump material is deformed or extruded over the top surfaces and sides of the conductive traces 276 and the protrusions 280. As a result, In particular, application of pressure causes the bump material 274 to undergo plastic deformation and cover the top surfaces and sides of the conductive traces 276 and the protrusions 280. [ The plastic flow of the bump material 274 creates a macroscopic mechanical interlock between the bump material and the conductive traces 276 and the top and sides of the protrusions 280. The mechanical interlocking between the bump material and the top and side surfaces of the conductive traces 276 and the protrusions 280 creates a rigid connection through a large contact area between each surface without significantly increasing the bonding force. The mechanical interlocking between the bump material and the top and side surfaces of the conductive traces 276 and the protrusions 280 also reduces lateral die shifting during subsequent fabrication processes such as the encapsulation process.

Figs. 15A-15C illustrate a BOL embodiment of a semiconductor die 224 with a bump material 284 formed on a contact pad 232, similar to Fig. 11C. The tip 286 extends from the body of the bump material 284 as a stepped bump with a narrower tip 286 than the body of the bump material 284, as shown in FIG. The semiconductor die 224 is positioned such that the bump material 284 is parallel to the interconnect sites on the conductive traces 288 of the substrate 290. In particular, the tip 286 is centered on the interconnect site of the conductive trace 288. The bump material 284 and the tip 286 may also be aligned with a conductive pad or other interconnection site formed on the substrate 290. The bump material 284 is wider than the conductive traces 288 on the substrate 290.

The conductive traces 288 are generally compliant and undergo plastic deformation greater than about 25 microns under a force equivalent to a vertical load of about 200 grams. A pressure or force F is applied to the rear surface 228 of the semiconductor die 224 to press the tip 284 against the conductive trace 288. The force F can be applied at a high temperature. Due to the shallow nature of the conductive traces 288, the conductive traces are deformed around the tips 286, as shown in FIG. 15B. In particular, application of the pressure causes the conductive traces 288 to undergo plastic deformation and cover the top and sides of the tip 286.

Fig. 15C shows another BOL embodiment with a round bump material 294 formed on the contact pad 232. Fig. The tip 296 extends from the body of the bump material 294 to form a stud bump with a narrower tip than the body of the bump material 294. The semiconductor die 224 is positioned such that the bump material 294 is parallel to the interconnect sites on the conductive traces 298 of the substrate 300. In particular, the tips 296 are centered on the interconnecting sites of the conductive traces 298. The bump material 294 and the tip 296 may also be aligned with conductive pads or other interconnection sites formed on the substrate 300. The bump material 294 is wider than the conductive traces 298 on the substrate 300.

The conductive traces 298 typically undergo plastic deformation greater than about 25 microns under a force equivalent to a normal load of about 200 grams compliant. A pressure or force F is applied to the rear surface 228 of the semiconductor die 224 to press the tip 296 against the conductive trace 298. The force F can be applied at a high temperature. Due to the shallow nature of the conductive traces 298, the conductive traces are deformed around the tips 296. In particular, application of the pressure causes the conductive traces 298 to undergo plastic deformation and cover the top and sides of the tip 296.

The conductive traces described in Figs. 12A-12G, 13A-13D and Figs. 14A-14D may also be of a soft material as described in Figs. 15A-15C.

16A-16B illustrate a BOL embodiment of a semiconductor die 224 with a bump material 304 formed on a contact pad 232, similar to FIG. 11C. The bump material 304 is generally compliant and undergoes plastic deformation greater than about 25 microns under the force equivalent to a vertical load of about 200 grams. The bump material 304 is wider than the conductive traces 306 on the substrate 308. Conductive vias 310 are formed through conductive traces 306 with openings 312 and conductive sidewalls 314 as shown in Figure 16A. The conductive traces 306 are applicable to interconnect structures, as shown in Figures 8-10.

Semiconductor die 224 is positioned so that bump material 304 is parallel to the interconnect sites on conductive traces 306, see Figures 20a-20g. In addition, the bump material 304 may be aligned with a conductive pad or interconnection site formed on the substrate 308. A pressure or force F is applied to the rear surface 228 of the semiconductor die 224 to press the bump material 304 into the openings 312 of the conductive traces 306 and the conductive vias 310. [ The force F can be applied at a high temperature. 16B, the bump material is deformed or extruded around the top and sides of the conductive traces 306 and into the openings 312 of the conductive vias 310 . In particular, application of pressure causes the bump material 304 to undergo plastic deformation and cover the top surface and sides of the conductive traces 306 and the openings 312 of the conductive vias 310. The bump material 304 is thus electrically connected to the conductive traces 306 and the conductive sidewalls 314 for z-directional vertical interconnections through the substrate 308. The plastic flow of the bump material 304 creates a mechanical interlock between the bump material and the top surface of the conductive trace 306 and the opening 312 of the conductive via 310. The mechanical interlocking between the bump material and the top surface of the conductive traces 306 and the openings 312 of the conductive vias 310 creates a strong connection through a large contact area between each surface without significantly increasing the bonding force . Mechanical interlocking between the bump material and the top surface of the conductive traces 306 and the openings 312 of the conductive vias 310 also reduces lateral die sinking during subsequent fabrication processes such as encapsulation. Because the conductive vias 310 are formed in interconnect sites with bump material 304, the overall substrate interconnect area is reduced.

In the embodiment of Figures 12a-12g, 13a-13d, 14a-14d, 15a-15c, and 16a-16b, the conductive trace pitch is reduced by making the conductive traces narrower than the interconnect structure, ) Density and I / O count. The narrower conductive traces reduce the force F required to deform the interconnect structure around the conductive traces. For example, the required force F may be 30-50% of the force required to deform the bump for a conductive trace or pad wider than the bump material. A lower compressive force (F) is useful for fine pitch interconnects and small dies to maintain coplanarity within a specific tolerance range and achieve uniform unidirectional deformation and high reliability interconnections. In addition, deforming the interconnect structure around the conductive traces mechanically locks the bumps into the traces to prevent die shifting or die floating during reflow.

 17A-17C illustrate a mold underfill (MUF) process for depositing an encapsulant around the bumps between the semiconductor die and the substrate. 17A shows a semiconductor die 224 mounted on a substrate 254 using a bump material 234 from Fig. 12B and positioned between an upper mold support 316 and a lower mold support 318 of the chase mold 320. Fig. Respectively. Other semiconductor die and substrate combinations from Figures 12a-12g, 13a-13d, 14a-14d, 15a-15c and 16a-16b may be used for the upper mold support 316 and the lower mold support (not shown) of the chase mold 320 318. < / RTI > The upper mold support 316 includes a compressible release film 322.

17B, an upper mold support 316 and a lower mold support 318 are gathered together to enclose the semiconductor die 224 and the substrate 254 with the open space between the substrate and the semiconductor die and the substrate. Compressible release films 322 are aligned in alignment with the back surface 228 and side surfaces of the semiconductor die 224 to prevent the formation of encapsulant on these surfaces. While the liquid vacuum seal 324 is being injected into one side of the chase mold 320 using the nozzle 326, the optional vacuum assist 328 attracts pressure from the opposite side, The space and the open space between the semiconductor die 224 and the substrate 254 are evenly filled with encapsulant. The encapsulant 324 can be a polymer composite such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a suitable polymer with a filler. The encapsulant 324 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. The compressible material 322 prevents the encapsulant 324 from flowing on the back surface 228 of the semiconductor die 224 and around the side surface. The encapsulant 324 is cured. The back side and side of the semiconductor die 224 remain exposed from the encapsulant 324.

Fig. 17C shows an embodiment of the MUF and mold overfill (MOF), i.e., without the compressible material 322. Fig. Semiconductor die 224 and substrate 254 are positioned between upper mold support 316 and lower mold support 318 of chase mold 320. An upper mold support 316 and a lower mold support 318 are gathered together to enclose the semiconductor die 224 and the substrate 254 with the open space around the substrate, around the semiconductor die, and between the semiconductor die and the substrate . The optional vacuum assist 328 attracts pressure from the opposite side while the liquid encapsulant 324 is injected into one side of the chase mold 320 using the nozzles 326 to provide pressure around the semiconductor die 224 and / The open space between the semiconductor die 224 and the substrate 254 and the open space over the substrate 254 are uniformly filled with encapsulant. The encapsulant 324 is cured.

18 shows another embodiment for depositing an encapsulant around the semiconductor die 224 and into a gap between the semiconductor die 224 and the substrate 254. [ The semiconductor die 224 and the substrate 254 are enclosed by a dam 330. The encapsulant 332 is dispensed in liquid form from the nozzle 334 into the dam 330 to fill the open space above the substrate 254 with the open space between the semiconductor die 224 and the substrate 254. The volume of the encapsulant 332 dispensed from the nozzle 334 is controlled to fill the dam 330 without covering the back surface 228 or side of the semiconductor die 224. The sealing material 332 is cured.

19 shows the semiconductor die 224 and the substrate 254 after the MUF process from Figs. 17A, 17C and 18. Fig. The encapsulant 224 is evenly distributed over the substrate 254 and around the bump material 234 between the semiconductor die 224 and the substrate 254.

20A-20G are plan views of various conductive trace rails on a substrate or PCB 340. [ In Figure 20A, the conductive traces 342 are straight conductors with integrated bump pads or interconnection sites 344 formed on the substrate 340. The sides of the substrate bump pad 344 may be collinear with the conductive traces 342. In the prior art, solder registration openings (SRO) are typically formed on the interconnect sites to accommodate the bump material during reflow. The SRO increases the interconnect pitch and reduces the I / O count. In contrast, a masking layer 346 may be formed on a portion of the substrate 340, but a masking layer is not formed around the substrate bump pad 344 of the conductive traces 342. That is, portions of the conductive traces 342 designed to engage the bump material lack any SRO of the masking layer 346 that may be used for bump accommodation during reflow.

The semiconductor die 224 is positioned over the substrate 340 and the bump material is arranged side by side with the substrate bump pads 344. The bump material is electrically and metallurgically connected to the substrate bump pad 344 by physically contacting it with the bump pad and then reflowing the bump material under the reflow temperature.

In another embodiment, an electrically conductive bump material is deposited over the substrate bump pads 444 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder with a selective flux solution and combinations thereof. For example, the bump material may be a process Sn / Pb, a high-lead solder or a lead-free solder. The bump material is bonded to the substrate bump pad 344 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the bump material above its melting point to form the bump or interconnect structure 348, as shown in Figure 20B. In some applications, the bump 348 is reflowed twice to improve electrical contact to the substrate bump pad 344. The bump material around the narrow substrate bump pad 344 maintains the die position during reflow.

In high routing density applications, it is desirable to minimize the escape pitch of the conductive traces 342. The escape pitch between the conductive traces 342 can be reduced by removing the masking layer for reflow acceptance purposes, i. E., Reflowing the bump material without the masking layer. Since no SRO is formed around the die bump pad 232 or the substrate bump pad 344, the conductive traces 342 can be formed with finer pitches, i.e., the conductive traces 342 can be formed in close proximity to the structure Or in its neighborhood. The pitch between the conductive traces 342 is given by P = D + PLT + W / 2 where D is the base diameter of the bump 348, PLT is the die diameter of the bump 348, And W is the width of the conductive trace 342. In one embodiment, given a bump base diameter of 100 mu m, a PLT of 10 mu m, and a trace line width of 30 mu m, the minimum escape pitch of the conductive traces 242 is 125 mu m. Mask-less bump formation, as can be seen in the prior art, necessitates a description of the ligament space, mask solder mask registration error (SRT) and minimum resolvable SRO of the masking material between adjacent openings .

When the bump material is reflowed to connect the die bump pad 232 metallically and electrically to the substrate bump pad 344 without a masking layer, wetting and surface tension may cause the bump material to become self- Held in confinement and held in the space between the die pump pad 232 and the substrate bump pad 344 and in the portion of the substrate 340 immediately adjacent to the conductive traces 342 in the footprint of the bump pad. .

To achieve the desired self-confinement characteristics, the bump material may be removed from the die bump pad 232 to make the area in contact with the bump material more wettable than the surrounding area of the conductive trace 342, Or may be impregnated with the flux solution before being placed on the substrate bump pad 344. The molten bump material remains locally within the region defined by the bump pad due to the wetting characteristics of the flux solution. The bump material does not advance to a less wettable area. An oxide layer or other insulating layer of the thin film may be formed over the areas where the bump material was not intended to be made less wettable. For this reason, a masking layer 340 is not needed around the die pump pad 232 or the substrate bump pad 344.

20C illustrates another embodiment of a parallel conductive trace 352 as a streak conductor with integrated rectangular bump pads or interconnection sites 354 formed on substrate 350. [ In this case, the substrate bump pad 354 is wider than the conductive traces 342 and less than the width of the engagement bumps. The sides of the substrate bump pad 354 may be parallel to the conductive traces 352. A masking layer 356 may be formed on a portion of the substrate 350, but a masking layer is not formed around the substrate bump pad 354 of the conductive trace 352. That is, portions of the conductive traces 352 designed to engage the bump material lack any SRO of the masking layer 356 that may be used for bump accommodation during reflow.

20D illustrates another embodiment of conductive traces 360 and 362 arranged in an array of multiple rows with offset integrated bump pads or interconnection sites 364 formed on a substrate 366 for maximum interconnect density and capacitance Respectively. Alternating conductive traces 360 and 362 include elbows for routing to bump pads 364. The sides of each substrate bump pad 364 are collinear with the conductive traces 360,362. A masking layer 368 may be formed on a portion of the substrate 366 but the masking layer 368 is not formed around the substrate bump pads 364 of the conductive traces 360,362. That is, portions of the conductive traces 360, 362 that are designed to engage the bump material lack any SRO of the masking layer 368 that may be used for bump accommodation during reflow.

20E illustrates another embodiment of conductive traces 370 and 372 arranged in an array of multiple columns with offset integrated bump pads or interconnection sites 374 formed on a substrate 376 for maximum interconnect density and capacitance. Respectively. Alternating conductive traces 370 and 372 include elbows for routing to bump pads 374. In this case, the substrate bump pad 374 is rounded and wider than the conductive traces 370 and 372, but less than the width of the mating interconnect bump material. A masking layer 378 may be formed on a portion of the substrate 376 but the masking layer 378 is not formed around the substrate bump pad 374 of the conductive traces 370 and 372. [ That is, portions of the conductive traces 370, 372 that are designed to engage the bump material lack any SRO of the masking layer 378 that may be used for bump accommodation during reflow.

 20F shows another embodiment of conductive traces 380 and 382 arranged in an array of multiple rows with offset integrated bump pads or interconnection sites 384 formed on substrate 386 for maximum interconnect density and capacitance Respectively. Alternating conductive traces 380 and 382 include elbows for routing to bump pads 384. In this case, the substrate bump pad 384 is rectangular and wider than the conductive traces 380, 382, but less than the width of the mating interconnect bump material. A masking layer 388 may be formed on a portion of the substrate 386 but a masking layer 388 is not formed around the substrate bump pad 384 of the conductive traces 380 and 382. That is, portions of the conductive traces 380, 382 that are designed to engage the bump material lack any SRO of the masking layer 388 that may be used for bump accommodation during reflow.

As an example of an interconnection process, the semiconductor die 224 is positioned over the substrate 366 and the bump material 234 is aligned with the substrate bump pad 364 from Figure 20d. The bump material 234 may be formed by pressing the bump material or by physically contacting the bump material with the bump pads as described in Figures 12a-12g, 13a-13d, 14a-14d, 15a-15c and 16a-16b, And is electrically and metallurgically connected to the substrate bump pad 364 by reflowing the bump material under the reflow temperature.

In another embodiment, an electrically conductive bump material is electrodeposited over the substrate bump pad 364 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder with a selective flux solution and combinations thereof. For example, the bump material may be eutectic Sn / Pb, a high-lead solder or a lead-free solder. The bump material is bonded to the substrate bump pad 364 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form the bump or interconnect structure 390, as shown in Figure 20g. In some applications, the bump 390 is reflowed twice to improve electrical contact to the substrate bump pad 364. The bump material around the narrow substrate bump pad 364 maintains the die position during reflow. The bump material 234 or the bump 390 may also be formed on the substrate bump pad structure of Figures 20a-20g.

In high routing density applications, it is desirable to minimize the escape pitches of the conductive traces (360, 362) or other conductive trace configurations of Figures 20a-20g. The escape pitch between the conductive traces 360,362 can be reduced by removing the masking layer for reflow accepting purposes, i. E., Reflowing the bump material without the masking layer. Since no SRO is formed around the die bump pad 232 or the substrate bump pad 364, the conductive traces 360, 362 can be formed with finer pitches, i.e., the conductive traces 360, Or in its neighborhood. The pitch between the conductive traces 360 and 362 is given by P = D / 2 + PLT + W / 2, where D is the base diameter of the bump 390, PLT is the die position error, and W is the width of the conductive traces 360,362. In one embodiment, given a bump base diameter of 100 mu m, a PLT of 10 mu m, and a trace line width of 30 mu m, the minimum escape pitch of the conductive traces 360 and 362 is 75 mu m. Mask-less bump formation, as can be seen in the prior art, is a description of the ligament space of the masking material between adjacent openings, the solder mask registration (SRT) and the minimum resolvable SRO Eliminates the need.

When the bump material is reflowed to connect the die bump pad 232 metallically and electrically to the substrate bump pad 364 without a masking layer, wetting and surface tension may cause the bump material to become self- Held in a confinement state and held in a space between the die pump pad 232 and the substrate bump pad 364 and in a portion of the substrate 366 immediately adjacent to the conductive traces 360,362 in the bump pad footprint .

In order to achieve the desired self-confinement characteristics, the bump material may be removed from the die bump pad 232 or the substrate bump pad (not shown) to make the area in contact with the bump material more wettable than the surrounding area of the conductive traces 360, 364, < / RTI > The molten bump material remains locally within the region defined by the bump pad due to the wetting characteristics of the flux solution. The bump material does not advance to a less wettable area. An oxide layer or other insulating layer of the thin film may be formed over the areas where the bump material was not intended to be made less wettable. For this reason, a masking layer 368 is not needed around the die pump pad 232 or the substrate bump pad 364.

In FIG. 21A, a masking layer 392 is electrodeposited over a portion of the conductive traces 394, 396. However, the masking layer 392 is not formed on the integrated bump pad 398. As a result, there is no SRO for each bump pad 398 on the substrate 400. A non-wetting masking patch 402 is formed on the substrate 400 in an interleaved fashion within the array of integrated bump pads 398, i.e., between adjacent bump pads. A masking patch 402 may also be formed on the semiconductor die 224 in an interstitial fashion within the array of die bump pads 398. More generally, the masking patch is formed in close proximity to the integrated bump pads in any arrangement to prevent progression to less wettable areas.

The semiconductor die 224 is positioned over the substrate 400 and the bump material is flush with the substrate bump pad 398. The bump material may be applied by pressing the bump material or by physically contacting the bump material with the bump pad and then by bumping the bump material as described in Figures 12a-12g, 13a-13d, 14a-14d, 15a-15c and 16a-16b And is electrically and metallurgically connected to substrate bump pad 398 by reflow under reflow temperature.

In another embodiment, an electrically conductive bump material is electrodeposited over die integrated bump pads 398 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder with a selective flux solution and combinations thereof. For example, the bump material may be a process Sn / Pb, a high-lead solder or a lead-free solder. The bump material is bonded to the integrated bump pad 398 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the bump material above its melting point to form a spherical ball or bump 404, as shown in Figure 21B. In some applications, the bump 404 is reflowed twice to improve electrical contact to the integrated bump pad 398. The bumps may also be press bonded to the integrated bump pads 398. The bumps 404 represent one form of interconnect structure that may be formed on the integrated bump pads 398. The interconnect structure may also be a stud bump, micro bump or other electrical interconnect.

In high routing density applications, it is desirable to minimize the escape pitch. To reduce the pitch between the conductive traces 394 and 396, the bump material is reflowed around the integrated bump pad 398 without a masking layer. The escape pitch between the conductive traces 394 and 396 can be reduced by removing the masking layer for reflow acceptance purposes and the associated SRO around the integrated bump pad, i. E., Reflowing the bump material without a masking layer. The masking layer 392 may be formed on portions of the substrate 400 away from the conductive traces 394 and 396 and the integrated bump pads 398 but the masking layer 392 is not formed around the integrated bump pads 398. [ That is, portions of the conductive traces 394, 396 designed to engage the bump material lack any SRO of the masking layer 392 that may be used for bump accommodation during reflow.

A masking patch 402 is also formed on the substrate 400 in an interstitial fashion within the array of the encapsulating bump pads 398. The masking patch 402 is a non-wetting material. The masking patch 402 is the same material as the masking layer 392 and may be applied during the same process step or it may be different material and applied during different process steps. The masking patches 402 may be formed by selective oxidation, plating, or other processing of traces or pad portions within the integrated bump pad 398 array. The masking patch 402 limits the bump material flow to the integrated bump pad 398 to prevent leaching of the conductive bump material into adjacent structures.

The wetting and surface tension is reduced by the die bump pad 232 and the integrated bump pad 398 when the bump material is reflowed with the masking patch 402 intruded into the integrated bump pad 398 array. And defines and retains the bump material within the space between the conductive traces 394 and 396 and on the portion of the substrate 400 in the footprint of the integrated bump pad 398. [

 The bump material may be removed from the die bump pad 232 or the integrated bump pad 398 to make the area that is in contact with the bump material more wettable selectively than the surrounding area of the conductive traces 394, 396 to achieve desired com- plementation characteristics. Lt; RTI ID = 0.0 > flux < / RTI > solution. The molten bump material remains locally within the region defined by the bump pad due to the wetting characteristics of the flux solution. The bump material does not advance to a less wettable area. An oxide layer or other insulating layer of the thin film may be formed over the areas where the bump material was not intended to be made less wettable. For this reason, a masking layer 392 is not needed around the die pump pad 232 or the integrated bump pad 398.

Since no SRO is formed around the die bump pad 232 or the integrated bump pad 398, the conductive traces 394 and 396 can be formed with finer pitches, that is, May be placed adjacent to adjacent structures. Assuming the same solder registration design rules, the pitch between the conductive traces 394 and 396 is given by P = (1.1D + W) / 2 where D is the base diameter of the bump 404 and W is the conductive trace 394, ). In one embodiment, given a bump diameter of 100 mu m and a trace line width of 20 mu m, the minimum escape pitch of the conductive traces 394 and 396 is 65 mu m. Bump formation eliminates the need to describe the ligament space of the masking material between adjacent openings, and the minimum resolvable SRO, as is known in the art.

22 shows a package-on-package (PoP) 405 having a semiconductor die 406 mounted on a semiconductor die 408 using die attach adhesives 410. Each of the semiconductor dies 406 and 408 has an active surface including analog and digital circuits implemented as an active element, a passive element, a conductive layer, and an insulating layer formed within the die and electrically interconnected depending on the electrical design and function of the die . For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed in the active surface for implementing analog or digital circuitry, such as a DSP, ASIC, memory, or other signal processing circuitry. Semiconductor dies 406 and 408 may also include IPDs, such as inductor capacitors and resistors for RF signal processing.

Semiconductor die 406 may be formed using bump material 416 formed on contact pad 418 using any embodiment from Figures 12a-12g, 13a-13d, 14a-14d, 15a-15c or 16a-16b Is mounted on a conductive trace (412) formed on a substrate (414). The conductive traces 412 are applicable to interconnect structures, as shown in Figures 8-10. The semiconductor die 408 is electrically connected to a contact pad 420 formed on the substrate 414 using a bond wire 422. The opposite end of the bond wire 422 is coupled to the contact pad 424 on the semiconductor die 406.

A masking layer 426 is formed over the substrate 414 and is open beyond the footprint of the semiconductor die 406. The masking layer 426 does not confine the bump material 416 to the conductive traces 412 during reflow but the open mask acts as a dam so that the encapsulant 428 does not contact the contact pad 420 or the bond wire 422 ). The encapsulant 428 is electrodeposited between the semiconductor die 408 and the substrate 414, similar to Figs. 17A-17C. The masking layer 426 blocks the MUF encapsulant 428 from reaching the contact pads 420 and the bond wires 422, which can lead to defects upon reaching them. The masking layer 426 allows a larger semiconductor die to be placed on a given substrate without the risk of the encapsulant 428 being pulled into the contact pad 420.

While one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to the embodiments without departing from the scope of the invention as set forth in the following claims.

Claims (25)

Providing a semiconductor die having a plurality of bumps formed over the surface of the semiconductor die,
Providing a substrate;
Forming a plurality of conductive traces on a surface of a substrate having an interconnect site;
Forming a masking layer on a surface of the substrate, the masking layer comprising a plurality of parallel and elongated openings exposing at least two of the conductive traces, wherein a plurality of conductive Thereby preventing flow of the bump material through the boundary of the plurality of elongated openings, while allowing flow of the bump material along the length of the traces,
Coupling the bump to the interconnect site such that the bump covers the top and sides of the interconnect site, the length of the bump along the interconnect site being greater than the width of the bump across the interconnect site, Is tapered along the length of the bump such that it is wider and closer to the interconnect die and closer to the interconnecting site,
And electrodepositing an encapsulant around the bumps between the semiconductor die and the substrate. The method according to claim 1,
Wherein one of the plurality of conductive traces passes under at least two of the elongated apertures. The method according to claim 1,
Wherein each length of the plurality of elongated apertures is perpendicular to each length of the plurality of conductive traces. The method according to claim 1,
Wherein the width of each of the plurality of elongated openings is 90 占 퐉 or less. The method according to claim 1,
Wherein the surface of the substrate is non-wettable to the bump material. The method according to claim 1,
Wherein the bump comprises a soluble portion and a non-soluble portion. Providing a semiconductor die,
Providing a substrate;
Forming a plurality of conductive traces on a surface of a substrate having an interconnect site;
Forming a masking layer over the surface of the substrate, the masking layer including a plurality of elongated openings exposing at least two of the conductive traces;
Forming a plurality of interconnect structures between the interconnecting sites of the semiconductor die and the substrate, wherein along the interconnect sites the length of the interconnect structure is greater than the width of the interconnect structure across the interconnect sites, The width of the connection structure is tapered along the length of the bump so as to be wider and closer to the semiconductor die and closer to the interconnect site,
And electrodepositing an encapsulant between the semiconductor die and the substrate. 8. The method of claim 7,
Wherein one of the plurality of conductive traces passes under at least two of the plurality of elongated apertures. 8. The method of claim 7,
Wherein each length of the plurality of elongated apertures is perpendicular to each length of the plurality of conductive traces. 8. The method of claim 7,
Wherein the width of each of the plurality of elongated openings is 90 占 퐉 or less. 8. The method of claim 7,
The elongated apertures allow flow of the bump material along the length of the plurality of conductive traces within the elongated apertures, but prevent the flow of bump material through the boundary of the elongated apertures Gt; 8. The method of claim 7,
Wherein the interconnect structure comprises a soluble portion and a non-soluble portion. 8. The method of claim 7,
Wherein the interconnect structure comprises a conductive pillar and a bump formed on the conductive pillar. Providing a semiconductor die;
Providing a substrate;
Forming a plurality of conductive traces on a surface of a substrate having interconnect sites,
Forming a masking layer over the surface of the substrate, the masking layer including a plurality of elongated openings exposing at least two of the conductive traces; And
Forming a plurality of the interconnect structures between the interconnecting sites of the semiconductor die and the substrate such that the interconnect structure covers the top and sides of the interconnect sites, Wherein the length of the structure is greater than the width of the interconnect structure across the interconnect sites. 15. The method of claim 14,
≪ / RTI > further comprising electrodepositing an encapsulant between the semiconductor die and the substrate. 15. The method of claim 14,
Wherein one of the plurality of conductive traces passes under at least two of the plurality of elongated apertures. 15. The method of claim 14,
Wherein each length of the plurality of elongated apertures is perpendicular to each length of the plurality of conductive traces. 15. The method of claim 14,
Wherein the width of each of the plurality of elongated openings is 90 占 퐉 or less. 15. The method of claim 14,
Wherein the interconnect structure comprises a soluble portion and a non-soluble portion. 15. The method of claim 14,
Wherein the interconnect structure comprises a conductive pillar and a bump formed on the conductive pillar. A semiconductor die;
A substrate having interconnect sites and having a plurality of conductive traces formed on the surface of the substrate;
A masking layer formed over the surface of the substrate, the masking layer including a plurality of elongated openings exposing at least two of the conductive traces;
A plurality of interconnect structures formed between the interconnecting sites of the semiconductor die and the substrate, the interconnect structure having a width that is wider and closer to the semiconductor die and a length of the interconnect structure Tapered along -
And an encapsulating material electrodeposited between the semiconductor die and the substrate. 22. The method of claim 21,
Wherein one of the plurality of conductive traces passes under at least two of the plurality of elongated apertures. 22. The method of claim 21,
Wherein each length of the plurality of elongated apertures is perpendicular to each length of the plurality of conductive traces. 22. The method of claim 21,
Wherein the interconnect structure comprises a soluble portion and a non-soluble portion. 22. The method of claim 21,
Wherein the interconnect structure comprises a conductive pillar and a bump formed on the conductive pillar.

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