JP2022522938A - 構成要素の埋め込みアレイを有するパッケージデバイス - Google Patents
構成要素の埋め込みアレイを有するパッケージデバイス Download PDFInfo
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- 239000012212 insulator Substances 0.000 claims abstract description 4
- 239000004020 conductor Substances 0.000 claims description 66
- 239000003990 capacitor Substances 0.000 claims description 64
- 238000000034 method Methods 0.000 claims description 22
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 238000010586 diagram Methods 0.000 abstract description 10
- 238000001816 cooling Methods 0.000 description 9
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
Description
本出願は、「構成要素の埋め込みアレイを有するPCT(PCT HAVING EMBEDDED ARRAY OF COMPONENTS)」と題する、2019年1月7日に出願された米国特許出願第62/789021号の優先権を主張し、また、「構成要素の埋め込みアレイを有するパッケージデバイス(PACKAGED DEVICE HAVING IMBEDDED ARRAY OF COMPONENTS)」と題する、2019年1月16日に出願された米国特許出願第62/793046号の優先権を主張し、それらの開示は、それらの全体が参照により本明細書に組み込まれる。
Claims (22)
- 内部に含まれる埋め込み受動素子のアレイを有する埋め込み構成要素アレイ層と、
内部に形成された複数のトレースおよび複数のビアを有する、前記埋め込み構成要素アレイ層の第1の表面に隣接して存在する集積ファンアウト(InFO)層と、前記埋め込み構成要素アレイ層の第2の表面に隣接して存在し、少なくとも前記InFO層に電気的に結合された絶縁体層と、
前記埋め込み構成要素アレイ層を通過し、前記InFO層の前記複数のビアのうちのいくつかに電気的に結合された複数のビアと、を備える、構造。 - 前記InFO層への電気接続を提供する第1のはんだボールと、
前記埋め込み構成要素アレイ層を通過する前記複数のビアへの電気接続を提供する第2のはんだボールと、をさらに備える、請求項1に記載の構造。 - 前記構成要素のアレイは、
集中コンデンサ、
集中インダクタ、
集中抵抗器、または
集積回路(IC)
のうちの少なくとも1つを含む、請求項1に記載の構造。 - 内部に含まれる埋め込み受動素子の第1のアレイを有する第1の埋め込み構成要素アレイ層と、
内部に含まれる埋め込み受動素子の第2のアレイを有する第2の埋め込み構成要素アレイ層と、
内部に形成された第1の複数のトレースおよび第2の複数のビアを有する、前記第1の埋め込み構成要素アレイ層の第1の表面に隣接して存在する第1の集積ファンアウト(InFO)層と、
内部に形成された第2の複数のトレースおよび第2の複数のビアを有する、前記第2の埋め込み構成要素アレイ層の第1の表面に隣接して存在する第2のInFO層と、
前記第1の埋め込み構成要素アレイ層の第2の表面に隣接し、前記第2の埋め込み構成要素アレイ層の第2の表面に隣接して存在する接続層であって、結果、前記接続層が前記第1の埋め込み構成要素アレイ層と前記第2の埋め込み構成要素アレイ層との間に挟まれ、内部に形成されている第3の複数のトレースおよび第3の複数のビアを有する前記接続層と、
前記第1の埋め込み構成要素アレイ層を通過する第1の複数のビアと、
前記第2の埋め込み構成要素アレイ層を通過する第2の複数のビアと、を備える、構造。 - 前記第1のInFO層への電気接続を提供する第1のはんだボールと、
第2のInFO層への電気接続を提供する第2のはんだボールと、をさらに備える、請求項4に記載の構造。 - 前記構成要素のアレイは、
集中コンデンサ、
集中インダクタ、
集中抵抗器、または
集積回路(IC)
のうちの少なくとも1つを含む、請求項4に記載の構造。 - プリント回路基板(PCB)であって、
コアと、
前記コア内に形成された構成要素のアレイと、
前記構成要素のアレイに結合された複数の導体と、
前記PCBの外部の信号ルーティングを提供する複数の導体と、を備える、プリント回路基板(PCB)。 - 電気的遮蔽を提供する複数の導体をさらに備える、請求項7に記載のPCB。
- 前記構成要素のアレイに結合された前記複数の導体は、前記PCBの外部の複数の構成要素への接続を提供する、請求項7に記載のPCB。
- 前記構成要素のアレイは、
集中コンデンサ、
集中インダクタ、
集中抵抗器、または
集積回路(IC)
のうちの少なくとも1つを含む、請求項7に記載のPCB。 - プリント回路基板(PCB)を構築するための方法であって、
内部に分散された構成要素のアレイを有するコアを形成することと、
前記構成要素のアレイに結合された複数の導体を形成することと、
前記PCBの外部の信号ルーティングを提供する複数の導体を形成することと、を含む、方法。 - 電気的遮蔽を提供する複数の導体を形成することをさらに含む、請求項11に記載の方法。
- 前記構成要素のアレイに結合された前記複数の導体が、前記PCBの外部の複数の構成要素への接続を提供する、請求項11に記載の方法。
- 前記構成要素のアレイは、
集中コンデンサ、
集中インダクタ、
集中抵抗器、または
集積回路(IC)
のうちの少なくとも1つを含む、請求項11に記載の方法。 - プリント回路基板(PCB)であって、
第1のコアと、
前記第1のコア内に形成された構成要素の第1のアレイと、
第2のコアと、
前記第2のコア内に形成された構成要素の第2のアレイと、
前記構成要素の第1のアレイに結合された複数の導体と、
前記構成要素の第2のアレイに結合された複数の導体と、
前記PCBの外部の信号ルーティングを提供する複数の導体と、を備える、プリント回路基板(PCB)。 - 電気的遮蔽を提供する複数の導体をさらに備える、請求項15に記載のPCB。
- 前記構成要素の第1のアレイに結合された前記複数の導体は、前記PCBの外部の複数の構成要素への接続を提供する、請求項15に記載のPCB。
- 前記構成要素の第1のアレイは、
集中コンデンサ、
集中インダクタ、
集中抵抗器、または
集積回路(IC)
のうちの少なくとも1つを含む、請求項15に記載のPCB。 - プリント回路基板(PCB)コンデンサを構築するための方法であって、
内部に分散された構成要素の第1のアレイを有する第1のコアを形成することと、
内部に分散された構成要素の第2のアレイを有する第2のコアを形成することと、
前記構成要素の第1のアレイに結合された複数の導体を形成することと、
前記構成要素の第2のアレイに結合された複数の導体を形成することと、
前記PCBの外部の信号ルーティングを提供する複数の導体を形成することと、を含む、方法。 - 電気的遮蔽を提供する複数の導体を形成することをさらに含む、請求項19に記載の方法。
- 前記構成要素の第1のアレイに結合された前記複数の導体は、前記PCBの外部の複数の構成要素への接続を提供する、請求項19に記載の方法。
- 前記構成要素の第1のアレイは、
集中コンデンサ、
集中インダクタ、
集中抵抗器、または
集積回路(IC)
のうちの少なくとも1つを含む、請求項19に記載の方法。
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