TWI744922B - 積體電路裝置及形成封裝結構的方法 - Google Patents

積體電路裝置及形成封裝結構的方法 Download PDF

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TWI744922B
TWI744922B TW109117962A TW109117962A TWI744922B TW I744922 B TWI744922 B TW I744922B TW 109117962 A TW109117962 A TW 109117962A TW 109117962 A TW109117962 A TW 109117962A TW I744922 B TWI744922 B TW I744922B
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sealant
dielectric layer
package structure
interposer
forming
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TW109117962A
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TW202046416A (zh
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余振華
盧思維
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台灣積體電路製造股份有限公司
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Abstract

本揭露實施例提供一種形成封裝結構的方法，包括將裝置晶粒接合到中介層。中介層包括貫通導孔，從中介層的半導體基板的頂表面延伸到半導體基板的頂表面與底表面之間的中間處。執行分割製程，以將中介層和裝置晶粒鋸成一封裝結構。所述方法還包括將封裝結構放置在載體之上、將封裝結構密封在密封劑中、減薄密封劑和中介層的半導體基板，直到露出貫通導孔、以及形成多個重分佈線路，其中重分佈線路中之一者與貫通導孔接觸。

Description

積體電路裝置及形成封裝結構的方法
本發明實施例係關於一種半導體封裝技術，特別係有關於一種基板上晶圓上晶片(CoWoS)封裝結構極其形成方法。
在封裝積體電路中，多個晶粒(dies)可以被接合到中介層晶圓(interposer wafer)上，中介層晶圓之中包括多個中介層(interposers)。在完成晶粒的接合之後，底部填充材料(underfill)可以被分配到晶粒與中介層晶圓之間的間隙中。然後，可以執行固化製程以固化底部填充材料。
固化後的底部填充材料可能收縮。結果，固化的底部填充材料對晶粒和中介層晶圓施加應力，並且可能導致中介層晶圓翹曲。中介層晶圓的翹曲進一步導致後續製程中的困難。舉例來說，在後續製程(例如，模製(molding)、研磨、減薄(thinning)等)中，需要通過真空將中介層晶圓固定在工作台(chuck table)上，以便在其上形成金屬線路和焊接區域(solder regions)。然而，在中介層晶圓具有翹曲的情況下，中介層晶圓可能無法被固定在工作台上。
本揭露一些實施例提供一種形成封裝結構的方法，包括將裝置晶粒接合到中介層。中介層包括貫通導孔，從中介層的半導體基板的頂表面延伸 到半導體基板的頂表面與底表面之間的中間處。所述方法還包括執行第一分割製程，以將中介層和裝置晶粒鋸成一第一封裝結構。所述方法還包括將第一封裝結構放置在載體之上。所述方法還包括將第一封裝結構密封在第一密封劑中。所述方法還包括減薄密封劑和中介層的半導體基板，直到露出貫通導孔。此外，所述方法包括形成多個重分佈線路，其中重分佈線路中之一者與貫通導孔接觸。
本揭露一些實施例提供一種形成封裝結構的方法，包括將多個中介層密封在密封劑中，中介層被密封劑彼此分開，其中中介層包括多個貫通導孔，延伸到中介層的多個半導體基板中。所述方法還包括研磨中介層以去除部分的半導體基板，其中貫通導孔的表面被露出。所述方法還包括形成第一介電層，第一介電層在半導體基板和中介層的貫通導孔之上，並且與半導體基板和貫通導孔接觸。所述方法還包括形成延伸到第一介電層中的多個重分佈線路，以接觸中介層的貫通導孔。此外，所述方法包括鋸穿密封劑，以將中介層分成多個封裝結構。
本揭露一些實施例提供一種積體電路裝置，包括封裝結構、第一密封劑、介電層以及多個重分佈線路。封裝結構包括裝置晶粒以及與裝置晶粒接合的中介層。中介層包括半導體基板以及貫穿半導體基板的貫穿孔。第一密封劑將封裝結構密封在其中。介電層接觸半導體基板和第一密封劑。重分佈線路延伸到介電層中，其中重分佈線路中之一者與貫通導孔接觸。
20:晶圓/中介層晶圓
22:基板
24:貫通導孔
26:隔離襯層
28:互連結構
30:介電層
32:金屬線路/重分佈層
34:導孔/重分佈層
36:電連接件
38:電連接件
40:中介層
42:封裝部件/(裝置)晶粒
44:底部填充材料
46:密封劑
46A:基底材料
46B:填料顆粒
48:重建晶圓
50:劃線
52:晶粒附接膜
54:封裝結構
60:載體
62:釋放膜
64:緩衝層
66:重分佈線路
68:介電層
70:開口
72:(金屬)晶種層
74:光阻
76:開口
78:金屬柱/貫通導孔
80:密封劑
80A:基底材料
80B:填料顆粒
82:介電層
84:開口
86:重分佈線路
86A:導孔
86B:金屬線路
88:介電層
90:重分佈線路
92:介電層
94:重分佈線路
96:介電層
97:基板
100:重建晶圓
102:開口
103:開口
104:積體被動裝置
106:焊接區域
108:底部填充材料
110:凸塊下金屬層
112:電連接件
114:劃線
116:封裝結構
120:虛線
124:部分
200:製程流程
202,204,206,208,210,212,214,216,218,220,222,224,226,228,230,232:製程
第1圖到第18圖是根據一些實施例的形成封裝結構的中間階段的剖視圖。
第19圖到第24圖是根據一些實施例的形成封裝結構的中間階段的剖視圖。
第25圖示出了根據一些實施例的封裝結構的一部分的放大圖。
第26圖示出了根據一些實施例的用於形成封裝結構的製程流程。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下描述具體的構件及其排列方式的實施例以闡述本揭露。當然，這些實施例僅作為範例，而不該以此限定本揭露的範圍。例如，在說明書中敘述了一第一特徵形成於一第二特徵之上或上方，其可能包含第一特徵與第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於第一特徵與第二特徵之間，而使得第一特徵與第二特徵可能未直接接觸的實施例。另外，在本揭露不同範例中可能使用重複的參考符號及/或標記，此重複係為了簡化與清晰的目的，並非用以限定所討論的各個實施例及/或結構之間有特定的關係。
再者，空間相關用語，例如“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用語，係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用語意欲包含使用中或操作中的裝置之不同方位。設備可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
根據各種實施例，提供了一種封裝結構及其形成方法。根據一些實施例示出了形成封裝結構的中間階段。討論了一些實施例的變形。在各視圖及說明性實施例中，相似的參考符號用來表示相似的元件。根據本揭露的一些實施例，一種形成基板上晶圓上晶片(Chip-on-Wafer-on-Substrate，CoWoS)封裝結構的製程包括：將多個裝置晶粒(device dies)接合到中介層晶圓上、密封所述裝置晶粒、以及將所得的重建晶圓(reconstructed wafer)鋸成多個分離的晶圓上晶片(Chip-on-Wafer，CoW)封裝結構。然後，將所述分離的晶圓上晶片(CoW)封裝 結構放置在載體(carrier)之上，接著進行密封。執行減薄/平坦化製程(thinning/planarization process)以露出中介層中的貫通導孔(through-vias)。使用扇出製程(fan-out processes)形成重分佈線路(Redistribution lines，RDLs)，其中重分佈線路和相應的介電層結合作為基板。因此，本揭露實施例中的基板是從中介層開始形成，而不是預先形成再接合到晶圓上晶片(CoW)封裝結構。
實施例將針對特定背景來描述，即基板上晶圓上晶片(CoWoS)封裝技術。然而，其他實施例也可以應用於其他封裝技術，例如將裝置晶粒接合到包括主動裝置(例如電晶體)的裝置晶圓(而不是中介層晶圓)，以及其他處理(processing)。本文中討論的實施例將提供示例以使得能夠製造或使用本揭露的標的，並且具有本領域普通技術的人員將容易理解，可以在不同實施例的預期範圍之內進行修改。以下討論的圖式中的相似的參考數字及符號表示相似的部件。儘管所討論的方法實施例可以特定順序來執行，但是其他方法實施例也可以其他任何邏輯順序來執行。
第1圖到第18圖示出了根據本揭露的一些實施例的形成封裝結構的中間階段的剖視圖。相應的製程也示意性地反應在第26圖所示的製程流程中。
第1圖示出了中介層晶圓20的剖視圖。中介層晶圓20可以包括基板22。根據一些實施例，基板22是一半導體基板，其可以進一步為結晶矽基板(crystalline silicon substrate)，儘管它也可以包含其他半導體材料，例如矽鍺、碳矽等。根據一些替代實施例，基板22是一介電基板。根據一些實施例，中介層晶圓20之中不具有主動裝置(例如電晶體及二極體)。在這些實施例中，中介層晶圓20可以包括或可以不包括形成於其中的被動裝置，例如電容、電感及電阻。根據一些替代實施例，晶圓20是一裝置晶圓，其包括形成在半導體基板22的頂表面上的主動裝置(例如電晶體，圖未示)。可以形成貫通導孔(有時稱為貫 通基板導孔(Through-Substrate Vias，TSVs))24，以從基板22的頂表面延伸到基板22中。當在矽基板中形成時，貫通導孔24有時也稱為貫通矽導孔。儘管未示於第1圖中，每個貫通導孔24可以由隔離襯層(isolation liner)26(參見第25圖)環繞，隔離襯層26由例如氧化矽、氮化矽等介電材料形成。隔離襯層26將個別的貫通導孔24與半導體基板22隔離。
在晶圓20是中介層晶圓的實施例中，中介層晶圓20包括複數個中介層40，其可以是彼此相同的。中介層晶圓20中的基板22可以在整個中介層晶圓20中連續地延伸，並且多個中介層40中的基板22是互連的，而不會被介電區域彼此分開。根據一些替代實施例，晶圓20可以包括裝置晶粒(也稱作晶片)，其可以是邏輯/核心晶粒、記體體晶粒、類比晶粒等。
互連結構28形成在半導體基板22之上，並且用於電性連接至貫通導孔24。互連結構28可以包括複數個介電層30。金屬線路32形成在介電層30中。導孔(via)34形成在上方和下方的金屬線路32之間，並且互連上方和下方的金屬線路32。金屬線路32和導孔34有時稱為重分佈層(Redistribution Layer，RDL)32/34。根據一些實施例，介電層30由氧化矽、氮化矽、碳化矽、氮氧化矽、其組合及/或其多層形成。或者，介電層30可以包括一或多個具有低k值的低k介電層。例如，介電層30中的低k介電材料的k值可以小於約3.0，或者小於約2.5。
電連接件36形成在中介層晶圓20的頂表面處。根據一些實施例，電連接件36包括金屬柱，其中在金屬柱的頂表面上方可以形成或可以不形成焊料蓋(solder caps)。根據一些替代實施例，電連接件36包括焊接區域(solder regions)。在其他實施例中，電連接件36可以是包括銅柱、鎳層、焊料蓋、化鎳浸金(Electroless Nickel Immersion Gold，ENIG)、化鎳浸鈀金(Electroless Nickel Electroless Palladium Immersion Gold，ENEPIG)及/或其類似物的複合凸塊。
進一步參考第1圖，封裝部件42接合到中介層40，例如通過覆晶接合(flip-chip bonding)。相應的製程顯示為如第26圖所示的製程流程200中的製程202。電連接件38通過電連接件36將封裝部件42中的電路電性耦合到重分佈層32/34和中介層晶圓20中的貫通導孔24。封裝部件42可以是包括邏輯電路、記憶體電路等的裝置晶粒。因此，封裝部件42在下文中也可替代地稱為晶粒42。根據本揭露的其他實施例，封裝部件42包括封裝結構，該封裝結構包括接合到相應的中介層的晶粒、封裝基板及/或其類似物。在每一個中介層40上方，可以有一個、兩個或更多個晶粒42接合在其上。
接下來，如第2圖所示，將底部填充材料(underfill)44分配到晶粒42與中介層晶圓20之間的空間(間隙)中。底部填充材料44可以包括聚合物、樹脂、環氧樹脂等作為基底材料，並且可以在其中包括填料顆粒。填料顆粒可以由氧化矽(silica)、氧化鋁等形成，並且可以具有球形形狀。然後，在固化製程中固化底部填充材料44。取決於底部填充材料44的類型，固化製程可以包括熱固化製程或紫外線(Ultra-Violet，UV)固化製程。
在施加底部填充材料44之後，將裝置晶粒42密封在密封劑46中。相應的製程顯示為如第26圖所示的製程流程200中的製程204。密封劑46可以是模塑料(molding compound)、模製底部填充材料(molding underfill)等。密封劑46的頂表面高於裝置晶粒42的頂表面。根據一些替代實施例，底部填充材料44和密封劑46在同一製程中被施加，例如，使用模製底部填充材料。
第3圖示意性地示出了密封劑46的一些細節。密封劑46可以包括基底材料46A以及在基底材料46A中的填料顆粒46B。基底材料46A可以是聚合物、樹脂、環氧樹脂等。填料顆粒46B可以是介電材料(例如，SiO2、Al2O3、氧化矽、鐵(Fe)的介電化合物、鈉(Na)的介電化合物等)的顆粒，並且可以具有球形形狀。而且，根據一些示例，如第3圖所示，球狀填料顆粒46B可以具有相 同或不同的直徑。
回到第2圖，固化密封劑46，然後進行平坦化製程，其可以是化學機械研磨(Chemical Mechanical Polish，CMP)製程或機械研磨製程。根據本揭露的一些實施例，在平坦化製程之後，一些或所有的裝置晶粒42的頂表面(其可以是半導體基板的頂表面)被露出。根據本揭露的一些實施例，在平坦化製程之後，裝置晶粒42被一層剩餘的密封劑46覆蓋。
在整個說明書中，包括中介層晶圓20、晶粒42、底部填充材料44以及密封劑46的結構統稱為重建晶圓(reconstructed wafer)48。重建晶圓48也稱作晶圓上晶片(CoW)晶圓。根據一些實施例，可以在分割製程(singulation process)之前將作為黏合膜的晶粒附接膜(Die-Attach Film，DAF)52黏附到重建晶圓48的頂表面，然後將晶粒附接膜與重建晶圓48一起鋸開。
在平坦化製程之後，執行分割製程以將重建晶圓48分離成單獨的封裝結構(packages)54。相應的製程顯示為如第26圖所示的製程流程200中的製程206。可以沿著中介層晶圓20的劃線50執行分割製程。第3圖示出了所得的封裝結構54中之一者(有時稱作晶圓上晶片(CoW)晶粒或晶圓上晶片(CoW)封裝結構)。經鋸切的晶粒附接膜52是附接到封裝結構54，並且可以與密封劑46和晶粒42的半導體基板(未單獨示出)接觸。
第3圖示出了封裝結構54的一個示例。作為平坦化製程之結果，一些填料顆粒46B被部分地研磨，導致一些填料顆粒46B的某些部分(例如第3圖中的底部部分)被去除，而頂部部分仍保留著。因此，所得的部分填料顆粒46B將具有平坦的底表面，該平坦的底表面與基底材料46A的底表面和裝置晶粒42的半導體基板共面(coplanar)。再者，由於分割製程，一些填料顆粒46B被鋸切，導致一些填料顆粒46B的某些部分(例如第3圖中所示最左邊的填料顆粒46B的左邊部分)被去除。因此，所得的部分填料顆粒46B將具有平坦的左或右表面(側 壁)，該平坦的表面與基底材料46A的側壁共面(齊平)。
第4圖到第20圖示出了扇出封裝結構(fan-out package)的形成，該扇出封裝結構具有封裝結構54封裝於其中。參考第4圖，提供載體60，並且在載體60上塗布釋放膜(release film)62。載體60由透明材料形成，並且可以是玻璃載體、陶瓷載體等。載體60可以具有圓形的俯視形狀，並且可以具有矽晶圓的尺寸。釋放膜62可以由光熱轉換(Light-To-Heat-Conversion，LTHC)塗層材料形成。釋放膜62可以通過塗布方式施加到載體60上。根據本揭露的一些實施例，光熱轉換塗層材料能夠在光/輻射(例如雷射)的熱的作用下分解，因此可以將載體60從形成在其上的結構釋放。
根據一些實施例，如第4圖所示，緩衝層64形成在釋放膜62上。聚合物緩衝層64可以由介電材料形成，其可以是例如聚苯並噁唑(polybenzoxazole，PBO)、聚酰亞胺、苯並環丁烯(benzocyclobutene，BCB)等的聚合物。重分佈線路66形成在緩衝層64之上。相應的製程顯示為如第26圖所示的製程流程200中的製程208。重分佈線路66的形成可以包括在緩衝層64之上形成晶種層(圖未示)，在晶種層之上形成圖案化的遮罩(例如圖案化的光阻，圖未示)，然後執行金屬鍍層(plating)製程以形成重分佈線路66。然後，去除圖案化的遮罩和晶種層之被圖案化的遮罩覆蓋的部分，留下如第4圖中所示的重分佈線路66。根據本揭露的一些實施例，晶種層包括鈦層和在鈦層之上的銅層。晶種層可以使用例如物理氣相沉積(Physical Vapor Deposition，PVD)來形成。可以使用例如電化學鍍或化學鍍(electroless plating)來執行鍍層。
進一步參考第4圖，介電層68形成在重分佈線路66上。相應的製程顯示為如第26圖所示的製程流程200中的製程210。介電層68的底表面可以與重分佈線路66和緩衝層64的頂表面接觸。根據本揭露的一些實施例，介電層68由聚合物形成，其可以是例如聚苯並噁唑、聚酰亞胺等的感光材料。根據 一些替代實施例，介電層68由例如氮化矽的氮化物、例如氧化矽的氧化物等形成。然後，對介電層68進行圖案化以在其中開口70。因此，重分佈線路66的一些焊墊部分(pad portions)通過介電層68中的開口70暴露。
參考第5圖，金屬晶種層72例如通過物理氣相沉積形成。相應的製程顯示為如第26圖所示的製程流程200中的製程212。根據本揭露的一些實施例，金屬晶種層72包括鈦層和在鈦層之上的銅層。根據本揭露的一些替代實施例，金屬晶種層72包括與緩衝層64接觸的銅層。
如第5圖所示，例如光阻74的鍍層遮罩(plating mask)形成在金屬晶種層72之上。相應的製程顯示為如第26圖所示的製程流程200中的製程214。然後，使用光微影遮罩(圖未示)在光阻74上執行曝光製程。在光阻74的後續顯影製程之後，在光阻74中形成開口76。金屬晶種層72的一些部分通過開口76暴露。
接下來，如第6圖所示，通過在開口76中鍍上金屬材料而形成金屬柱78。相應的製程顯示為如第26圖所示的製程流程200中的製程216。在共同的晶種形成和鍍層製程中，也形成導孔，其延伸到介電層68中以接觸重分佈線路66。金屬柱78可替代地稱為貫通導孔(through-vias)或貫通模製導孔(through-molding vias)，因為它們將穿透最終封裝結構中的隨後形成的密封材料(可以是模塑料)。鍍層的金屬材料可以是銅或銅合金。金屬柱78的頂表面低於光阻74的頂表面，從而使金屬柱78的形狀由開口76限定。金屬柱78可以具有基本上垂直和筆直的邊緣。或者，金屬柱78在剖視圖中可以具有沙漏形狀，其中金屬柱78的中間部分比相應的頂部和底部窄。
在隨後的步驟中，去除光阻74，並且暴露下方的金屬晶種層72的部分。然後，在蝕刻製程(例如，各向異性蝕刻步驟或等向性蝕刻步驟)中去除金屬晶種層72的暴露部分。因此，剩餘的晶種層72的邊緣可以與相應的上方的 金屬柱78的部分具有或基本上具有相同邊界(co-terminus)。所得的金屬柱78如第7圖中所示。在整個說明書中，在鍍層的金屬柱78正下方的金屬晶種層72的剩餘部分(延伸到介電層68中以接觸重分佈線路66的導孔)被認為是金屬柱78的部分。金屬柱78的俯視形狀包括但不限於圓形、矩形、六邊形、八邊形等。在形成金屬柱78之後，暴露介電層68。
第8圖示出了晶圓上晶片(CoW)封裝結構54的放置/附接，其中晶粒附接膜52將個別的封裝結構54黏附到介電層68。相應的製程顯示為如第26圖所示的製程流程200中的製程218。接下來，如第9圖所示，封裝結構54和金屬柱78被密封在密封劑80中。相應的製程顯示為如第26圖所示的製程流程200中的製程220。密封劑80填充相鄰的貫通導孔78之間的間隙以及貫通導孔78與封裝結構54之間的間隙。密封劑80可以包括模塑料、模製底部填充材料、環氧樹脂及/或樹脂。密封劑80的頂表面高於金屬柱78的頂端和封裝結構54的頂表面。模塑料可以包括基底材料80A(未在第9圖中示出，參考第25圖)以及在基底材料中的填料顆粒80B(未示出)。基底材料80A可以是樹脂、環氧樹脂等。填料顆粒80B可以是SiO2、Al2O3、氧化矽等的介電顆粒，並且可以具有球形形狀。而且，球狀填料顆粒可以具有相同或不同的直徑。基底材料80A和填料顆粒80B如第25圖所示。
在隨後的步驟中，如第10圖所示，執行例如化學機械研磨步驟或機械研磨步驟之類的平坦化步驟，以減薄(thin)密封劑80和中介層40中的基板22。密封劑80和中介層40中的基板22都被研磨。根據本揭露的一些實施例，執行平坦化製程，直到金屬柱78和中介層40中的貫通導孔24都被露出。另外，環繞貫通導孔24的隔離襯層26(參考第25圖)也被露出。由於平坦化製程，貫通導孔24和金屬柱78的頂端與密封劑80的頂表面齊平(共面)。金屬柱78在下文中可替換地稱為貫通導孔78，因為它們貫穿密封劑80。
第11圖到第13圖示出了一重分佈結構的形成，該重分佈結構位在封裝結構54和金屬柱78上方，並且連接至封裝結構54和金屬柱78。相應的製程顯示為如第26圖所示的製程流程200中的製程222。第11圖到第12圖示出了重分佈線路的第一層和相應的介電層的形成。參考第11圖，形成介電層82。根據本揭露的一些實施例，介電層82由例如聚苯並噁唑、聚酰亞胺等的聚合物形成。形成方法包括以可流動形式塗布介電層82，然後固化介電層82。根據本揭露的一些替代實施例，介電層82由例如氮化矽、氧化矽等無機介電材料形成。形成方法可以包括化學氣相沉積(Chemical Vapor Deposition，CVD)、原子層沉積(Atomic Layer Deposition，ALD)、電漿輔助化學氣相沉積(Plasma-Enhanced Chemical Vapor Deposition，PECVD)或其他適用的沉積方法。然後，例如通過光微影製程來形成開口84。根據一些實施例，在介電層82是由例如聚苯並噁唑或聚酰亞胺等的感光材料形成的情況下，開口84的形成涉及使用微影遮罩(圖未示)在介電層82上的曝光製程，以及對暴露的介電層82進行顯影。貫通導孔24和貫通導孔78通過開口84暴露。
接下來，參考第12圖，形成重分佈線路86。重分佈線路86包括形成在介電層82中以接觸貫通導孔24和貫通導孔78的導孔86A，以及在介電層82之上的金屬跡線(金屬線路)86B。根據本揭露的一些實施例，重分佈線路86以鍍層製程形成，該鍍層製程包括沉積金屬晶種層(圖未示)、在金屬晶種層上方形成和圖案化光阻(圖未示)、以及在金屬晶種層上方鍍上例如銅及/或鋁之類的金屬材料。金屬晶種層和鍍層的金屬材料可以由相同或不同的材料形成。然後，去除圖案化的光阻，接著蝕刻先前被圖案化的光阻覆蓋的金屬晶種層的部分。第25圖示出了重分佈線路86中之一者和介電層82的放大圖。
參考第13圖，在介電層82之上形成更多個介電層，並且在重分佈線路86之上形成連接到重分佈線路86的更多個重分佈線路。在一些示例中， 介電層包括介電層88、介電層92以及介電層96。在一些示例中，重分佈線路包括重分佈線路90和重分佈線路94。可以使用選自用於形成介電層82的候選材料的相同或不同組的材料來形成介電層88、介電層92以及介電層96，該材料可以包括聚苯並噁唑)、聚酰亞胺、苯並環丁烯或其他有機或無機材料。重分佈線路90和重分佈線路94的材料及形成過程可以與重分佈線路86的形成相同，包括形成晶種層、形成圖案化的遮罩、鍍上重分佈線路90和重分佈線路94、然後去除圖案化的遮罩和晶種層的不需要的部分。在整個說明書中，在釋放膜62上方的部件統稱為重建晶圓100。
如第25圖所示，重分佈線路86可以包括在介電層82中的導孔86A和在介電層82之上的金屬線路86B。重分佈線路86之從開口84(參考第11圖)形成的某些部份的頂表面可以凹陷到比直接覆蓋介電層82的金屬線路86B的頂表面更低的位置。形成在重分佈線路86之上的重分佈線路(例如重分佈線路90和重分佈線路94)可以具有相似的頗面輪廓。
接下來，從載體60上剝離如第13圖中所示的重建晶圓100。相應的製程顯示為如第26圖所示的製程流程200中的製程224。可以通過將光束(例如雷射光束)投射到釋放膜62上來執行剝離，從而由光束產生的熱量導致釋放膜62分解，並且從載體60上釋放重建晶圓100。然後，例如通過電漿清潔步驟去除釋放膜62的殘留物。所得的重建晶圓100如第14圖所示。
第15圖示出了在緩衝層64中形成開口102。根據一些實施例，開口102是使用雷射光束通過雷射鑽孔來形成。相應的製程顯示為如第26圖所示的製程流程200中的製程226。重分佈線路66用作雷射光束的停止層，並且重分佈線路66的一些部分通過開口102暴露。根據一些實施例，還形成開口103以暴露重分佈線路66的一些部分。根據一些其他實施例，沒有形成開口103。開口103可以用於散熱。舉例來說，在封裝所得的封裝結構時的最終結構中， 可以將熱介面材料(Thermal Interface Material，TIM)分配到開口103中以與重分佈線路66接觸，並且熱介面材料也與一散熱器(heat sink)接觸以將熱量逸散到散熱器中。
第16圖示出了積體被動裝置(Integrated Passive Device，IPD)104接合到重分佈線路66。相應的製程顯示為如第26圖所示的製程流程200中的製程228。根據一些實施例，積體被動裝置104包括電容、電感、電阻或其組合，其形成為分離的裝置晶粒。可以通過焊接區域106進行接合。底部填充材料108可以分配在積體被動裝置104與重建晶圓100之間。
第17圖示出了根據一些示例性實施例的凸塊下金屬層(Under-Bump Metallurgies，UBM)110和電連接件112的形成。相應的製程顯示為如第26圖所示的製程流程200中的製程230。根據本揭露的一些實施例，凸塊下金屬層110形成為延伸到介電層96中的開口中以接觸重分佈線路94中的金屬焊墊。凸塊下金屬層110可以由鎳、銅、鈦或其多層形成。根據一些示例性實施例，凸塊下金屬層110包括鈦層和在鈦層之上的銅層。
然後，形成電連接件112。電連接件112的形成可以包括在凸塊下金屬層110的暴露部分上放置焊球(solder balls)，然後對焊球進行回焊(reflowing)。所得的電連接件112為焊接區域。根據本揭露的一些替代實施例，電連接件112的形成包括執行一鍍層步驟以在凸塊下金屬層110之上形成焊料層，然後對焊料層進行回焊。電連接件112還可以包括非焊料金屬柱，或者在非焊料金屬柱之上的金屬柱及焊料蓋，其也可以通過鍍層來形成。
接下來，將重建晶圓100放置在切割膠帶(圖未示)上，切割膠帶附接到框架(圖未示)上。根據本揭露的一些實施例，電連接件112或積體被動裝置104都與切割膠帶接觸。接下來，在晶粒鋸切製程(die-saw process)中(例如，使用刀片)將重建晶圓100分割。相應的製程顯示為如第26圖所示的製程流程 200中的製程232。刀片通過重建晶圓100的劃線114，並且形成封裝結構116。第18圖示出了根據一些實施例的所得的封裝結構116。封裝結構116也稱為基板上晶圓上晶片封裝結構或CoWoS封裝結構，其中重分佈線路86、重分佈線路90和重分佈線路94以及相應的介電層82、介電層88、介電層92和介電層96共同作為基板97。CoWoS封裝結構116與傳統的CoWoS封裝結構的不同之處在於，基板97在扇出製程(fan-out process)中是直接從中介層40和密封劑80形成，而不是預先形成(為有核心或無核心的封裝基板)再接合到中介層。
第19圖到第24圖示出了根據本揭露的一些替代實施例的形成封裝結構的中間階段的剖視圖。這些實施例與第1圖到第18圖所示的實施例類似，除了沒有在與封裝結構54相同的高度處形成貫穿孔、沒有附接積體被動裝置(IPD)、以及重分佈線路是形成在封裝結構54的一側而不是兩側之外。除非另外說明，否則這些實施例中的部件的材料和形成過程與第1圖到第18圖所示的實施例中由相同的參考符號所標示的相同部件基本上相同。因此，可以在對第1圖到第18圖所示的實施例的討論中找到關於第19圖到第24圖所示的部件的形成過程及材料的細節。
這些實施例的初始步驟基本上與第1圖到第3圖所示的相同，其中形成了封裝結構54。接著，參考第19圖，釋放膜62塗布在載體60上，並且緩衝層64形成在釋放膜62上。接下來，封裝結構54通過晶粒附接膜52附接到緩衝層64上。根據本揭露的一些實施例，在緩衝層64上沒有形成金屬柱。
參考第20圖，封裝結構54和晶粒附接膜52被密封在密封劑80中。根據本揭露的一些實施例，封裝結構54被完全密封，其中密封劑80的頂表面高於封裝結構54的頂表面。然後，固化密封劑80，接著執行平坦化製程以減薄中介層40中的半導體基板22。所得的結構如第21圖所示。在平坦化製程之後，露出貫通導孔24(以及如第25圖中所示的隔離襯層26)，其中貫通導孔24 的頂表面與密封劑80的頂表面共面。
第22圖示出了重分佈結構(基板97)的形成，該重分佈結構(基板97)包括例如介電層82、介電層88、介電層92和介電層96以及重分佈線路86、重分佈線路90和重分佈線路94。在形成重分佈結構之後，將所得的重建晶圓100從載體60上剝離。在隨後的製程中，如第23圖所示，形成凸塊下金屬層(UBM)110和電連接件112。然後，將重建晶圓100分割，並且所得的封裝結構116如第24圖所示。
根據一些實施例，封裝結構116包括密封在密封劑80中的晶粒附接膜52。緩衝層64可以附接到晶粒附接膜52和密封劑80。根據一些替代實施例，可以研磨重建晶圓100以去除緩衝層64和晶粒附接膜52。第24圖示出了虛線120，其中當去除緩衝層64和晶粒附接膜52時，封裝結構116的底表面可以處在由虛線120所示的高度。
如第18圖到第24圖所示的封裝結構116可以接合到其他的封裝結構上。舉例來說，第18圖到第24圖中的封裝結構116的電連接件112可以接合到另一個封裝部件，例如印刷電路板、框架、封裝結構或其類似物。底部填充材料(未示出)也可以設置在封裝結構116和對應接合的封裝部件之間以保護電連接件112。可以附接熱介面材料和散熱器，其中熱介面材料在封裝結構116與散熱器之間並與之接觸。熱介面材料也可以延伸到第15圖中的開口103中。
第25圖示出了如第18圖中所示的封裝結構116的一部分124的放大圖。示出了隔離襯層26環繞貫通導孔24。隔離襯層26可以由例如氧化矽、氮化矽等的介電材料形成。隔離襯層26和貫通導孔24的頂表面是共面的，並且與重分佈線路86的導孔86A的底表面接觸。取決於貫通導孔24和導孔86A的相對尺寸，隔離襯層26的頂表面也可以接觸介電層82的底表面。再者，貫通導孔24可以與重分佈線路86的晶種層接觸，該晶種層可以包含例如鈦。第25圖 示出了密封劑80包括一些與介電層82接觸的部分填料顆粒80B。由於填料顆粒80B的這些部分在第10圖所示的平坦化製程中被研磨，這些部分填料顆粒80B可以具有與介電層82接觸的平坦的頂表面。作為比較，與介電層68接觸的部分填料顆粒80B是未研磨的完整球形顆粒，並且可以具有圓形的底表面。
除此之外，封裝結構54中的密封劑46具有與密封劑80接觸的左邊緣。根據一些實施例，一些部分填料顆粒46B是在密封劑46與密封劑80之間的介面處，並且部分填料顆粒46B具有與密封劑80和晶粒附接膜52接觸的平坦表面。
在上面說明的實施例中，根據本揭露的一些實施例討論了一些製程和特徵。也可以包括其他的特徵和製程。舉例來說，可以包括測試結構以幫助對3D封裝或3DIC裝置進行驗證測試。這些測試結構可以包括例如形成在重分佈層中或在基板上的測試墊，該些測試墊允許測試3D封裝或3DIC裝置、使用探針及/或探針卡等。可以對中間結構以及最終結構進行驗證測試。此外，本文中揭露的結構和方法可以與測試方法結合使用，該測試方法包含對已知的優良晶粒的中間驗證，以提高成品率及降低成本。
本揭露實施例具有一些有利特徵。一些晶圓上晶片(CoW)封裝結構(包括中介層)很大，例如其尺寸大於約70mm x 70mm。在傳統的封裝製程中，大的晶圓上晶片封裝結構可能包括焊接區域，並可能在中介層的貫穿孔上形成重分佈線路。晶圓上晶片封裝結構通過焊接區域接合到預先形成的封裝基板(可能是有核心或無核心的基板)。由於晶圓上晶片封裝結構很大，而且由於中介層與預先形成的封裝基板的熱膨脹係數(Coefficient of Thermal Expansion，CTE)之間存在顯著差異，所以這些封裝結構會遇到例如焊接點不良、底部填充材料孔隙(void)、平坦度差以及可靠度降低等問題。根據本揭露的實施例，使用積體扇出(Integrated Fan-Out，InFO)製程來直接從晶圓上晶片(CoW)封裝結構形成基板， 因此，沒有使用焊接區域將晶圓上晶片封裝結構接合到基板。另外，中介層晶圓的減薄(thinning)是在鋸切中介層晶圓之後而不是之前執行。如此一來，提高了所得的封裝結構的可靠度。
根據本揭露的一些實施例，提供一種形成封裝結構的方法，包括將裝置晶粒接合到中介層。中介層包括貫通導孔，從中介層的半導體基板的頂表面延伸到半導體基板的頂表面與底表面之間的中間處。所述方法還包括執行第一分割製程，以將中介層和裝置晶粒鋸成一第一封裝結構。所述方法還包括將第一封裝結構放置在載體之上。所述方法還包括將第一封裝結構密封在第一密封劑中。所述方法還包括減薄密封劑和中介層的半導體基板，直到露出貫通導孔。此外，所述方法包括形成多個重分佈線路，其中重分佈線路中之一者與貫通導孔接觸。在一些實施例中，所述方法更包括形成與第一封裝結構和第一密封劑接觸的介電層，其中重分佈線路延伸到介電層中，且其中貫通導孔由隔離襯層環繞，並且隔離襯層與介電層和重分佈線路中之一者接觸。在一些實施例中，所述方法更包括在將裝置晶粒接合到中介層之後，將裝置晶粒密封在第二密封劑中，其中在第一分割製程中，第二密封劑被鋸穿。在一些實施例中，中介層沒有主動裝置。在一些實施例中，在減薄中介層的半導體基板之前，半導體基板的一部分與貫通導孔重疊，並且在減薄之操作中，半導體基板的所述部分被去除。在一些實施例中，所述方法更包括在載體之上形成金屬柱，其中金屬柱密封在第一密封劑中，且其中在減薄第一密封劑之後，金屬柱被露出。在一些實施例中，所述方法更包括在載體之上形成多個額外的重分佈線路，其中第一封裝結構放置在額外的重分佈線路之上，以及將被動裝置接合到額外的重分佈線路。在一些實施例中，所述方法更包括執行第二分割製程以形成第二封裝結構，其中第一封裝結構、部分的第一密封劑以及部分的重分佈線路是在第二封裝結構中。
根據本揭露的一些實施例，提供一種形成封裝結構的方法，包括將多個中介層密封在密封劑中，中介層被密封劑彼此分開，其中中介層包括多個貫通導孔，延伸到中介層的多個半導體基板中。所述方法還包括研磨中介層以去除部分的半導體基板，其中貫通導孔的表面被露出。所述方法還包括形成第一介電層，第一介電層在半導體基板和中介層的貫通導孔之上，並且與半導體基板和貫通導孔接觸。所述方法還包括形成延伸到第一介電層中的多個重分佈線路，以接觸中介層的貫通導孔。此外，所述方法包括鋸穿密封劑，以將中介層分成多個封裝結構。在一些實施例中，在鋸穿密封劑之操作中，中介層沒有被鋸穿。在一些實施例中，所述方法更包括接合多個裝置晶粒，其中裝置晶粒中之每一者接合到中介層中之一者，且其中密封劑包括與中介層處在相同高度的第一部分以及與裝置晶粒處在相同高度的第二部分。在一些實施例中，所述方法更包括將裝置晶粒中之所述一者密封在額外的密封劑中，以及在將中介層密封在密封劑中之前，鋸穿額外的密封劑。在一些實施例中，第一介電層在密封劑之上延伸，並且第一介電層的底表面接觸密封劑的頂表面。在一些實施例中，中介層之中沒有主動裝置和被動裝置。
根據本揭露的一些實施例，提供一種積體電路裝置，包括封裝結構、第一密封劑、介電層以及多個重分佈線路。封裝結構包括裝置晶粒以及與裝置晶粒接合的中介層。中介層包括半導體基板以及貫穿半導體基板的貫穿孔。第一密封劑將封裝結構密封在其中。介電層接觸半導體基板和第一密封劑。重分佈線路延伸到介電層中，其中重分佈線路中之一者與貫通導孔接觸。在一些實施例中，中介層更包括環繞貫通導孔的隔離襯層，其中隔離襯層將貫通導孔與半導體基板分開，並且隔離襯層與重分佈線路和介電層中之一者接觸。在一些實施例中，中介層之中沒有主動裝置。在一些實施例中，封裝結構更包括第二密封劑，將裝置晶粒密封在其中，其中第二密封劑的側壁與中介層的相應的 側壁齊平。在一些實施例中，所述積體電路裝置更包括金屬柱以及被動裝置，其中金屬柱貫穿第一密封劑，被動裝置在第一密封劑之相對於重分佈線路的相反側上，其中被動裝置電性耦接至金屬柱。在一些實施例中，所述積體電路裝置更包括與封裝結構接觸的黏合膜，其中黏合膜密封在第一密封劑中。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
200:製程流程
202,204,206,208,210,212,214,216,218,220,222,224,226,228,230,232:製程

Claims (15)

  1. 一種形成封裝結構的方法，包括：將一裝置晶粒接合到一中介層，其中該中介層包括一貫通導孔，該貫通導孔從該中介層的一半導體基板的一頂表面延伸到該半導體基板的該頂表面與一底表面之間的一中間處；執行一第一分割製程，以將該中介層和該裝置晶粒鋸成一第一封裝結構；在一載體之上形成複數個第一重分佈線路；將該第一封裝結構放置在該載體和該些第一重分佈線路之上，其中該第一封裝結構通過一晶粒附接膜附接到該些第一重分佈線路，並且該裝置晶粒與該晶粒附接膜接觸；將該第一封裝結構密封在一第一密封劑中；減薄該第一密封劑和該中介層的該半導體基板，直到露出該貫通導孔；形成複數個第二重分佈線路，其中該些第二重分佈線路中之一重分佈線路與該貫通導孔接觸；以及將一被動裝置接合到該些第一重分佈線路。
  2. 如請求項1之形成封裝結構的方法，更包括形成與該第一封裝結構和該第一密封劑接觸的一介電層，其中該些第二重分佈線路延伸到該介電層中，且其中該貫通導孔由一隔離襯層環繞，並且該隔離襯層與該介電層和該重分佈線路中之一者接觸。
  3. 如請求項1之形成封裝結構的方法，更包括在將該裝置晶粒接合到該中介層之後，將該裝置晶粒密封在一第二密封劑中，其中在該第一分割製程中，該第二密封劑被鋸穿。
  4. 如請求項1之形成封裝結構的方法，其中在減薄該中介層的該半導體基板之前，該半導體基板的一部分與該貫通導孔重疊，並且在該減薄 之操作中，該半導體基板的該部分被去除。
  5. 如請求項1之形成封裝結構的方法，更包括在該載體之上形成一金屬柱，其中該金屬柱密封在該第一密封劑中，且其中在減薄該第一密封劑之期間，該金屬柱和該貫通導孔被露出。
  6. 如請求項1之形成封裝結構的方法，更包括在形成該些第二重分佈線路之後，執行一第二分割製程以形成一第二封裝結構，其中該第一封裝結構、部分的該第一密封劑以及部分的該些第二重分佈線路係在該第二封裝結構中。
  7. 一種形成封裝結構的方法，包括：在一載體之上形成複數個第一重分佈線路；在該些第一重分佈線路之上形成一介電層；將複數個封裝結構放置在該介電層之上，其中該些封裝結構包括複數個中介層；在一共同的鍍層製程中形成複數個金屬柱和複數個導孔，其中該些金屬柱在該介電層之上，該些導孔延伸到該介電層中以接觸該些第一重分佈線路；將該些中介層和該些金屬柱密封在一密封劑中，該些中介層被該密封劑彼此分開，其中該些中介層包括複數個貫通導孔，該些貫通導孔延伸到該些中介層的複數個半導體基板中；研磨該些中介層和該些金屬柱以去除部分的該些半導體基板，其中該些貫通導孔和該些金屬柱的表面被露出；形成一第一介電層，該第一介電層在該些半導體基板和該些中介層的該些貫通導孔之上，並且與該些半導體基板和該些貫通導孔接觸；形成延伸到該第一介電層中的複數個第二重分佈線路，以接觸該些中介層的該些貫通導孔和該些金屬柱；以及 鋸穿該密封劑，以將該些中介層分成複數個額外的封裝結構。
  8. 如請求項7之形成封裝結構的方法，更包括將一被動裝置接合到該些第一重分佈線路。
  9. 如請求項7之形成封裝結構的方法，更包括接合複數個裝置晶粒，其中該些裝置晶粒中之每一者接合到該些中介層中之一者，且其中該密封劑包括與該些中介層處在相同高度的一第一部分以及與該些裝置晶粒處在相同高度的一第二部分。
  10. 如請求項9之形成封裝結構的方法，更包括：將該些裝置晶粒中之該一者密封在一額外的密封劑中；以及鋸穿該額外的密封劑。
  11. 如請求項7之形成封裝結構的方法，其中該第一介電層在該密封劑之上延伸，並且該第一介電層的一底表面接觸該密封劑的一頂表面。
  12. 一種積體電路裝置，包括：複數個第一重分佈線路，內埋在一介電層中；一封裝結構，在該介電層和該些第一重分佈線路之上，該封裝結構包括：一裝置晶粒；一中介層，與該裝置晶粒接合，其中該中介層包括：一半導體基板；以及一貫通導孔，貫穿該半導體基板；一第一密封劑，在該介電層和該些第一重分佈線路之上，並將該封裝結構密封在其中；一第一介電層，接觸該半導體基板和該第一密封劑；以及複數個第二重分佈線路，延伸到該第一介電層中，其中該些第二重分佈線路中之一重分佈線路與該貫通導孔接觸，其中該些第一重分佈線路和該些第二重 分佈線路位於該封裝結構的兩側。
  13. 如請求項12之積體電路裝置，其中該中介層更包括環繞該貫通導孔的一隔離襯層，其中該隔離襯層將該貫通導孔與該半導體基板分開，並且該隔離襯層與該重分佈線路和該第一介電層中之一者接觸。
  14. 如請求項12之積體電路裝置，其中該封裝結構更包括一第二密封劑，將該裝置晶粒密封在其中，其中該第二密封劑的複數個側壁與該中介層的相應的複數個側壁齊平。
  15. 如請求項12之積體電路裝置，更包括：一金屬柱，貫穿該第一密封劑；以及一被動裝置，在該第一密封劑之相對於該些第二重分佈線路的一相反側上，其中該被動裝置通過該些第一重分佈線路電性耦接至該金屬柱。
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