CN115224013A - 芯片封装结构 - Google Patents

芯片封装结构 Download PDF

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Publication number
CN115224013A
CN115224013A CN202211025463.4A CN202211025463A CN115224013A CN 115224013 A CN115224013 A CN 115224013A CN 202211025463 A CN202211025463 A CN 202211025463A CN 115224013 A CN115224013 A CN 115224013A
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China
Prior art keywords
chip
molding layer
forming
layer
conductive
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CN202211025463.4A
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English (en)
Inventor
陈威宇
黄立贤
苏安治
陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN115224013A publication Critical patent/CN115224013A/zh
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    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

提供芯片封装结构。芯片封装结构包含再布线基板。芯片封装结构包含第一芯片结构，其位于再布线基板上。芯片封装结构包含第一焊料凸块，其配置于再布线基板与第一芯片结构之间，并电性连接再布线基板与第一芯片结构。芯片封装结构包含第一成型层，其围绕第一芯片结构。第一成型层与第一芯片结构以及再布线基板之间隔有第一焊料凸块，以定义间隙于第一成型层与第一芯片结构以及再布线基板之间。芯片封装结构包含第二芯片结构，其位于第一芯片结构上。芯片封装结构包含第二成型层，其围绕第二芯片结构。芯片封装结构包含第三成型层，其围绕第一成型层、第二成型层、与第一焊料凸块，并填入间隙中。

Description

芯片封装结构
本申请为分案申请，其母案申请的申请号为201710205828.4，申请日为2017年3月31日，发明名称为“芯片封装结构”。
技术领域
本公开实施例涉及半导体结构，更特别涉及芯片封装结构与其形成方法。
背景技术
半导体集成电路产业经历快速成长。集成电路材料与设计的技术进步，使每一代的电路比前一代的电路更小更复杂。然而这些进展会增加集成电路工艺的复杂度。
在集成电路的进展中，随着几何尺寸(工艺所能产生的最小构件或线路)缩小，功能密度(单位芯片面积中的内连线装置数目)增加。上述尺寸缩小的工艺的优点为增加产能及降低相关成本。
然而随着结构尺寸一直缩小，将更难以进行工艺，且工艺(如热工艺)也更易影响集成电路的效能。综上所述，目前挑战为形成越来越小的半导体装置时兼顾其可信度。
发明内容
本公开实施例提供的芯片封装结构，包括：再布线基板；第一芯片结构，位于再布线基板上；第一焊料凸块，配置于再布线基板与第一芯片结构之间，并电性连接再布线基板与第一芯片结构；第一成型层，围绕第一芯片结构，其中第一成型层与第一芯片结构以及再布线基板之间隔有第一焊料凸块，以定义间隙于第一成型层与第一芯片结构以及再布线基板之间；第二芯片结构，位于第一芯片结构上；第二成型层，围绕第二芯片结构；以及第三成型层，围绕第一成型层、第二成型层、与第一焊料凸块，并填入间隙中。
附图说明
图1A至图1J是一些实施例中，芯片封装结构于其形成工艺的多种阶段中的剖视图。
图1G-1是一些实施例中，图1G的焊料凸块与导电柱的放大剖视图。
图2是一些实施例中，芯片封装结构的剖视图。
图3是一些实施例中，芯片封装结构的剖视图。
图4A至图4C是一些实施例中，芯片封装结构于其形成工艺的多种阶段中的剖视图。
图5是一些实施例中，芯片封装结构的剖视图。
图6是一些实施例中，芯片封装结构的剖视图。
附图标记说明：
D距离
G间隙
I内连线结构
T、T1、T2厚度
W、W3、W4、W5、W6、W7、W8、W9、W10宽度
W1、W2最大宽度
110、220承载基板
120粘着层
130、130b、170芯片结构
130a、130c、131、134a、136a、138a、139a、142、146、162、170a、178a、179a、182、232a、244上表面
130d、144、154、184、194、239、242、418、518侧壁
132、172芯片
134、174、232、412、512介电层
136、176接合垫
138、178内连线结构
139、179钝化层
140、180、240成型层
150绝缘层
152孔洞
160导电通孔结构
190导电柱
192、412a、512a下表面
200、300、400、500、600、700、800芯片封装结构
210焊料凸块
230再布线基板
234、414、514线路层
236a、236b导电垫
238、416、516导电通孔
250导电凸块
410、510再布线层
具体实施方式
下述内容提供的不同实施例或实例可实施本公开的不同结构。特定构件与排列的实施例是用以简化本公开而非局限本公开。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本公开的多种例子中可重复标号及/或符号，但这些重复仅用以简化与清楚说明，不代表不同实施例及/或设置之间具有相同标号及/或符号的单元之间具有相同的对应关系。
此外，空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。应理解的是，在下述方法之前、之中、与之后可进行额外步骤，且其他实施例的方法的一些步骤可省略或取代为其他步骤。
图1A至图1J是一些实施例中，芯片封装结构于其形成工艺的多种阶段中的剖视图。
如图1A所示的一些实施例，提供承载基板110。在一些实施例中，承载基板110设置以在后续工艺步骤中，提供暂时的机械与结构支撑。在一些实施例中，承载基板110包含玻璃、氧化硅、氧化铝、上述的组合、及/或类似物。在一些实施例中，承载基板110包含芯片。
如图1A所示的一些实施例，粘着层120形成于承载基板110上。在一些实施例中，粘着层120包含任何合适的粘着材料如高分子材料。举例来说，一些实施例的粘着层120包含紫外线胶，照射紫外线时将失去其粘着性。在一些实施例中，粘着层120包含双面粘着带。粘着层120的形成方法可为压合工艺、旋转涂布工艺、或另一合适工艺。
如图1A所示的一些实施例，提供芯片结构130至粘着层120上。在一些实施例中，每一芯片结构130包含芯片132、介电层134、接合垫136、内连线结构138、与钝化层139。在一些实施例中，介电层134形成于芯片132上。
在一些实施例中，介电层134包含氧化硅、氮氧化硅、硼硅酸盐玻璃、磷硅酸盐玻璃、硼磷硅酸盐玻璃、氟化硅酸盐玻璃、低介电常数材料、孔洞状的介电材料、或上述的组合。在一些实施例中，介电层134的形成方法可为化学气相沉积工艺、高密度等离子体化学气相沉积工艺、旋转涂布工艺、溅镀工艺、或上述的组合。
在一些实施例中，接合垫136埋置于介电层134中。在一些实施例中，接合垫电性连接至芯片132之中/之上的装置(未图示)。在一些实施例中，内连线结构138形成于个别的接合垫136上。
在一些实施例中，内连线结构138包含导电柱或导电凸块。在一些实施例中，钝化层139形成于介电层134上，并围绕内连线结构138。钝化层139可包含高分子材料或另一合适的绝缘材料。
如图1B所示的一些实施例，成型层140形成于承载基板110与粘着层120上。在一些实施例中，成型层140围绕芯片结构130。在一些实施例中，部分的成型层140位于芯片结构130之间。成型层140可包含高分子材料或另一合适的绝缘材料。
在一些实施例中，成型层140的形成方法包含形成成型化合物材料于粘着层120上、进行硬化工艺以交联(或热固化)成型化合物材料层的高分子、以及在成型化合物材料层上进行研磨工艺，直到露出内连线结构138。如此一来，一些实施例的内连线结构138的上表面138a、钝化层139的上表面139a、芯片结构130的上表面130a、与成型层140的上表面142将共平面(或彼此齐平)。
如图1B所示的一些实施例中，绝缘层150形成于成型层140与芯片结构130上。在一些实施例中，绝缘层150为连续的层状物。在一些实施例中，绝缘层150具有孔洞152于内连线结构138上。在一些实施例中，孔洞152分别露出下方的内连线结构138。
如图1C所示的一些实施例，导电通孔结构160形成于孔洞152之中与之上，以分别电性连接至内连线结构138。导电通孔结构160可包含铜或另一合适的导电材料。
如图1C所示的一些实施例，提供芯片结构170于绝缘层150上。在一些实施例中，芯片结构170位于芯片结构130及成型层140上。
在一些实施例中，芯片结构170露出每一芯片结构130的一部分。在一些实施例中，芯片结构170位于导电通孔结构160之间。在一些实施例中，导电通孔结构160围绕芯片结构170。
在一些实施例中，每一芯片结构170包含芯片172、介电层174、接合垫176、内连线结构178、与钝化层179。在一些实施例中，介电层174形成于芯片172上。
在一些实施例中，介电层174包含氧化硅、氮氧化硅、硼硅酸盐玻璃、磷硅酸盐玻璃、硼磷硅酸盐玻璃、氟化硅酸盐玻璃、低介电常数材料、孔洞状的介电材料、或上述的组合。在一些实施例中，介电层174的形成方法可为化学气相沉积工艺、高密度等离子体化学气相沉积工艺、旋转涂布工艺、溅镀工艺、或上述的组合。
在一些实施例中，接合垫176埋置于介电层174中。在一些实施例中，接合垫176电性连接至形成于芯片172之中/之上的装置(未图示)。在一些实施例中，内连线结构178分别形成于接合垫176上。
在一些实施例中，内连线结构178包含导电柱或导电凸块。在一些实施例中，钝化层179形成于介电层174上，并围绕内连线结构178。钝化层179包含高分子材料或另一合适的绝缘材料。
如图1C所示的一些实施例，成型层180形成于绝缘层150上。在一些实施例中，绝缘层150与成型层140及芯片结构130之间，隔有成型层180与芯片结构170。在一些实施例中，成型层180位于芯片结构130及成型层140上。
在一些实施例中，成型层180围绕芯片结构170与导电通孔结构160。在一些实施例中，部分的成型层180位于芯片结构170与导电通孔结构160之间。成型层180可包含高分子材料或另一合适的绝缘材料。
在一些实施例中，成型层180的形成方法包含形成成型化合物材料于绝缘层150上、进行硬化工艺以交联(或热固化)成型化合物材料层的高分子、以及在成型化合物材料层上进行研磨工艺，直到露出内连线结构160与内连线结构178。
如此一来，一些实施例的内连线结构178的上表面178a、钝化层179的上表面179a、芯片结构170的上表面170a、导电通孔结构160的上表面162、与成型层180的上表面182将共平面(或彼此齐平)。在一些实施例中，导电通孔结构160穿过成型层180。
如图1D所示的一些实施例，导电柱190分别形成于导电通孔结构160与内连线结构178上。在一些实施例中，导电柱190直接接触下方的导电通孔结构160与下方的内连线结构178。
导电柱190可包含铜或另一合适的导电材料。在一些实施例中，导电柱190不含锡。在一些实施例中，导电柱190的形成方法为电镀工艺。
如图1D所示的一些实施例，焊料凸块210形成于导电柱190上。在一些实施例中，焊料凸块210直接接触导电柱190。在一些实施例中，一些导电柱190位于芯片结构170与焊料凸块210之间。
在一些实施例中，一些导电柱190位于导电通孔结构160与焊料凸块210之间。焊料凸块210可包含锡、银、金、铅、或另一合适的焊料材料。在一些实施例中，焊料凸块210与导电柱190由不同材料组成。在一些实施例中，焊料凸块210的形成方法可为电镀工艺。
如图1E所示的一些实施例，自承载基板110剥离芯片结构130与成型层140。在一些实施例中，剥离工艺包含在粘着层120上进行热工艺。举例来说，以紫外线照射粘着层120，以弱化粘着层120的粘着性。
如图1E所示的一些实施例，在成型层180、绝缘层150、与成型层140上进行切割工艺，以形成个别的芯片封装结构200。在一些实施例中，每一芯片封装结构200包含芯片结构130、成型层140、绝缘层150、导电通孔结构160、芯片结构170、成型层180、导电柱190、与焊料凸块210。
在一些实施例中，芯片封装结构200为多芯片堆叠的封装结构。一些实施例的每一芯片封装结构200中，成型层180的侧壁184、绝缘层150的侧壁154、与成型层140的侧壁144共平面。
如图1F所示的一些实施例，提供承载基板220。承载基板220设置以在后续工艺步骤中，提供暂时的机械与结构支撑。在一些实施例中，承载基板220包含玻璃、氧化硅、氧化铝、上述的组合、及/或类似物。
如图1F所示的一些实施例，再布线基板230分开地形成于载体基板220上(而非整体地形成于芯片封装结构200上)。在一些实施例中，再布线基板230包含介电层232、线路层234、导电垫236a与236b、以及导电通孔238。在一些实施例中，介电层232具有上表面232a。
在一些实施例中，线路层234与导电通孔238位于介电层232中。在一些实施例中，导电垫236a位于介电层232上。在一些实施例中，导电垫236b位于介电层232下。
在一些实施例中，导电通孔238位于导电垫236a与236b以及线路层234之间。如此一来，一些实施例的导电垫236a与236b与线路层234可依设计需求，经由导电通孔238彼此电性连接。在一些实施例中，每一导电通孔238的宽度W朝介电层232的上表面232a的方向持续增加。
如图1G所示的一些实施例，芯片封装结构200翻转朝上后，置于再布线基板230上。在一些实施例中，焊料凸块210位于个别的导电垫236a上。在一些实施例中，之后可在焊料凸块210上进行再流动工艺。
在一些实施例中，导电柱190的组成为第一导电材料，而焊料凸块210的组成为第二导电材料。在一些实施例中，第一导电材料的第一熔点高于第二导电材料的第二熔点。
在一些实施例中，再流动工艺的温度介于第一熔点与第二熔点之间。如此一来，一些实施例的再流动工艺中的焊料凸块210将熔融，并接合至导电垫236a与导电柱190。
图1G-1是一些实施例中，图1G的焊料凸块210与导电柱190的放大剖视图。如图1G与图1G-1所示，在再流动工艺之后，焊料凸块210覆盖焊料凸块210上的导电柱190的下表面192。在一些实施例中(未图示)，焊料凸块210亦覆盖焊料凸块210上的导电柱190的部分侧壁194。
在一些实施例中，导电柱190的厚度T2大于焊料凸块210的厚度T1。在一些实施例中，焊料凸块210的最大宽度W1大于其上的导电柱190的最大宽度W2。
在一些实施例中，导电柱190与其下的焊料凸块210一起形成内连线结构I。在一些实施例中，内连线结构I的厚度T，实质上等于芯片结构170(或成型层180)与再布线基板230之间的距离D。在一些实施例中，厚度T或距离D介于约20微米至约30微米之间。
在一些实施例中，成型层180与芯片结构170与再布线基板230之间隔有间隙G。在一些实施例中，导电柱190与焊料凸块210位于间隙G中。
由于导电柱190不会在再流动工艺中熔融，因此导电柱190可维持内连线结构I的厚度T，且导电柱190可维持距离D至适当数值。如此一来，后续工艺中的成型化合物材料可轻易填入间隙G。
此外，导电柱190可在维持相同距离D时，减少其下方的焊料凸块210的体积，可避免相邻的焊料凸块210因再流动工艺而短路。
如图1H所示的一些实施例，成型层240形成于再布线基板230上。在一些实施例中，成型层240围绕芯片封装结构200。
在一些实施例中，成型层240围绕芯片结构130、成型层140、绝缘层150、导电通孔结构160、芯片结构170、成型层180、导电柱190、与焊料凸块210。
在一些实施例中，成型层240填入间隙G。在一些实施例中，成型层240直接接触焊料凸块210、导电柱190、再布线基板230、成型层140与180、以及绝缘层150。成型层240可包含高分子材料或另一合适的绝缘材料。
在一些实施例中，成型层240的形成方法包含形成成型化合物材料于再布线基板230与芯片封装结构200上、进行硬化工艺以交联(或热固化)成型化合物材料层的高分子、以及在成型化合物材料层上进行研磨工艺，直到露出芯片结构130的上表面131。
如图1I所示的一些实施例，移除承载基板220。如图1I所示的一些实施例中，导电凸块250分别形成于导电垫236b上。导电凸块250可包含锡或另一合适的导电材料。在一些实施例中，导电凸块250的形成方法可包含形成焊料膏于导电垫236b上，并再流动焊料膏。
如图1J所示的一些实施例中，在成型层240与再布线基板230上进行切割工艺，以形成个别的芯片封装结构300。在一些实施例中，每一芯片封装结构300包含芯片封装结构200、成型层240、再布线基板230、与导电凸块250。在一些实施例的芯片封装结构300中，成型层240的侧壁242与再布线基板230的侧壁239共平面。
在一些实施例中，在芯片封装结构300中，成型层240的上表面244、芯片结构130的上表面131、与成型层140的上表面146共平面。在一些实施例中，导电柱160穿过成型层180。在一些实施例中，成型层240连续地围绕整个芯片封装结构200。
在一些实施例中，成型层240为单层结构。在一些实施例中，成型层240未覆盖芯片结构130的上表面131。在一些实施例中，芯片封装结构300为扇出式芯片封装结构。
在一些实施例中，再布线基板230的宽度W3大于芯片封装结构200的宽度W4。在一些实施例中，宽度W4大于芯片结构130的宽度W5或芯片结构170的宽度W6。
在一些实施例中，图1A至图1J的工艺包含形成芯片封装结构200、将芯片封装结构200接合至再布线基板230、形成成型层240于再布线基板230上以及芯片封装结构200之间、以及进行切割工艺以形成个别的芯片封装结构300。
在一些实施例中，由于芯片封装结构200与再布线基板230分开形成，可避免形成再布线基板230的介电层232的热工艺影响芯片封装结构200的芯片132与172。如此一来，一些实施例可维持芯片132与172的效能。
此外，由于分开形成芯片封装结构200与再布线基板230，因此可同时形成芯片封装结构200与再布线基板230。如此一来，一些实施例可缩短芯片封装结构300的周期(工艺时间)。
在一些实施例中，可对图1D的导电柱190与焊料凸块210进行电性检测(如最终检测)，以确认良品晶粒。在一些实施例中，可对图1F的再布线基板230进行电性检测(如最终检测)，以确认良品再布线层。
在一些实施例中，之后在图1G所示的步骤中，捡选具有良品晶粒的芯片封装结构200并将其置于具有良品再布线层的再布线基板230上，以形成具有良品晶粒与良品再布性层的芯片封装结构300。如此一来，一些实施例可改善芯片封装结构300的良率。
图2是一些实施例中，芯片封装结构400的剖视图。如图2所示的一些实施例，芯片封装结构400与图1J的芯片封装结构300类似，差别在于芯片封装结构400进一步包含再布线层410。
在一些实施例中，再布线层410位于成型层140与180之间、位于芯片结构130与成型层180之间、位于芯片结构130与170之间、位于成型层140与芯片结构170之间、以及位于芯片结构130与导电通孔结构160之间。
在一些实施例中，再布线层410包含介电层412、线路层414、与导电通孔416。在一些实施例中，线路层414与导电通孔416位于介电层412中。在一些实施例中，导电通孔416位于线路层414与内连线结构138之间。
如此一来，一些实施例的内连线结构138与线路层414可依设计需求，经由导电通孔416彼此电性连接。在一些实施例中，每一导电通孔416的宽度W8朝介电层412的下表面412a的方向持续增加。
在一些实施例中，再布线层410直接接触芯片结构130、成型层140与240、导电通孔结构160、与绝缘层150。在一些实施例中，成型层180的侧壁184、成型层140的侧壁144、与再布线层410的侧壁418共平面。在一些实施例中，再布线层410的宽度W7与芯片封装结构200的宽度W4实质上相同。
图3是一些实施例中，芯片封装结构500的剖视图。如图3所示的一些实施例，芯片封装结构500与图2的芯片封装结构400类似，差别在于芯片封装结构500进一步包含再布线层510。
在一些实施例中，再布线层510位于成型层240与180之间、位于芯片结构170与成型层240之间、位于芯片结构170与导电柱190之间、以及位于导电通孔结构160与导电柱190之间。
在一些实施例中，再布线层510包含介电层512、线路层514、与导电通孔516。在一些实施例中，线路层514与导电柱516位于介电层512中。在一些实施例中，导电通孔516位于线路层514与内连线结构178之间。
如此一来，一些实施例的内连线结构178与线路层514可依设计需求，经由导电通孔516彼此电性连接。在一些实施例中，每一导电通孔516的宽度W10朝介电层512的下表面512a的方向持续增加。
在一些实施例中，再布线层510直接接触芯片结构170、成型层180与240、导电通孔结构160、与导电柱190。在一些实施例中，成型层180的侧壁184、成型层的侧壁144、再布线层410的侧壁418、与再布线层510的侧壁518共平面。在一些实施例中，再布线层410的宽度W7、芯片封装结构200的宽度W4、与再布线层510的宽度W9实质上彼此相同。
图4A至图4C是一些实施例中，形成芯片封装结构的工艺的多种阶段其剖视图。如图4A所示的一些实施例，提供承载基板110与粘着层120。在一些实施例中，图4A的承载基板110与粘着层120的材料、结构、与位置与图1A的承载基板110与粘着层120的材料、结构、与位置类似。
如图4A所示的一些实施例，提供芯片结构130b于粘着层120上。在一些实施例中，图4A的芯片结构130b与图1A的芯片结构130类似，差别在于芯片结构130b不包含内连线结构138与钝化层139。
如图4B所示的一些实施例，成型层140形成于承载基板110与粘着层120上。在一些实施例中，成型层140围绕芯片结构130b。在一些实施例中，部分的成型层140位于芯片结构130b之间。成型层140可包含高分子材料或另一合适的绝缘材料。
在一些实施例中，成型层140的形成方法包含转移成型工艺。转移成型工艺可包含：提供模具于粘着层120上，其中模具的顶板部分直接接触接合垫136的上表面136a与介电层134的上表面134a，且模具的侧壁部分与芯片结构130b的侧壁部分130d之间具有空间；将成型化合物材料注入空间中；进行硬化工艺以交联(热固化)成型化合物材料的高分子；以及移除模具。
在一些实施例中，由于模具的顶板部分直接接触上表面136a与134a，成型层140将露出接合垫136与介电层134。如此一来，不需在成型化合物材料层上进行研磨工艺以露出接合垫136。
如此一来，一些实施例不需避免研磨工艺损伤接合垫136，而形成内连线结构与钝化层于接合垫136上。因此在一些实施例中，可减少芯片结构130b的成本。在一些实施例中，接合垫136的上表面136a、介电层134的上表面134a、芯片结构130b的上表面130c、与成型层140的上表面142共平面(或彼此对准)。
如图4B所示的一些实施例，绝缘层150形成于成型层140与芯片结构130b上。在一些实施例中，绝缘层150为连续的层状物。在一些实施例中，绝缘层150具有孔洞152分别位于接合垫136上。在一些实施例中，孔洞152各自露出下方的接合垫136。
在一些实施例中，进行图1C至图1J中的步骤后，实质上形成图4C所示的芯片封装结构600。在一些实施例中，芯片封装结构600与图1J的芯片封装结构300类似，差别在芯片封装结构600的芯片结构130b，不包含图1J的芯片封装结构300的内连线结构138与钝化层139。如此一来，一些实施例可降低芯片封装结构600的成本。
图5是一些实施例中，芯片封装结构700的剖视图。如图5所示的一些实施例，芯片封装结构700与图4C的芯片封装结构600类似，差别在于芯片封装结构700还包括再布线层410。
在一些实施例中，图5的再布线层410与图2的再布线层410类似。在一些实施例中，再布线层410位于成型层140与180之间、位于芯片结构130b与成型层180之间、位于芯片结构130b与170之间、位于成型层140与芯片结构170之间、以及位于芯片结构130b与导电通孔结构160之间。
在一些实施例中，再布线层410包含介电层412、线路层414、与导电通孔416。在一些实施例中，线路层414与导电通孔416位于介电层412中。在一些实施例中，导电通孔416位于线路层414与接合垫136之间。
如此一来，一些实施例的导电垫136与线路层414可依设计需求，经由导电通孔416彼此电性连接。在一些实施例中，再布线层410直接接触芯片结构130b、成型层140与240、导电通孔结构160、与绝缘层150。
图6是一些实施例中，芯片封装结构800的剖视图。如图6所示的一些实施例，芯片封装结构800与图5的芯片封装结构700类似，差别在于芯片封装结构800还包括再布线层510。
在一些实施例中，图6的再布线层510与图3的再布线层510类似。在一些实施例中，再布线层510位于成型层240与180之间、位于芯片结构170与成型层240之间、位于芯片结构170与导电柱190之间、以及位于导电通孔结构160与导电柱190之间。
在一些实施例中，再布线层510包含介电层512、线路层514、与导电通孔516。在一些实施例中，线路层514与导电通孔516位于介电层512中。在一些实施例中，导电通孔516位于线路层514与内连线结构178之间。
如此一来，一些实施例的内连线结构178与线路层514可依设计需求，经由导电通孔516彼此电性连接。在一些实施例中，再布线层510直接接触芯片结构170、成型层180与240、导电通孔结构160、与导电柱190。
本公开一些实施例提供芯片封装结构与其形成方法。用以形成芯片封装结构的方法包括分别形成多芯片堆叠的封装结构与再布线基板；将多芯片堆叠的封装结构接合至再布线基板上；以及形成成型层于再布线基板上并围绕多芯片封装结构。如此一来，可避免形成再布线基板的介电层的方法的热工艺，影响多芯片堆叠的封装结构。如此一来，可维持芯片效能，并改善具有这些芯片的芯片封装结构良率。
在一些实施例中，提供芯片封装结构，其包含再布线基板。芯片封装结构包含第一芯片结构，其位于再布线基板上。芯片封装结构包含第一焊料凸块，其配置于再布线基板与第一芯片结构之间，并电性连接再布线基板与第一芯片结构。芯片封装结构包含第一成型层，其围绕第一芯片结构，其中第一成型层与第一芯片结构以及再布线基板之间隔有第一焊料凸块，以定义间隙于第一成型层与第一芯片结构以及再布线基板之间。芯片封装结构包含第二芯片结构，其位于第一芯片结构上。芯片封装结构包含第二成型层，其围绕第二芯片结构。芯片封装结构包含第三成型层，其围绕第一成型层、第二成型层、与第一焊料凸块，并填入间隙中。
在一些实施例中，上述芯片封装结构还包括：导电凸块，位于间隙中以及第一芯片结构与第一焊料凸块之间。
在一些实施例中，上述芯片封装结构的导电柱直接接触第一芯片结构与第一焊料凸块。
在一些实施例中，上述芯片封装结构的第一焊料凸块的组成为第一导电材料，导电柱的组成为第二导电材料，且第二导电材料的熔点高于第一导电材料的熔点。
在一些实施例中，上述芯片封装结构的第一焊料凸块的最大宽度大于导电柱的最大宽度。
在一些实施例中，上述芯片封装结构的第三成型层直接接触第一焊料凸块、导电柱、再布线基板、第一成型层、与第二成型层。
在一些实施例中，上述芯片封装结构还包括：导电通孔结构，其穿过第一成型层并电性连接至第二芯片结构；第二焊料凸块，其位于间隙中并连接至再布线基板；以及导电柱，其位于导电通孔结构与第二焊料凸块之间。
在一些实施例中，上述芯片封装结构还包括：再布线层，其位于第一成型层与间隙中的第三成型层之间，并位于第一芯片结构与第一焊料凸块之间，其中导电通孔结构连接至再布线层。
在一些实施例中，上述芯片封装结构的第三成型层的侧壁与再布线基板的侧壁共平面，第三成型层的上表面、第二芯片结构的上表面、与第二成型层的上表面共平面，且第一芯片结构的下表面与第一成型层的下表面共平面。
一些实施例提供芯片封装结构，其包含再布线基板。芯片封装结构包含第一芯片结构，其位于再布线基板上。芯片封装结构包含第一焊料凸块，其配置于再布线基板与第一芯片结构之间，且电性连接再布线基板与第一芯片结构。芯片封装结构包含第一成型层，其围绕第一芯片结构。第一成型层及第一芯片结构均与再布线基板隔有第一焊料凸块，以定义间隙于第一成型层及第一芯片结构与再布线基板之间。芯片封装结构包含第一导电柱，其位于间隙中并位于第一芯片结构下。第一焊料凸块配置于第一导电柱与再布线基板之间。第一焊料凸块与第一导电柱一起形成内连线结构，且内连线结构的厚度实质上等于第一芯片结构与再布线基板之间的距离。芯片封装结构包含第二芯片结构，其位于第一芯片结构与第一成型层中至少一者上。芯片封装结构包含第二成型层，其围绕第二芯片结构。芯片封装结构包含第三成型层，其围绕第一成型层、第二成型层、第一焊料凸块、与第一导电柱，并填入间隙中。
在一些实施例中，上述芯片封装结构的第一导电柱的厚度大于第一焊料凸块的厚度。
在一些实施例中，上述芯片封装结构还包括：导电通孔结构穿过第一成型层并电性连接至第二芯片结构；第二焊料凸块位于间隙中；以及第二导电柱位于导电通孔结构与第二焊料凸块之间。
在一些实施例中，上述芯片封装结构还包括：再布线层位于第二成型层第一成型层之间、位于第二芯片结构第一成型层之间、与位于第二芯片结构与第一芯片结构之间，其中导电通孔结构连接至再布线层。
在一些实施例中，上述芯片封装结构的再布线层的侧壁、第一成型层的侧壁、与第二成型层的侧壁共平面。
在一些实施例中，上述芯片封装结构的第二芯片结构包含芯片、介电层、与导电垫，介电层位于芯片上，导电垫埋置于介电层中，且第二成型层的下表面、介电层的下表面、与导电垫的下表面共平面。
在一些实施例中，提供芯片封装结构的形成方法，其包括：提供第一芯片结构于第一承载基板上。上述方法包括形成第一成型层以围绕第一芯片结构。上述方法包括将第二芯片结构置于第一芯片结构上。上述方法包括形成第二成型层以围绕第二芯片结构。上述方法包括形成第一焊料凸块于第二芯片结构上。上述方法包括移除第一承载基板。上述方法包括提供再布线基板于第二承载基板上。上述方法包括经由第一焊料凸块将第二芯片结构接合至再布线基板。第二成型层与第二芯片结构均与再布线基板之间隔有第一焊料凸块，以定义间隙于第二成型层与第二芯片结构及再布线基板之间。上述方法包括形成第三成型层于再布线基板上，以围绕第一成型层、第二成型层、与第一焊料凸块，并填入间隙。上述方法包括移除第二承载基板。
在一些实施例中，上述形成芯片封装结构的方法还包括：在形成第二成型层之后与形成第一焊料凸块之前，形成导电柱于第二芯片结构上，其中第一焊料凸块形成于导电柱上。
在一些实施例中，上述形成芯片封装结构的方法，其中导电柱的组成为第一导电材料，第一焊料凸块的组成为第二导电材料，且第一导电材料的熔点高于第二导电材料的熔点，且经由第一焊料凸块将第二芯片接合至再布线基板的步骤包括：将第一焊料凸块置于再布线基板上；以及在第一焊料凸块上进行再流动工艺，且再流动工艺的温度介于第一导电材料的熔点与第二导电材料的熔点之间。
在一些实施例中，上述形成芯片封装结构的方法还包括：在形成第一成型层之后与放置第二芯片结构之前，形成导电通孔结构于第一芯片结构上，其中第二成型层亦围绕导电通孔结构。
在一些实施例中，上述形成芯片封装结构的方法还包括：在形成第一焊料凸块的步骤中，形成第二焊料凸块于导电通孔结构上。
上述实施例的特征有利于本领域技术人员理解本公开。本领域技术人员应理解可采用本公开作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本领域技术人员亦应理解，这些等效置换并未脱离本公开精神与范畴，并可在未脱离本公开的精神与范畴的前提下进行改变、替换、或更动。

Claims (20)

1.一种芯片封装结构的形成方法，包括：
沿着一第一芯片结构和一第二芯片结构的侧壁形成一第一成型层；
在该第一成型层、该第一芯片结构和该第二芯片结构上形成一或多个绝缘层；
将一第三芯片结构接合至所述一或多个绝缘层；
在所述一或多个绝缘层上形成一第一导电通孔结构；
在所述一或多个绝缘层上形成一第二成型层，该第二成型层沿着该第三芯片结构和该第一导电通孔结构的侧壁延伸；以及
沿着该第一成型层、所述一或多个绝缘层和该第二成型层的侧壁形成一第三成型层。
2.如权利要求1所述的芯片封装结构的形成方法，其中该第三芯片结构的多个第一接触垫背离该第一芯片结构。
3.如权利要求2所述的芯片封装结构的形成方法，还包括将该第三芯片结构的所述多个第一接触垫直接接合至一基板。
4.如权利要求3所述的芯片封装结构的形成方法，其中在形成该第三成型层之前，进行接合该第三芯片结构的所述多个第一接触垫。
5.如权利要求4所述的芯片封装结构的形成方法，其中形成该第一导电通孔结构包括形成该第一导电通孔结构穿过所述一或多个绝缘层至该第一芯片结构的一第二接触垫。
6.如权利要求4所述的芯片封装结构的形成方法，其中该第三成型层在该第三芯片结构和该基板之间延伸。
7.一种芯片封装结构的形成方法，包括：
形成邻近一第一芯片结构的一第一成型层；
在该第一成型层上形成一或多个第一绝缘层；
在该第一芯片结构和所述一或多个第一绝缘层上设置一第二芯片结构；
形成邻近该第二芯片结构的一第二成型层；
将该第二芯片结构接合至一基板；以及
在该基板上形成一第三成型层并围绕该第一成型层和该第二成型层。
8.如权利要求7所述的芯片封装结构的形成方法，还包括在所述一或多个第一绝缘层中形成多个导电再布线，其中该第一芯片结构的多个接触垫电耦合到该导电再布线中的对应的一些。
9.如权利要求8所述的芯片封装结构的形成方法，还包括在形成该第三成型层之前，在该第二芯片结构和该第二成型层上形成一再布线结构。
10.如权利要求9所述的芯片封装结构的形成方法，其中形成该第三成型层包括沿着该再布线结构的侧壁形成该第三成型层。
11.如权利要求7所述的芯片封装结构的形成方法，其中在形成该第三成型层之后，该第一成型层的横向边缘与该第二成型层的横向边缘对齐。
12.如权利要求7所述的芯片封装结构的形成方法，其中形成该第三成型层包括在该第二芯片结构和该基板之间形成该第三成型层。
13.如权利要求7所述的芯片封装结构的形成方法，还包括形成多个导电通孔结构电连接到该第一芯片结构的一接触垫，其中形成该第二成型层包括沿着所述多个导电通孔结构的侧壁形成该第二成型层。
14.如权利要求13所述的芯片封装结构的形成方法，其中所述多个导电通孔结构延伸穿过所述一或多个第一绝缘层。
15.一种芯片封装结构的形成方法，包括：
沿着一或多个第一芯片结构的侧壁形成一第一成型层；
在该第一成型层和所述一或多个第一芯片结构上形成一第一互连结构；
将一第二芯片结构接合至该第一互连结构；
在该第一互连结构上形成一导电通孔结构；
沿着该导电通孔结构和该第二芯片结构的侧壁形成一第二成型层；以及
沿着该第一成型层和该第二成型层的侧壁形成一第三成型层。
16.如权利要求15所述的芯片封装结构的形成方法，其中所述一或多个第一芯片结构的主表面不含该第一成型层和该第二成型层。
17.如权利要求15所述的芯片封装结构的形成方法，还包括在形成该第三成型层之前，在该第二芯片结构、该导电通孔结构和该第二成型层上形成一第二互连结构。
18.如权利要求17所述的芯片封装结构的形成方法，其中该第一互连结构包括一第一通孔，其中该第一通孔的宽度随着该第一通孔延伸远离所述一或多个第一芯片结构而减小。
19.如权利要求18所述的芯片封装结构的形成方法，其中该第二互连结构包括一第二通孔，其中该第二通孔的宽度随着该第二通孔延伸远离该第二芯片结构而减小。
20.如权利要求15所述的芯片封装结构的形成方法，其中该第三成型层接触该第二成型层的侧壁和底部。
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