CN107845611A - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
CN107845611A
CN107845611A CN201710300971.1A CN201710300971A CN107845611A CN 107845611 A CN107845611 A CN 107845611A CN 201710300971 A CN201710300971 A CN 201710300971A CN 107845611 A CN107845611 A CN 107845611A
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China
Prior art keywords
crystal grain
layer
dummy
encapsulating structure
height
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Granted
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CN201710300971.1A
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CN107845611B (zh
Inventor
陈宪伟
黄立贤
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN107845611A publication Critical patent/CN107845611A/zh
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Abstract

本发明实施例提供一种封装结构，其包括基板及形成于基板上的装置晶粒。装置晶粒有第一高度。封装结构包括虚置晶粒，形成于基板上且邻近装置晶粒，其中虚置晶粒有第二高度。第二高度低于第一高度。封装结构也包括封装层，形成于装置晶粒及虚置晶粒间。

Description

封装结构
技术领域
本发明实施例涉及封装结构，且特别有关于一种具有虚置晶粒的封装结构。
背景技术
半导体装置被用于各种电子应用中，如个人电脑、移动电话、数字相机及其他电子设备。半导体装置的制造通常是在半导体基板上依顺序沉积绝缘或介电层、导电层及半导体层，并以光刻图案化各种材料层以在其上形成电路组件和元件。许多集成电路通常于单一半导体晶圆上制造，且晶圆上的独立晶粒通过沿着切割道在集成电路之间以锯切来单粒化。独立晶粒通常各别地封装，例如在多晶片模块中或于其他封装类型中封装。
业界已经开始发展新的封装技术，如堆叠式封装层叠(package on package，简称PoP)，其中装置晶粒的顶部封装与有着另一装置晶粒的底部封装接合。通过采用新的封装技术，可将各种具有相同或不同功能的封装体整合在一起。
虽然现有的封装结构及其制造方法通常足以满足其预期目的，但并非完全令人满意。
发明内容
于一些实施例中，提供一种封装结构，包括基板及形成于基板上的装置晶粒。装置晶粒有第一高度。封装结构包括虚置晶粒，形成于基板上且邻近装置晶粒，其中虚置晶粒有第二高度。第二高度低于第一高度。封装结构也包括封装层，形成于装置晶粒及虚置晶粒间。
于一些实施例中，提供一种封装结构，包括基板及形成于基板上的第一装置晶粒。封装结构包括第一虚置晶粒，形成于基板上且邻近第一装置晶粒。封装结构也包括第一封装层，围绕第一装置晶粒及第一虚置晶粒，其中第一封装层覆盖第一虚置晶粒的上表面。封装结构也包括重分布结构，形成于第一封装层上，其中重分布结构电性连接至第一装置晶粒。
于一些实施例中，提供一种封装结构，包括第一封装结构和第二封装结构。第一封装结构包括：第一装置晶粒，形成于基板上，第一虚置晶粒形成于基板上，第一封装层围绕第一装置晶粒及第一虚置晶粒，其中第一封装层覆盖于第一虚置晶粒，以及形成于该第一封装层上的重分布结构，其中重分布结构电性连接至第一装置晶粒。第二封装结构包括形成于重分布结构上的第二虚置晶粒，以及第二封装层，围绕第二虚置晶粒，其中第二封装层覆盖第二虚置晶粒。
附图说明
以下将配合说明书附图详述本发明的实施例。应注意的是，依据在业界的标准做法，各种特征并未按照比例绘示且仅用以说明例示。事实上，可能任意地放大或缩小元件的尺寸，以清楚地表现出本发明的特征。
图1A-图1D是根据本发明一些实施例绘示的形成封装结构各种阶段的剖面图。
图2A是根据本发明一些实施例绘示的第一装置晶粒及第一虚置晶粒的俯视图。
图2B是根据本发明一些实施例绘示的封装层覆盖于第一虚置晶粒的俯视图。
图3A-图3G是根据本发明一些实施例绘示的形成封装结构各种阶段的剖面图。
图4A-图4G是根据本发明一些实施例绘示的形成封装结构各种阶段的剖面图。
图5A-图5G是根据本发明一些实施例绘示的形成封装结构各种阶段的剖面图。
图6A-图6B是根据本发明一些实施例绘示的形成封装结构各种阶段的剖面图。
其中，附图标记说明如下：
100、200、400、500、600～封装结构
102、142、162～基板
103～承载基板
106～介电层
107、180～重分布结构
108～粘合层
112～晶种层
114～导电结构
116～通孔
140～第一装置晶粒
144～介电层
146～导电垫
148、182、186、682、686～钝化层
150～连接器
160～第一虚置晶粒
165～第三装置晶粒
170～封装层
184、684～重分布线
186～顶钝化层
188、688～凸块下金属层
190、196、690～电连接器
192～载体
194～开口
300～顶部封装
302～封装基板
310～装置晶粒
616～第二通孔
640～第二装置晶粒
660～第二虚置晶粒
670～第二封装层
680～第二重分布结构
H1、H2、H3～高度
d1～间格距离
具体实施方式
以下公开许多不同的实施方法或是例子来实行本发明的不同特征，以下描述具体的元件及其排列的实施例以阐述本发明。当然这些实施例仅用以例示，且不该以此限定本发明的范围。例如第一特征形成于第二特征之上，其包括第一特征与第二特征是直接接触的实施例，另外也包括于第一特征与第二特征之间另外有其他特征的实施例，亦即，第一特征与第二特征并非直接接触。另外，本发明在不同例子中可能重复使用相同的元件符号及/或标号。此重复的目的是为了简洁性与清楚性且除非另有说明，否则不代表所讨论的各种实施例和配置之间有特定的关系。
在此并讨论一些实施例的变型。在各种附图及示意性实施例中，相似的参考编号被用于代表相似的元件。再者，在以下的制造过程中的各阶段之前、之中及之后，可提供一些额外的操作，且以下描述的一些操作在其他的实施例中可被代替或消除。
提供封装结构及其形成方法的实施例。图1A-图1D是根据本发明一些实施例绘示形成封装结构100各种阶段的剖面图。
如图1A所示，提供基板102。基板102可由硅或其他半导体材料如锗形成。于一些实施例中，基板102由半导体化合物如碳化硅、砷化镓、砷化铟和磷化铟形成。基板102为暂时支撑基板。于一些实施例中，基板102由半导体材料、陶瓷材料、高分子材料、金属材料、其他适合的材料或其组合形成。于一些实施例中，基板102为玻璃基板。于一些实施例中，基板102为半导体基板，如硅晶圆。
于基板102上形成介电层106。于一些实施例中，介电层106由高分子或含高分子层形成。介电层106可以是聚对苯撑苯并二噻唑(poly-p-phenylenebenzobisthiazole，PBO)层、聚酰亚胺(polyimide，PI)层、阻焊剂(solder resist，SR)层、ABF膜(Ajinomotobuildup film)、晶片附着膜(die attach film，DAF)、其他适合的材料或其组合。
通过使用粘合层108作为粘合胶，于介电层106上形成第一装置晶粒140和第一虚置晶粒160。粘合层108包括任何适合的粘合材料，如高分子材料。于一些实施例中，粘合层108包括双面胶。由层压制程、旋转涂布制程或其他适合的制程形成粘合层108。
第一装置晶粒140包括半导体基板142、介电层144、导电垫146、钝化层148和连接器150。导电垫146电性连接至连接器150。于一些实施例中，由氧化硅、氮氧化硅，硼硅酸盐玻璃(borosilicate glass，BSG)、磷酸硅玻璃(phosphoric silicate glass，PSG)、硼磷硅玻璃(borophosphosilicate glass，BPSG)、氟化硅酸盐玻璃(fluorinated silicateglass，FSG)、低介电常数(low-k)材料、多孔介电材料或其组合形成介电层144。于一些实施例中，由化学气相沉积(chemical vapor deposition，CVD)、旋转涂布制程、溅镀制程或其组合形成介电层144。
于一些实施例中，由氧化硅、氮化硅、氮氧化硅或其组合形成钝化层148。于一些其他实施例中，由高分子形成钝化层148。于一些实施例中，由CVD制程、旋转涂布制程、溅镀制程或其组合形成钝化层148。
可于第一装置晶粒140上形成其他装置元件。装置元件包括晶体管(例如，金属氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistors，MOSFET)，互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)晶体管，双极性接面型晶体管(bipolar junction transistors，BJT)，高压晶体管(high-voltage transistors)，高频晶体管(high-frequency transistors)，p通道和/或n通道场效应晶体管(p-channel and/or n-channel field effect transistors，PFET/NFET)等)，二极管和/或其它适用元件。进行各种制程如沉积、蚀刻、注入、光刻、回火及/或其他适合的制程，以形成装置元件。
第一虚置晶粒160包括基板162。可由硅或其他半导体材料如锗形成基板162。于一些实施例中，由如碳化硅、砷化镓、砷化铟或磷化铟的半导体化合物形成基板162。
第一虚置晶粒160并未提供任何功能，且于第一虚置晶粒160上并无连接器形成。第一虚置晶粒160用于降低基板102的不对称翘曲(于X和Y方向)或弯曲应力。第一虚置晶粒160的热膨胀系数大抵上相同或相似于第一装置晶粒140的热膨胀系数。于一些实施例中，由硅形成第一虚置晶粒160。若第一虚置晶粒160与第一装置晶粒140的热膨胀系数显着地不同，第一虚置晶粒160可能不会补偿应力。因此，在晶圆级封装阶段或封装(package，PKG)阶段可能发生不对称翘曲，并且导致晶圆级制程和PKG接合制程期间的产量损失。
第一装置晶粒140的上表面比第一虚置晶粒160的上表面高。进一步来说，钝化层148的上表面比第一虚置晶粒160的上表面高。第一装置晶粒140于Z方向有第一高度H1，第一虚置晶粒160于Z方向有第二高度H2(Z方向与基板102的上表面垂直)。第二高度H2小于第一高度H1。于一些实施例中，第二高度H2与第一高度H1的高度比值介于大约65％至大约85％的范围。若该比值大于85％，裂纹形成于第一虚置晶粒160和封装层(稍后形成)之间的界面上形成的重分布结构中的风险可能变得严重。如果该比值小于65％，则不对称翘曲的抑制可能不显着。
根据一些实施例，如图1B所示，于形成第一装置晶粒140和第一虚置晶粒160之后，于第一装置晶粒140和第一虚置晶粒160之间形成封装层170。换句话说，封装层170围绕第一装置晶粒140和第一虚置晶粒160。
于一些实施例中，封装层170由成型模料，例如液体环氧树脂(liquid epoxy)、可变形凝胶(deformable gel)、硅橡胶(silicon rubber)等形成。于一些实施例中，在第一装置晶粒140和第一虚置晶粒160上分配成型模料，因此进行热处理以硬化成型模料。进行平坦化制程以露出连接器150的上表面。于平坦化制程之后，第一装置晶粒140的上表面大抵与封装层170的上表面等高。于一些实施例中，平坦化制程包括研磨制程、化学机械抛光(chemical mechanical polishing，CMP)制程、蚀刻制程及其他适合的制程或其组合。
随后如图1C所示，根据一些实施例，于封装层170、第一装置晶粒140和第一虚置晶粒160上形成重分布结构180。重分布结构180包括至少一条重分布线(redistributionlines，RDL)和至少一层钝化层。重分布结构180包括形成于钝化层182上的RDL184。
于一些实施例中，由金属材料如铜、铜合金、铝、铝合金、钨、钨合金、钛、钛合金、钽或钽合金形成RDL184。于一些实施例中，由电镀、无电电镀、溅镀或CVD形成RDL184。于一些实施例中，由有机材料，例如聚苯并恶唑(polybenzoxazole，PBO)、苯并环丁烯(benzocyclobutene，BCB)、PI、硅氧树脂(silicone)、丙烯酸酯(acrylates)、硅氧烷(siloxane)或其组合形成钝化层182。于一些其它实施例中，钝化层182由非有机材料形成，如氧化硅、未掺杂硅酸盐玻璃、氮氧化硅、阻焊剂、氮化硅、六甲基二硅氮烷(hexamethyldisilazane，HMDS)等。
随后如图1D所示，根据一些实施例，于RDL184上形成顶钝化层186。于一些实施例中，顶钝化层186由有机材料形成，如聚苯并恶唑(polybenzoxazole，PBO)、BCB、PI、硅氧树脂、丙烯酸酯、硅氧烷或其组合。于一些其它实施例中，钝化层186由非有机材料形成，如氧化硅、未掺杂硅酸盐玻璃、氮氧化硅、阻焊剂、氮化硅、六甲基二硅氮烷等。
在钝化层186中形成凸块下金属(under bump metallurgy，UBM)层188，并且在UBM层188上形成电连接器190。电连接器190电性连接至RDL184。因此，得到封装结构100。
于形成封装结构100后，对封装结构100进行可靠度测试，以确认封装结构100的功能，进而预测封装结构100的平均故障时间(mean-time to failure，MTFF)。可靠度测试包括热循环制程。当对封装结构100进行热循环制程时，封装层170和第一装置晶粒140可能会以不同的速率膨胀，因封装层170、第一装置晶粒140和第一虚置晶粒160分别有不同的热膨胀系数。因此，应力聚集在封装层170和第一装置晶粒140间的界面。因此，直接位于封装层170和第一装置晶粒140间的界面上的RDL184可能会由于应力集中而裂开。特别是于部分直接位于第一装置晶粒140角落上的RDL184，破裂现象会变得更严重。当第二高度H2与第一高度H1等高时，在第一虚置晶粒160上将会出现破裂现象。
为了预防破裂，于第一装置晶粒140旁形成有较小高度H2的第一虚置晶粒160。和第一虚置晶粒160与第一装置晶粒140等高的例子相比，第一虚置晶粒160和封装层170间的界面相对来说离RDL184较远，以降低破裂的风险。
于一些实施例中，第二高度H2与第一高度H1的高度比值介于大约65％至大约85％的范围。若该范围大于85％，则破裂问题可能会变的严重。若该比值小于65％，翘曲会产生。
图2A是根据一些实施例绘示第一装置晶粒140和第一虚置晶粒160的俯视图。图1A是绘示沿着图2A中的线I-I’的剖面图。
如图2A所示，于基板102上形成第一装置晶粒140、第一虚置晶粒160和第三装置晶粒165。第一虚置晶粒160的俯视形状可为矩形、正方形、圆形或类似形状。第一虚置晶粒160的俯视形状取决于第一装置晶粒140和第三装置晶粒165的俯视形状。若于基板102上且邻近于第一装置晶粒140及第三装置晶粒165处无虚置晶粒，X方向的应力将不会与Y方向相同。因此，当封装结构100于热循环制程(高温和低温的循环)时，可能会因不平等的应力分布发生不对称翘曲或弯曲。
第一虚置晶粒160的第一功能是平衡应力分布，以预防于晶圆级封装或封装阶段的不对称翘曲。另外，由于具有高热膨胀系数的封装层170体积较小，通过使用第一虚置晶粒160也减少了基板102上的弯曲应力。具有比第一装置晶粒140的第一高度(H1)小的高度(H2)的第一虚置晶粒160的第二功能是降低在直接位于第一虚置晶粒160和封装层170间界面上的RDL184中破裂的风险。
于一些实施例中，于第一装置晶粒140和第一虚置晶粒160的间隔距离d1介于大约50μm至大约100μm间。若间隔距离d1比100μm大，则晶粒对晶粒(die-to-die，D2D)的通信距离变得更长，并导致在高运作频率下显着的信号延迟。若间格距离d1比50μm小，控制晶片放置过程的精度成为挑战。
图2B是根据一些实施例绘示封装层170覆盖第一虚置晶粒160的俯视图。图1B是绘示沿着图2B中的线II-II’的剖面图。
如图2B所示，封装层170覆盖第一虚置晶粒160，因此露出第一装置晶粒140的上表面和第三装置晶粒165的上表面。
排除区域(Keep-Out Zone，KOZ)的定义是指围绕着晶粒(如140和160)且之中不能放置任何元件的区域。直接位于重分布结构180的RDL184上的KOZ区可能会因为应力集中在KOZ区上而容易裂开。于制造封装结构100时，可对第一装置晶粒140、第一虚置晶粒160和封装层170进行一些热处理。封装层170和第一装置晶粒140可能会以不同的速率膨胀，因第一装置晶粒140、第一虚置晶粒160和封装层170各自有不同的热膨胀系数。因此，应力集中在靠近第一装置晶粒140的KOZ区上。若第一虚置晶粒160和第一装置晶粒140有相同的高度，将有12个KOZ区(每个晶粒有4个KOZ角落)。然而，如图2B所示，因为封装层170覆盖有较低高度的第一虚置晶粒160，因此存在8个KOZ区(圆圈区A)而不是12个KOZ区。因此，当KOZ区的数目降低时，于重分布结构180的RDL184的破裂问题随的降低。
图3A-图3G是根据一些实施例绘示的形成封装结构200各种阶段的剖面图。
如图3A所示，于承载基板103上形成释放层104。配置承载基板103，以在随后的制程步骤期间提供临时的机械和结构支撑。于一些实施例中，承载基板103包括玻璃、氧化硅、氧化铝及其组合等。于一些其他实施例中，承载基板103包括晶圆。
可以由胶或者例如箔的层压材料形成释放层104，。于一些实施例中，释放层104是光敏感的，并且容易通过光照射从承载基板103分离。如使用紫外光或激光光来剥离释放层104。于一些实施例中，释放层104是光热转换(light-to-heat conversion，LTHC)涂层。于一些其他实施例中，释放层104是热敏感的，并且当其暴露于热时容易从承载基板103分离。
在释放层104上形成介电层106。由高分子或含高分子层形成介电层106。介电层106可以是聚对苯撑苯并二噻唑(PBO)层、PI层、阻焊剂层、ABF膜、晶片附着膜、其他适合的材料或其组合。
在介电层106上形成晶种层112。之后，在晶种层112上形成掩模层(图未示)，并且在掩模层中形成开口以露出晶种层112。之后在开口中形成导电结构114。因此，导电结构114形成在晶种层112上。导电结构114和晶种层112合称直通互连通孔(through InFOvias，TIV)116，其也被称为通孔116。于一些实施例中，导电结构114和晶种层112由相同的材料形成，因此在它们之间没有可区分的界面。于一些实施例中，通孔116在Z方向上具有第三高度H3。
于一些实施例中，由金属材料如铜、钛、铜合金、钛合金或其组合形成晶种层112。于一些实施例中，通过沉积制程如CVD、物理气相沉积制程(physical vapor deposition，PVD)、其他适合的制程或其组合形成晶种层112。导电结构114可以由如铜、铝、钨、镍、其合金或其组合的金属材料形成。于一些实施例中，利用电镀制程形成导电结构114。
如图3B所示，根据一些实施例，在形成通孔116之后，通过使用粘合层108作为黏合剂，在介电层106上形成第一装置晶粒140和第一虚置晶粒160。于一些实施例中，黏合层108是晶片附着膜。
应注意，第一装置晶粒140具有第一高度H1，并且第一虚置晶粒160具有第二高度H2。第一高度H1高于第二高度H2。第三高度H3高于第一高度H1。于一些实施例中，第二高度H2与第一高度H1的高度比值介于大约65％至大约85％的范围。若该比值大于85％，于第一装置晶粒140和封装层170(稍后形成)之间的界面上形成的重分布结构中，形成裂纹的风险可能变得严重。若该比值小于65％，可能产生翘曲。
随后，在第一装置晶粒140和第一虚置晶粒160上形成封装层170。于一些实施例中，封装层170完全封装并覆盖第一装置晶粒140、第一虚置晶粒160和通孔(TIVs)116。封装层170直接接触第一虚置晶粒160。之后如图3C所示，根据一些实施例，在封装层170上进行平坦化以露出第一装置晶粒140的上表面和通孔116的上表面。
应当注意，封装层170覆盖第一虚置晶粒160。封装层170围绕或封装第一虚置晶粒160的上表面和侧壁，并且仅第一虚置晶粒160的底表面不与封装层170接触。
于一些实施例中，由成型模料形成封装层170，例如液体环氧树脂(liquidepoxy)、可变形凝胶(deformable gel)、硅橡胶(silicon rubber)等。于一些实施例中，在介电层106、第一装置晶粒140和第一虚置晶粒160上分配成型模料，因此进行热处理以硬化成型模料。在平坦化制程之后，第一装置晶粒140的上表面与通孔116的上表面大抵上等高。于一些实施例中，平坦化制程包括研磨制程、化学机械抛光制程、蚀刻制程、其他适合制程或其组合。
然后如图3D所示，根据一些实施例，在封装层170、第一装置晶粒140和第一虚置晶粒160上形成重分布结构180。重分布结构180包括至少一个RDL和至少一层钝化层。重分布结构180包括形成在钝化层182中的RDL184。
然后如图3E所示，根据一些实施例，在RDL184上形成钝化层186。在钝化层186中形成UBM层188，并且在UBM层188上形成电连接器190。电连接器190电性连接至RDL184。因此得到封装结构200。于一些实施例中，封装结构200是扇出(fan-out)晶圆级封装结构。扇出晶圆级封装表示晶片结构上的输入/输出垫(I/O pads)可以分布到比晶片结构更大的面积，因此可以增加晶片结构表面上输入/输出垫的数量。
如图3F所示，根据一些实施例，在形成电连接器190之后，去除承载基板103和释放层104。然后，将电连接器190附接至载体192上。通过将紫外光或激光光投射到释放层104上来移除承载基板103，分解释放层104。载体192包括光敏感或热敏感胶带，并且容易从电连接器190分离。
然后，移除一部分介电层106以形成开口194。于一些实施例中，未移除或完全移除晶种层112。于一些其它实施例中，移除一部分晶种层112，并露出剩余的晶种层112。于一些其它实施例中，通过激光钻孔制程、蚀刻制程或其他适合的制程形成开口194。
如图3G所示，根据一些实施例，在形成开口194之后，填入电连接器196到开口194中。然后，通过电连接器196将顶部封装300接合到封装结构200。在填入电连接器196到开口194之前，通过印刷或喷墨制程在开口194中预形成焊膏(未绘示)。
顶部封装300包括封装基板302和装置晶粒310。装置晶粒310至封装机板302的接合可由打线接合(wire-bonding)或覆晶接合(flip-chip bonding)等实现。于一些实施例中，装置晶粒310包括记忆晶粒，如静态随机存取存储器(tatic Random Access Memory，SRAM)晶粒，动态随机存取存储器(Dynamic Random Access Memory，DRAM)晶粒等。
之后，封装结构200可以继续经历其他制程以形成其他结构或装置。之后，进行切割制程以将结构分离成晶片封装体。
于一些实施例中，封装层170的热膨胀系数高于第一虚置晶粒160，并且第一虚置晶粒160的热膨胀系数与第一装置晶粒140类似。例如，在玻璃化转变温度(Tg)之前，由成型模料制成的封装层170的热膨胀系数介于约5ppm/℃至10ppm/℃，并且在Tg之前，由硅晶粒制成的第一虚置晶粒160的热膨胀系数为约2.5ppm/℃至约3.5ppm/℃。由于热膨胀系数的不协调，应力可能集中在第一虚置晶粒160和封装层170之间的界面上。因此，当第一虚置晶粒160的上表面低于第一装置晶粒140的上表面时，第一虚置晶粒160和封装层170的界面远离重分布结构180的RDL184的第一金属层(M1)。可以降低重分布结构180的RDL184的破裂，并且改善封装结构200的性能。
图4A-图4G是根据本发明一些实施例绘示的形成封装结构400各种阶段的剖面图。用于形成封装结构400的一些制程和材料与用于形成封装结构200的制程和材料相同或相似，并且在此不再重复。
如图4A所示，根据一些实施例，在承载基板103上形成释放层104。于一些实施例中，承载基板103包括玻璃、氧化硅、氧化铝或其组合等。于一些其他实施例中，承载基板103包括晶圆。
于释放层104上形成介电层106。于介电层106上形成通孔116。由导电材料形成通孔116。
随后如图4B所示，根据一些实施例，于介电层106上通过粘合层108形成第一装置晶粒140和第一虚置晶粒160。第一虚置晶粒160包括基板162和缓冲层164。
缓冲层164用于保护基板162在薄化制程期间不损坏或破裂。于一些实施例中，由高分子形成缓冲层164，例如聚对亚苯基苯并双噻唑(poly-p-phenylenebenzobisthiazole，PBO)或PI。于一些其他实施例中，由氧化硅、氮化硅、氮氧化硅或其组合形成缓冲层164。于一些实施例中，由相同的材料形成缓冲层164和钝化层148。
应当注意，第一装置晶粒140具有第一高度H1，并且第一虚置晶粒160具有第二高度H2。第二高度H2小于第一高度H1，以减少直接在封装层170和第一虚置晶粒160之间的界面上方的RDL线184的破裂。
如图4C所示，根据一些实施例，在形成第一装置晶粒140和第一虚置晶粒160之后，在第一装置晶粒140和第一虚置晶粒160之间形成封装层170。换句话说，封装层170围绕第一装置晶粒140和第一虚置晶粒160。
然后如图4D所示，根据一些实施例，在封装层170、第一装置晶粒140和第一虚置晶粒160上形成重分布结构180。重分布结构180包括至少一个RDL和至少一层钝化层。重分布结构180包括形成在钝化层182中的RDL184。
然后如图4E所示，根据一些实施例，在RDL184上形成钝化层186。在钝化层186中形成UBM层188，并且在UBM层188上形成电连接器190。电连接器190电性连接到RDL184。因此得到封装结构400。
如图4F所示，根据一些实施例，在形成电连接器190之后，去除承载基板103和释放层104。然后，将电连接器190附接至载体192。之后，去除介电层106的一部分以形成开口194。
如图4G所示，根据一些实施例，在形成开口194之后，填入电连接器196至开口194中。然后，顶部封装300通过电连接器196接合至封装结构400。顶部封装300包括封装基板302和装置晶粒310。
应当注意，在基板162上形成缓冲层164以保护基板162免于损坏，特别是当基板162具有较小的高度时。缓冲层164的上表面仍然低于第一装置晶粒140的上表面。因此，降低重分布结构的破裂问题。
图5A-图5G是根据本发明一些实施例绘示的形成封装结构500各种阶段的剖面图。用于形成封装结构500的一些制程和材料和形成封装结构200的制程和材料类似或相同，在此不再重复。
如图5A所示，在承载基板103上形成释放层104。在释放层104上形成介电层106。在介电层106上形成背侧重分布结构107。背侧重分布结构107包括至少一个RDL和至少一层钝化层。重分布结构107包括形成在钝化层中的RDL。于一些实施例中，RDL由金属材料形成，如铜、铜合金、铝、铝合金、钨、钨合金、钛、钛合金、钽或钽合金。
在重分布结构107上形成通孔116。由导电材料形成通孔116。通孔116电性连接至重分布结构107。
之后如图5B所示，根据一些实施例，第一装置晶粒140和第一虚置晶粒160通过粘合层108形成在重分布结构107上。第一虚置晶粒160包括基板162。于一些其它实施例中，在基板162上形成缓冲层。
之后如图5C所示，根据一些实施例，封装层170围绕第一装置晶粒140和第一虚置晶粒160。
然后如图5D所示，根据一些实施例，在封装层170、第一装置晶粒140和第一虚置晶粒160上形成重分布结构180。重分布结构180包括形成在钝化层182中的RDL184。
然后如图5E所示，根据一些实施例，在RDL184上形成钝化层186。在钝化层186中形成UBM层188，并且在UBM层188上形成电连接器190。因此，获得封装结构500。
如图5F所示，根据一些实施例，在形成电连接器190之后，移除承载基板103和释放层104。然后，将电连接器190附接至载体192。之后，去除介电层106的一部分以形成开口194。开口194露出背侧重分布结构107的金属层。
如图5G所示，根据一些实施例，在形成开口194之后，填入电连接器196至开口194中。然后，顶部封装300通过电连接器196接合至封装结构500。顶部封装300包括封装基板302和装置晶粒310。
图6A-图6B是根据本发明一些实施例绘示的形成封装结构600各种阶段的剖面图。用于形成封装结构600的一些制程和材料与封装结构200类似或相同，在此不再重复。
如图6A所示，在介电层106上形成第一装置晶粒140和第一虚置晶粒160。在介电层106上形成通孔116。封装层170封装第一装置晶粒140、第一虚置晶粒160和通孔116。
在封装层170上形成重分布结构180。在重分布结构180上形成第二虚置晶粒660和第二装置晶粒640。在重分布结构180上形成第二通孔616。由第二封装层670封装第二虚置晶粒660、第二装置晶粒640和第二通孔616。第二虚置晶粒660直接位于第一装置晶粒140上方，并且第二装置晶粒640直接位于第一虚置晶粒160上方，以预防封装结构600的不对称翘曲。
在第二封装层670上形成第二重分布结构680。第二重分布结构680包括形成在钝化层682中的RDL684。在RDL684上形成钝化层686，在钝化层686中形成UBM层688，在UBM层688上形成电连接器690。
然后，电连接器690附接到载体(carrier)(图未示)。随后，移除介电层106的一部分以形成开口194。开口194露出通孔116的底表面。
如图6B所示，根据一些实施例，在形成开口194之后，填入电连接器196至开口194中。然后，顶部封装300通过电连接器196接合至封装结构600。顶部封装300包括封装基板302和装置晶粒310。
本发明提供了用于形成封装结构以及用于形成该封装结构的方法的实施例。在基板上形成虚置晶粒和装置晶粒，并且通过封装层封装虚置晶粒和装置晶粒。在封装层上形成重分布结构。装置晶粒具有第一高度，并且虚置晶粒具有第二高度。第二高度小于第一高度。因此，虚置晶粒和封装层之间的界面远离重分布结构。因此，减少重分布结构破裂的问题，且提高封装结构的性能。
于一些实施例中，提供一种封装结构，包括基板及形成于基板上的装置晶粒。装置晶粒有第一高度。封装结构包括虚置晶粒，形成于基板上且邻近装置晶粒，其中虚置晶粒有第二高度。第二高度低于第一高度。封装结构也包括封装层，形成于装置晶粒及虚置晶粒间。
于一些实施例中，提供一种封装结构，包括基板及形成于基板上的第一装置晶粒。封装结构包括第一虚置晶粒，形成于基板上且邻近第一装置晶粒。封装结构也包括第一封装层，围绕第一装置晶粒及第一虚置晶粒，其中第一封装层覆盖第一虚置晶粒的上表面。封装结构也包括重分布结构，形成于第一封装层上，其中重分布结构电性连接至第一装置晶粒。
于一些实施例中，提供一种封装结构，包括第一封装结构和第二封装结构。第一封装结构包括第一装置晶粒、第一虚置晶粒、第一封装层以及重分布结构：第一装置晶粒形成于基板上，第一虚置晶粒形成于基板上，第一封装层围绕第一装置晶粒及第一虚置晶粒，其中第一封装层覆盖于第一虚置晶粒，重分布结构形成于该第一封装层上，其中重分布结构电性连接至第一装置晶粒。第二封装结构包括第二虚置晶粒以及第二封装层，第二虚置晶粒形成于重分布结构上，第二封装层围绕第二虚置晶粒，其中第二封装层覆盖第二虚置晶粒。
如本发明一些实施例所述的封装结构，还包括：一缓冲层，形成于该虚置晶粒上，其中该缓冲层的一上表面比该装置晶粒的一上表面低。
如本发明一些实施例所述的封装结构，还包括：一通孔，邻近该装置晶粒形成，其中该通孔有一第三高度，该第三高度高于该第一高度。
如本发明一些实施例所述的封装结构，还包括：一重分布结构，形成于该封装层上，其中该重分布结构电性连接至该装置晶粒。
如本发明一些实施例所述的封装结构，其中该第二高度与该第一高度的一高度比值介于大约65％至大约85％之范围。
如本发明一些实施例所述的封装结构，其中该虚置晶粒的一热膨胀系数大抵上与该装置晶粒的一热膨胀系数相同。
如本发明一些实施例所述的封装结构，还包括一通孔以及一第二封装结构，该通孔邻近该装置晶粒形成；该第二封装结构形成于该装置晶粒上，其中该第二封装结构电性连接至该通孔。
如本发明另一些实施例所述的封装结构，还包括一通孔，该通孔邻近该第一装置晶粒形成，其中该通孔的一上表面与该第一装置晶粒的一上表面等高。
如本发明另一些实施例所述的封装结构，还包括一第二封装结构，该第二封装结构形成于该第一装置晶粒上，其中该第二封装结构电性连接至该通孔。
如本发明另一些实施例所述的封装结构，还包括一凸块下金属(under bumpmetallurgy)层以及一电连接器，该凸块下金属层形成于该重分布结构上；该电连接器形成于该凸块下金属层上。
如本发明另一些实施例所述的封装结构，其中该第一装置晶粒有一第一高度，该第一虚置晶粒有一第二高度，该第二高度与该第一高度的一高度比值介于大约65％至大约85％的范围。
如本发明另一些实施例所述的封装结构，其中该第一虚置晶粒的一热膨胀系数与该第一装置晶粒的一热膨胀系数相同。
如本发明另一些实施例所述的封装结构，还包括一第二装置晶粒以及一第二虚置晶粒，该第二装置晶粒形成于该封装层之上；该二虚置晶粒邻近该第二装置晶粒形成。
如本发明另一些实施例所述的封装结构，还包括一第二封装层，该第二封装层形成于该第二装置晶粒及该第二虚置晶粒之间，其中该第二封装层覆盖于该第二虚置晶粒的一上表面。
如本发明又一些实施例所述的封装结构，还包括一通孔，该通孔邻近该第一装置晶粒形成，其中该通孔与该重分布结构电性连接。
如本发明又一些实施例所述的封装结构，其中该第一装置晶粒有一第一高度，该第一虚置晶粒有一第二高度，且该第二高度小于该第一高度。
如本发明又一些实施例所述的封装结构，还包括一缓冲层，该缓冲层形成于该第一封装结构上，其中该缓冲层形成于该第一虚置晶粒及该第一封装层之间。
如本发明又一些实施例所述的封装结构，还包括一第三封装结构，该第三封装结构形成于该第一封装结构下，其中该第一封装结构形成于该第二封装结构及该第三封装结构间。
上述内容概述许多实施例的特征，因此任何所属技术领域中技术人员，可更加理解本发明的各方面。任何所属技术领域中技术人员，可能无困难地以本发明为基础，设计或修改其他制程及结构，以达到与本发明实施例相同的目的及/或得到相同的优点。任何所属技术领域中技术人员也应了解，在不脱离本发明的精神和范围内做不同改变、代替及修改，如此等效的创造并没有超出本发明的原理及后附权利要求书的保护范围。

Claims (1)

1.一种封装结构，包括：
一基板；
一装置晶粒，形成于该基板上，其中该装置晶粒有一第一高度；
一虚置晶粒，形成于该基板上且邻近该装置晶粒，其中该虚置晶粒有一第二高度，该第二高度低于该第一高度；以及
一封装层，形成于该装置晶粒及该虚置晶粒间。
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