TW202310270A - 半導體裝置、封裝結構及其製備方法 - Google Patents

半導體裝置、封裝結構及其製備方法 Download PDF

Info

Publication number
TW202310270A
TW202310270A TW111101496A TW111101496A TW202310270A TW 202310270 A TW202310270 A TW 202310270A TW 111101496 A TW111101496 A TW 111101496A TW 111101496 A TW111101496 A TW 111101496A TW 202310270 A TW202310270 A TW 202310270A
Authority
TW
Taiwan
Prior art keywords
conductive
layer
intermetallic compound
conductive feature
semiconductor die
Prior art date
Application number
TW111101496A
Other languages
English (en)
Inventor
蔡宗甫
施應慶
盧思維
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202310270A publication Critical patent/TW202310270A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16501—Material at the bonding interface
    • H01L2224/16503—Material at the bonding interface comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/215—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73217—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8136—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/81375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8136—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/81379—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8181—Soldering or alloying involving forming an intermetallic compound at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92132—Sequential connecting processes the first connecting process involving a build-up interconnect
    • H01L2224/92135—Sequential connecting processes the first connecting process involving a build-up interconnect the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一種封裝結構包括半導體晶粒、第一絕緣包封體、多個第一導電特徵、內連線結構和凸塊結構。 半導體晶粒包括由第一材料製成的多個導電柱。 第一絕緣包封體包封半導體晶粒。 第一導電特徵設置在半導體晶粒上並且電性連接到導電柱。 第一導電特徵至少包括不同於第一材料的第二材料。 內連線結構設置在第一導電特徵上，其中內連線結構包括由第二材料製成的多個連接結構。 凸塊結構將第一導電特徵電性連接到連接結構，其中凸塊結構包括不同於第一材料和第二材料的第三材料。

Description

半導體裝置、封裝結構及其製備方法
本揭露是有關於一種半導體裝置、封裝結構及其製備方法。
在各種電子應用（例如手機及其他移動電子設備）中使用的半導體裝置及積體電路通常是在單個半導體晶圓上製造。可以在晶圓級下，對晶圓的晶粒進行處理並與其他半導體裝置或晶粒封裝在一起，且已開發出用於晶圓級封裝（wafer level packaging）的各種技術。
一種封裝結構，包括多個半導體晶粒、第一絕緣包封體、多個第一導電特徵、局部矽內連線結構以及凸塊結構。多個半導體晶粒包括由第一材料製成的多個導電柱。多個第一導電特徵設置在多個半導體晶粒上且與多個導電柱電性連接，其中第一導電特徵包括與第一材料不同的第二材料。局部矽內連線結構設置在多個第一導電特徵上，其中局部矽內連線結構包括由第二材料製成的多個連接結構，且局部矽內連線結構用以提供多個半導體晶粒之間的電性連接。凸塊結構將多個第一導電特徵電性連接至多個連接結構，其中凸塊結構包括不同於第一材料和第二材料的第三材料。
一種半導體裝置包括內連線結構、穿孔、導電柱、重分佈層、凸塊結構以及第一金屬間化合物。內連線結構包括多個連接結構。穿孔環繞內連線結構。導電柱電性連接到內連線結構和穿孔。重分佈層配置於導電柱上並包括多個第一導電特徵與多個第二導電特徵，多個第一導電特徵將多個連接結構電性連接至導電柱，並且多個第二導電特徵將穿孔電性連接到導電柱。凸塊結構設置在多個連接結構和多個第一導電特徵之間。第一金屬間化合物夾置在多個第一導電特徵與凸塊結構之間，其中以第一金屬間化合物的厚度T1與凸塊結構的厚度TB之總和為100％時，第一金屬間化合物的厚度T1在5%到20%的範圍內。
一種封裝結構的製備方法包括以下步驟。提供半導體晶粒，半導體晶粒包括由第一材料製成的多個導電柱。形成包封半導體晶粒的第一絕緣包封體。在半導體晶粒上形成多個第一導電特徵並電性連接到多個導電柱，其中多個第一導電特徵件至少包括與第一材料不同的第二材料。在多個第一導電特徵上提供內連線結構，其中內連線結構包括由第二材料製成的多個連接結構。在多個第一導電特徵和多個連接結構之間提供凸塊結構，並執行回焊製程，使得凸塊結構將多個第一導電特徵電性連接到多個連接結構，其中凸塊結構包括不同於第一材料和第二材料的第三材料。
以下揭露內容提供用於實施本公開實施例的不同特徵的許多不同實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵之上或第二特徵上可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本揭露可能在各種實例中重複使用元件符號及/或字母。此種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可使用例如「在…之下（beneath）」、「在…下方（below）」、「下部的（lower）」、「在…上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向（旋轉90度或處於其他定向），且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
還可包括其他特徵及製程。舉例來說，可包括測試結構以說明對三維（three-dimensional，3D）封裝或三維積體電路（three-dimensional integrated circuit，3DIC）裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或基底上形成的測試焊盤（test pad），以便能夠對3D封裝或3DIC進行測試、使用探針及/或探針卡（probe card）等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可與包含對已知良好晶粒（known good die）進行中間驗證的測試方法結合使用以提高良率並降低成本。
圖1至圖13是根據本公開的一些示例性實施例的製造封裝結構的方法中的各個階段的示意性剖面圖。參考圖1，提供了載體102，其上方塗覆有緩衝層104。在一個實施例中，載體102可以是玻璃載體或是適合於承載半導體晶圓或用於封裝結構製造方法的重組晶圓的任何載體。
在一些實施例中，緩衝層104包括剝離層104A和介電層104B，其中剝離層104A位於載體102和介電層104B之間。在某些實施例中，剝離層104A設置在載體102上，剝離層104A的材料可以是任何適合用於將載體102從上述層面（例如、介電層104B）或設置在其上的任何晶圓結合和剝離的材料。在一些實施例中，剝離層104A可包括釋放層（例如光熱轉換（“LTHC”）層）或黏合層（例如紫外線固化黏合劑或熱固化黏合劑層）。在一些實施例中，介電層104B可以形成在剝離層104A上方。介電層104B可由介電材料製成，例如苯並環丁烯（“BCB”）、聚苯並噁唑（“PBO”）或任何其他合適的基於聚合物的介電材料。需要說明的是，載體102、剝離層104A以及介電層104B的材料不限於實施例的描述。在一些替代實施例中，可以選擇性地省略介電層104B；換言之，可以僅在載體102上方形成剝離層104A。
參考圖2，例如是通過一個取放製程（pick-and-place process）將第一半導體晶粒106和第二半導體晶粒107放置在緩衝層104上。在一些實施例中，第一半導體晶粒106和第二半導體晶粒107是通過晶粒貼合膜105被放置到緩衝層104上。在示例性的實施例中，第一半導體晶粒106和第二半導體晶粒107中的每一者包括半導體基底（106A/107A）、多個導電接墊（106B/107B）、鈍化層（106C/107C）、多個導電柱（106D、107D）以及保護層（106E、107E）。
如圖2所示，多個導電接墊（106B/107B）設置在半導體基底（106A/107A）上。鈍化層（106C/107C）形成在半導體基底（106A/107A）上方並且具有開口以部分的暴露出半導體基底（106A/107A）上的導電接墊（106B/107B）。半導體基底（106A/107A）可以是塊狀矽基底或絕緣體上矽（SOI）基底，並且還包括主動元件（例如，電晶體等）和可選的被動元件（例如電阻器、電容器、 電感器等）形成在其中。導電接墊（106B/107B）可以是鋁墊、銅墊或其他合適的金屬墊。鈍化層（106C/107C）可以是氧化矽層、氮化矽層、氮氧化矽層或由任何合適的介電材料形成的介電層。
此外，在一些實施例中，是選擇性地在鈍化層（106C/107C）上方形成後鈍化層（未示出）。後鈍化層覆蓋鈍化層（106C/107C）並具有多個接觸開口。導電接墊（106B/107B）被後鈍化層的接觸開口部分的暴露出。後鈍化層可以是苯並環丁烯（BCB）層、聚醯亞胺層、聚苯並噁唑（PBO）層或由其他合適的聚合物形成的介電層。在一些實施例中，導電柱（106D、107D）通過電鍍形成在導電接墊（106B、107B）上。導電柱（106D、107D）可以由第一材料製成，例如，第一材料可以是銅、或類似材料。在一些實施例中，保護層（106E、107E）形成於鈍化層（106C/107C）上或後鈍化層上，並覆蓋導電柱（106D、107D）以保護導電柱(106D、107D）。
在一些實施例中，第一半導體晶粒106可以是邏輯裝置，例如中央處理單元（CPU）、圖形處理單元（GPU）、晶片上系統（SoC；system-on-a-chip）、微控制器等。第二半導體晶粒107可以是記憶體裝置，例如動態隨機存取記憶體（DRAM）晶粒、靜態隨機存取記憶體（SRAM）晶粒、混合記憶體立方體（HMC；hybrid memory cube）模塊、高帶寬記憶體（HBM；high bandwidth memory）模塊，或類似裝置。在一些實施例中，第一半導體晶粒106和第二半導體晶粒107可以是相同類型的晶粒，例如SoC晶粒。第一半導體晶粒106和第二半導體晶粒107可以具有不同的尺寸（例如，不同的高度和/或表面積），或者可以具有相同的尺寸（例如，相同的高度和/或表面積）。
參考圖3，在緩衝層104上放置第一半導體晶粒106和第二半導體晶粒107之後，是在緩衝層104上方形成絕緣材料108以覆蓋第一半導體晶粒106和第二半導體晶粒107。在一些實施例中，絕緣材料108通過例如壓縮模製製程形成，以填充半導體晶粒（106/107）之間的間隙並包封半導體晶粒（106/107）。在此階段，半導體晶粒（106/107）的導電柱（106D/107D）和保護層（106E/107E）被絕緣材料108包封，並且被絕緣材料108很好的保護起來。換句話說，導電柱（106D/107D）和半導體晶粒（106/107）的保護層（106E/107E）沒有被暴露出來，並受到絕緣材料108的良好保護。
在一些實施例中，絕緣材料108例如包括聚合物（例如環氧樹脂、酚醛樹脂、含矽樹脂或其他合適的樹脂）、具有低介電常數（Dk）和低損耗正切（Df）特性的介電材料、或其他合適的材料。在某些實施例中，絕緣材料108還包括可被添加到其中以使絕緣材料108的熱膨脹係數（CTE；coefficient of thermal expansion）優化的無機填料或無機化合物（例如二氧化矽、黏土等）。本揭露並非僅限於此。
參考圖4，在隨後的步驟中，絕緣材料108被部分的移除以暴露出第一半導體晶粒106和第二半導體晶粒107的導電柱（106D/107D）。在一些實施例中，絕緣材料108和保護層 （106E/107E）通過平面化步驟進行研磨或拋光。例如，通過機械研磨製程和/或化學機械拋光（CMP；chemical mechanical polishing）製程進行平坦化步驟，直到導電柱（106D/107D）的頂表面（106-TS/107-TS）展露出為止。在一些實施例中，絕緣材料108被拋光以形成絕緣包封體108'。在一些實施例中，在平坦化步驟之後，導電柱（106D/107D）的頂表面（106-TS/107-TS）和絕緣包封體108'的頂表面108-TS共面且彼此齊平。在一些實施例中，在機械研磨或化學機械拋光（CMP）步驟之後，可以選則性的執行清潔步驟。例如，執行清潔步驟以清潔和去除平坦化步驟中所產生的殘留物。然而，本揭露不限於此，且所述平坦化步驟也可以通過任何其他合適的方法來執行。
參考圖5，在隨後的步驟中，可以在絕緣包封體108'上以及第一半導體晶粒106和第二半導體晶粒107上方形成重分佈層RDL1。在一些實施例中，形成重分佈層RDL1包括形成設置在絕緣包封體108'上的介電層110，並在介電層110上形成第一導電特徵114和第二導電特徵116。在一些實施例中，介電層110可以是使用微影罩幕圖案化的感光材料形成，例如聚苯並噁唑（PBO）、聚醯亞胺、苯並環丁烯（BCB）聚合物、環烯烴共聚物、丙烯酸類共聚物等，其可以通過旋塗、層壓、化學氣相沉積（CVD；chemical vapor deposition）等方式形成。也可以使用通過任何可接受的製程形成的其它可接受的介電材料。在一些實施例中，介電層110可以被圖案化以形成暴露出第一半導體晶粒106和第二半導體晶粒107的導電柱（106D/107D）的開口。
在一些實施例中，第一導電特徵114和第二導電特徵116形成在介電層110上，並填充到介電層110的開口中。例如，第一導電特徵114和第二導電特徵116是電性連接到第一半導體晶粒106和第二半導體晶粒107的導電柱（106D/107D）。在一些實施例中，在形成第一導電特徵114和第二導電特徵116之前，可以共形地在介電層110上方和介電層110的開口內形成晶種層（未示出）。接著，可以在晶種層上方形成導電材料，從而將晶種層圖案化以形成晶種層112A、112B，並且將導電材料圖案化以形成第一導電特徵114和第二導電特徵116。在一些實施例中，晶種層112A夾置在導電柱（106D/107D）和第一導電特徵114之間，而晶種層112B夾置在導電柱（106D/107D）和第二導電特徵116之間。在一些實施例中，晶種層112A、112B可由化學鍍（electroless plating）、化學氣相沉積 （CVD）、物理氣相沉積（PVD；physical vapor deposition）、原子層沉積 （ALD；atomic layer deposition）、高密度電漿CVD（HDPCVD；high density plasma chemical vapor deposition）或它們的組合來形成。在一實施例中，晶種層112A、112B藉由依序沉積或濺射鈦層和銅層而形成。
如圖5進一步所示，第一導電特徵114包括第一通孔部分114A和第一主體部分114B。例如，第一通孔部分114A是設置在介電層110的開口內並且被晶種層112A所圍繞。第一通孔部分114A通過晶種層112A連接或電性連接到導電柱（106D/107D）。第一主體部分114B設置在第一通孔部分114A上並形成在晶種層112A和介電層110上方。類似地，第二導電特徵116包括第二通孔部分116A和第二主體部分116B。例如，第二通孔部分116A設置在介電層110的開口內並且被晶種層112A所圍繞。第二通孔部分116A通過晶種層112A連接或電性連接到導電柱（106D/107D）。第二主體部分116B設置在第二通孔部分116A上並形成在晶種層112A和介電層110上方。
在一些實施例中，第一導電特徵114和第二導電特徵116由與導電柱（106D/107D）的第一材料不同的第二材料所製成。舉例來說，在一個實施例中，第二材料是鎳而第一材料是銅。第一導電特徵114和第二導電特徵116可以通過電鍍或沉積形成，並且可以使用微影和蝕刻製程來圖案化。
參考圖6，在後續步驟中，可在第二導電特徵116上形成多個穿孔118。例如，穿孔118是設置在第二導電特徵116的第二主體部分116B上並電性連接至第二主體部分116B。在一些實施例中，穿孔118的形成包括形成具有開口的罩幕圖案（未示出），然後通過電鍍或沉積形成填充開口的金屬材料（未示出），並去除罩幕圖案以形成穿孔118。在一些實施例中，穿孔118由第一材料所製成。例如，穿孔118可以包括諸如銅或銅合金等的金屬材料。
參考圖7，在形成穿孔118之後，是將內連線結構120設置在第一導電特徵114上以電性連接到第一導電特徵114。內連線結構120可以是局部矽內連線（LSI；local silicon interconnects），大型積體電路封裝、中介層晶粒等。在一些實施例中，內連線結構120包括基底120A、介電層120B、基底穿孔120C、導電接墊120D和連接結構120E。基底120A可以是半導體基底、介電層等。基底穿孔120C延伸穿過基底120A，並在內連線結構的背面被暴露出。介電層120B設置於基底120A上。導電接墊120D被介電層120B圍繞，同時電性連接至基底穿孔120C。此外，連接結構120E設置於導電接墊120D上並電性連接至導電接墊120D。
在內連線結構120是局部矽內連線（LSI）的一些實施例中，內連線結構120可以包括用於將第一半導體晶粒106電性連接到第二半導體晶粒107的橋接結構（未示出）。例如，橋接結構可以電性連接到一部份的連接結構120E。在一個實施例中，連接結構120E可以由類似於第一導電特徵114的第二材料所製成。舉例來說，在一些實施例中，連接結構120E和第一導電特徵114均由鎳所製成。在某些實施例中，連接結構120E的材料不同於導電接墊120D和基底穿孔120C的材料。
如圖7進一步所示，在一些實施例中，是在第一導電特徵114和連接結構120E之間提供凸塊結構122，並且執行回焊製程使得凸塊結構122電性連接到第一導電特徵114 以及連接結構120E。在某些實施例中，內連線結構120是通過凸塊結構122和第一導電特徵114電性連接到第一半導體晶粒106和第二半導體晶粒107。
在一些實施例中，凸塊結構122至少由不同於導電柱（106D/107D）的第一材料，並且不同於第一導電特徵114和連接結構120E的第二材料的第三材料所製成。舉例來說，第三材料包括諸如焊料（solder）或類似的導電材料。在某些實施例中，第一材料是銅，第二材料是鎳，而第三材料是錫。在一個實施例中，凸塊結構122是通過蒸發、電鍍、印刷、焊料轉移、焊球放置等步驟來初步形成焊料層而形成。接著，可以執行回焊製程以對焊料材料塑形，並且使得凸塊結構112與第一導電特徵114和連接結構120E接合。
在第一導電特徵114上放置內連線結構120之後，可以形成底部填充結構124以填充內連線結構120和重分佈層RDL1之間的間隙。舉例來說，底部填充結構124是覆蓋並圍繞連接結構120E、凸塊結構122和第一導電特徵114的第一主體部分114B。底部填充結構124可以減少應力並保護由凸塊回焊引起的接點。底部填充結構124可以用液體或是半液體形式方式施加，然後隨後進行固化。
圖8A是圖7所示的連接結構120E、凸塊結構122與第一導電特徵114之間的接合處的放大圖。在示例性的實施例中，在執行回焊製程以將凸塊結構122接合至連接結構120E和第一導電特徵114之後，可以形成第一金屬間化合物IMC1和第二金屬間化合物IMC2。在一些實施例中，第一金屬間化合物IMC1形成在第一導電特徵114和凸塊結構122之間，而第二金屬間化合物IMC2形成在連接結構120E和凸塊結構122之間。在示例性的實施例中，由於第一導電特徵114和連接結構120E由第二材料（例如鎳）所製成，第一金屬間化合物IMC1和第二金屬間化合物IMC2可以包括基於Ni-Sn的金屬間化合物。例如，在一個實施例中，第一金屬間化合物IMC1和第二金屬間化合物IMC2可以是Ni 3Sn 4。
如圖8A所示，第一金屬間化合物IMC1的最大厚度為T1，第二金屬間化合物IMC2的最大厚度為T2，而凸塊結構122的最小厚度為TB。在一些實施例中，以第一金屬間化合物IMC1的厚度T1與凸塊結構122的厚度TB之總和為100％時，第一金屬間化合物IMC1的厚度T1會在5％至20％（T1 /(T1+TB)）的範圍內。在某些實施例中，以第一金屬間化合物IMC1的厚度T1與凸塊結構122的厚度TB之總和為100％時，第一金屬間化合物IMC1的厚度T1會在5％至10％（T1 /(T1+TB)）的範圍內。
類似地，以第二金屬間化合物IMC2的厚度T2與凸塊結構的厚度TB之總和為100％時，第二金屬間化合物IMC2的厚度T2會在5％至20％（T2 /(T2+TB)）的範圍內。在某些實施例中，以第二金屬間化合物IMC2的厚度T2與凸塊結構的厚度TB之總和為100％時，第二金屬間化合物IMC2的厚度T2會在5％至10％（T2 /(T2+TB)）的範圍內。
通過使用第二材料（例如鎳）作為連接結構120E的材料和第一導電特徵114的材料，由於第二材料的反應性較低，因此連接結構120E以及第一導電特徵114分別與凸塊結構122的接合處將導致較少的金屬間化合物的形成。也就是說，可以將第一金屬間化合物IMC1和第二金屬間化合物IMC2的厚度控制在上述範圍內，其可提高接點良率，並且可靠性問題會更少。
圖8B和圖8C是根據本公開的一些比較例的連接結構120E、凸塊結構122和第一導電特徵114之間的接合處的放大圖。
在圖8B所示的比較例中，連接結構120E和第一導電特徵114由銅所製成。因此，在執行回焊製程以將凸塊結構122接合到連接結構120E和第一導電特徵114之後，將會形成具有更大厚度（T1、T2）的第一金屬間化合物IMC1和第二金屬間化合物IMC2。例如，以第一金屬間化合物IMC1的厚度T1與凸塊結構122的厚度TB之總和為100％時，第一金屬間化合物的厚度T1在25％至55％（T1/ (T1+TB)）的範圍內。類似地，以第二金屬間化合物IMC2的厚度T2與凸塊結構的厚度TB之總和為100％時，第二金屬間化合物IMC2的厚度T2在25％至55％（T2/( T2+TB)） 的範圍內。由於銅材料的快速反應會形成Cu 6Sn 5金屬間化合物，因此，第一金屬間化合物IMC1和第二金屬間化合物IMC2的厚度會增加。基於此，粗糙且較厚的Cu 6Sn 5金屬間化合物的形成可能會導致不良接合，並且在連接結構120E、凸塊結構122和第一導電特徵114之間的接合會存在可靠性問題。
在圖8C所示的比較例中，連接結構120E與第一導電特徵114由鎳所製成，但在連接結構120E上形成有額外的銅層120F以連接凸塊結構122。在此實施例中，在執行回焊製程以將凸塊結構122接合至連接結構120E和第一導電特徵114時，至少將形成具有更大厚度（T2）的第二金屬間化合物IMC2。例如，以第二金屬間化合物IMC2的厚度T2與凸塊結構的厚度TB之總和為100％時，第二金屬間化合物IMC2的厚度T2在25％至55％（T2/ (T2+TB)）的範圍內。由於銅材料的快速反應會形成Cu 6Sn 5金屬間化合物，因此，第二金屬間化合物IMC2的厚度會增加。基於此，粗糙且較厚的Cu 6Sn 5金屬間化合物的形成可能會導致不良接合，而連接結構120E、凸塊結構122與第一導電特徵114之間的接合仍會存在可靠性問題。
參考圖9，在執行回焊製程以將凸塊結構122接合到連接結構120E和第一導電特徵114之後，絕緣材料126是形成在介電層110和絕緣包封體108'上方，並形成為包封內連線結構120和穿孔118。在一些實施例中，絕緣材料126通過例如壓縮模製製程形成，以填充內連線結構120和相鄰穿孔118之間的間隙。在此階段， 內連線結構120和穿孔118被絕緣材料126包封，並且被很好的保護起來。
在一些實施例中，絕緣材料126例如包括聚合物（例如環氧樹脂、酚醛樹脂、含矽樹脂或其他合適的樹脂）、具有低介電常數（Dk）和低損耗角正切（Df）特性的介電材料，或其他合適的材料。在替代實施例中，絕緣材料126可以包括可接受的絕緣封裝材料。 在一些實施例中，絕緣材料126還包括可被添加到其中以使絕緣材料126的熱膨脹係數（CTE；coefficient of thermal expansion）優化的無機填料或無機化合物（例如二氧化矽、黏土等）。在某些實施例中，絕緣材料126可以與絕緣材料108相同或不同。本揭露並非僅限於此。
參考圖10，在一些實施例中，是執行薄化步驟以形成絕緣包封體126'。舉例來說，是減小絕緣材料126的厚度直到露出穿孔118的頂表面118-TS和基底穿孔120C的頂表面120-TS為止。在某些實施例中，絕緣材料126通過機械研磨製程和/或化學機械拋光（CMP）製程而被研磨或拋光以形成絕緣包封體126'。在一些實施例中，穿孔118可以被部分的拋光，使得穿孔118的頂表面118-TS與基底穿孔120C的頂表面120-TS齊平。在一些實施例中，絕緣包封體126'的頂表面126-TS、穿孔118的頂表面118-TS以及基底穿孔120C的頂表面120-TS彼此共面且齊平。
參考圖11，在薄化步驟之後，重分佈層128是形成在內連線結構120和穿孔118上方，位於絕緣包封體126'上。在一些實施例中，重分佈層128可以包括多層介電層128A和多層導電元件128B交替堆疊。雖然在此處僅繪示了兩層導電元件128B和三層介電層128A，然而，本公開的範圍不受本公開實施例的限制。 在其他實施例中，導電元件128B和介電層128A的層數可根據產品需求而進行調整。在一些實施例中，導電元件128B通過穿孔118電性連接到第一半導體晶粒106和第二半導體晶粒107。
在一些實施例中，介電層128A的材料可為聚醯亞胺、聚苯並噁唑（PBO）、苯並環丁烯（BCB）、氮化物例如氮化矽、氧化物例如氧化矽、磷矽玻璃（PSG）、硼矽玻璃（BSG）例如，硼摻雜磷矽玻璃（BPSG）、其組合或類似材料，且其可以使用微影和/或蝕刻製程來圖案化。在一些實施例中，介電層128A通過合適的製造技術形成，例如旋塗、化學氣相沉積（CVD）、電漿輔助化學氣相沉積（PECVD）等。本公開不限於此。
在一些實施例中，導電元件128B的材料可以為藉由電鍍或沉積形成的導電材料而製成，且例如包括鋁、鈦、銅、鎳、鎢和/或它們的合金，且可以使用微影和蝕刻來進行圖案化。在一些實施例中，導電元件128B可以是圖案化銅層或其他合適的圖案化金屬層。在說明書通篇中，用語“銅”旨在包括實質上純的元素銅、含有不可避免的雜質的銅以及含有少量元素（例如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯等）的銅合金。
在形成重分佈層128之後，可以在導電元件128B的最頂層的暴露的頂表面上設置多個導電接墊128C，以與導電端子（例如導電球）電性連接。在某些實施例中，導電接墊128C例如是用於球安置的球下金屬（under-ball metallurgy，UBM）圖案。如圖11所示，導電接墊128C形成於重分佈層128上並與其電性連接。在一些實施例中，導電接墊128C的材料可以包括銅、鎳、鈦、鎢或其合金，或類似材料，並且可例如通過電鍍製程而形成。本公開對導電接墊128C的數量不作限制，且可根據設計佈局進行選擇。在一些替代性實施例中，可以省略導電接墊128C。換言之，在後續步驟中形成的導電端子130可以直接設置在重佈線層128上。
如圖11所示，在形成導電接墊128C之後，多個導電端子130是設置在導電接墊128C上，位於重分佈層128上方。在一些實施例中，導電端子130可以通過植球（ball placement）製程或回焊製程而設置在導電接墊128C上。在一些實施例中，導電端子130例如是焊球或球柵陣列（ball grid array；BGA）球。在一些實施例中，導電端子130通過導電接墊128C連接到重分佈層128。在某些實施例中，一些導電端子130可以通過重分佈層128電性連接到半導體晶粒（106/107）。導電端子130的數量不限於本公開內容，並且可以基於導電接墊128C的數量來進行指定和選擇。
參考圖12，在形成重分佈層128並在其上方放置導電端子130之後，是將圖11所示的結構倒置並貼合到由框架302支撐的膠帶304（例如，切割膠帶（dicing tape）304）上。在一些實施例中，是剝離載體102以將第一半導體晶粒106和第二半導體晶粒107與載體102分離。在一些實施例中，剝離製程包括將例如雷射或紫外（ultra-violet，UV）光等光投射在剝離層104A上，使載體102能夠被輕易移除。在某些實施例中，剝離層104A可以被進一步去除或剝離。在剝離製程之後，介電層104B會被顯露出來。在一些替代實施例中，介電層104B可以被省略，因此，可以露出第一半導體晶粒106和第二半導體晶粒107的背面。在一些實施例中，可以執行切割或鋸切製程以將單獨的封裝彼此分離。舉例來說，在完成鋸切製程後，可以完成根據本公開的一些實施例的如圖13所示的封裝結構PK1（或半導體裝置）。
圖14為本公開的其他實施例的封裝結構的示意性剖面圖。圖14所示的封裝結構PK2（或半導體裝置）與圖13所示的封裝結構PK1類似，因此相同的元件符號將用於表示相同或類似的部件，且於此不再予以贅述。實施例之間的區別在於，第一導電特徵114和第二導電特徵116的設計。
在圖13中，第一導電特徵114包括均由第二材料（例如，鎳）所製成的第一通孔部分114A和第一主體部分114B，並且，第二導電特徵116包括均由第二種材料（例如，鎳）所製成的第二通孔部分116A和第二主體部分116B。然而，本公開不限於此。舉例來說，參考圖14，第一通孔部分114A由第一材料（例如，銅）所製成，而第一主體部分114B由第二材料（例如，鎳）所製成。類似地，第二通孔部分116A由第一材料（例如，銅）所製成，而第二主體部分116B由第二材料（例如，鎳）所製成。
如圖14中進一步所示，在一些實施例中，晶種層112A可包括第一部分112A-1和第二部分112A-2，其中第一部分112A-1圍繞第一通孔部分114A，而第二部分112A-2將第一通孔部分114A與第一主體部分114B物理性分離。類似地，晶種層112B可以包括第一部分112B-1和第二部分112B-2，其中第一部分112B-1圍繞第二通孔部分116A，而第二部分112B-2將第二通孔部分116A 與第二主體部分116B物理性分離。
在圖14的實施例中，由於第一主體部分114B和連接結構120E由第二材料（例如，鎳）所製成，由於第二材料（例如，鎳）的較低反應性，因此，連接結構120E和第一導電特徵114與凸塊結構122的接點將導致較少的金屬間化合物的形成。基於此，第一金屬間化合物IMC1和第二金屬間化合物IMC2的厚度可以控制在最小範圍內，其可以提高接點良率，同時可靠性問題會更少。
圖15為本公開其他實施例的封裝結構的示意性剖面圖。 圖15所示的封裝結構PK3（或半導體裝置）與圖13所示的封裝結構PK1相似。因此，相同的元件符號將用於表示相同或類似的部件，且於此不再予以贅述。實施例之間的區別在於重分佈層RDL1的設計。
在圖13中，重分佈層RDL1包括介電層110、晶種層112A、112B、第一導電特徵114和第二導電特徵116。換言之，重分佈層RDL1由單層的介電材料（介電材料110）和單層的導電材料（第一和第二導電特徵114、116）所構成。然而，本公開不限於此，且重分佈層RDL1還可以包括更多的導電層和介電層。舉例來說，參考圖15，重分佈層RDL1還可以包括導電元件層216，其設置在導電柱（106D/107D）和第一導電特徵114之間，且設置在導電柱（106D/107D）和第二導電特徵116之間。此外，導電元件層216是位於兩個介電層210之間，並且導電元件層216是形成在晶種層212之上。
在示例性的實施例中，導電元件層216的材料不同於第一導電特徵114和第二導電特徵116的材料。舉例來說，導電元件層216可以由第一材料（例如，銅）所製成，而第一導電特徵114和第二導電特徵116是由第二材料（例如，鎳）所製成。雖然此處僅繪示了一層導電元件層216和兩層介電層210，但需注意的是，導電元件層216和介電層210的數量不限於此，而可以根據設計需求來進行調整。
在圖15的實施例中，由於第一導電特徵114和連接結構120E由第二材料（例如，鎳）所製成，由於第二材料（例如，鎳）的較低反應性，因此，連接結構120E和第一導電特徵114與凸塊結構122的接點將導致較少的金屬間化合物的形成。基於此，第一金屬間化合物IMC1和第二金屬間化合物IMC2的厚度可以控制在最小範圍內，其可以提高接點良率，同時可靠性問題會更少。
圖16至圖18是根據本公開的一些其他示例性實施例的製造封裝結構的方法中的各個階段的示意性剖面圖。圖16至圖18所示的方法與圖1至圖13所示的方法類似。因此，相同的元件符號將用於表示相同或類似的部件，且於此不再予以贅述。實施例之間的區別在於圖16至圖18中存在金屬化層117。
如圖16所示，可以執行與圖1至圖5中所示相同的步驟以在第一半導體晶粒106和第二半導體晶粒107上方形成第一導電特徵114和第二導電特徵116。在一些實施例中，金屬化層117是做為為潤濕層（wetting layer）而形成在第一導電特徵114和第二導電特徵116上。金屬化層117可以是貴金屬，例如金（Au）、鈀（Pd）、鉑（Pt）或類似材料。在一個實施例中，金屬化層117是金質層，其可以設置在第一導電特徵114和第二導電特徵116的第二材料（例如，鎳）上方，以防止其氧化並提高潤濕性。是以金屬化層117的側壁與第一導電特徵114的側壁和第二導電特徵116的側壁對齊的方式，使金屬化層117設置在第一導電特徵114和第二導電特徵116上方。
參考圖17A，在後續步驟中，是位於第二導電特徵116上方在金屬化層117上形成穿孔118。所述穿孔118通過金屬化層117電性連接到第二導電特徵116。接著，是將內連線結構120設置在第一導電特徵114上方的金屬化層117上。在一些實施例中，是在金屬化層117和連接結構120E之間提供凸塊結構122，並且執行回焊製程使得凸塊結構122 電性連接至第一導電特徵114和連接結構120E。在某些實施例中，當執行回焊製程以接合凸塊結構122時，金屬化層117會熔化並溶解到凸塊結構122中。換言之，形成於第一導電特徵114上方的金屬化層117將會消失。
舉例來說，參考圖17B所示的連接結構120E、凸塊結構122與第一導電特徵114之間的接合處的放大圖，在回焊製程時，金屬化層117會熔化以形成金屬元素117'，其會溶解到凸塊結構122中。例如，若金屬化層117是金質層，則金元素將會溶解到凸塊結構122（例如，焊料）中。在這樣的實施例中，在執行回焊製程以將凸塊結構122接合到連接結構120E和第一導電特徵114之後，可以形成第一金屬間化合物IMC1和第二金屬間化合物IMC2。舉例來說，第一金屬間化合物IMC1可以包括基於Au-Sn和基於Ni-Sn的金屬間化合物，而第二金屬間化合物IMC2可以包括基於Ni-Sn的金屬間化合物。在一個實施例中，第一金屬間化合物IMC1包括AuSn 4和Ni 3Sn 4，而第二金屬間化合物IMC2則包括Ni 3Sn 4。
如圖17B所示，第一金屬間化合物IMC1的最大厚度為T1，第二金屬間化合物IMC2的最大厚度為T2，而凸塊結構122的最小厚度為TB。在此實施例中，以第一金屬間化合物IMC1的厚度T1與凸塊結構122的厚度TB之總和為100％時，第一金屬間化合物IMC1的厚度T1在5％至20％（T1 /(T1+TB)）的範圍內。在某些實施例中，以第一金屬間化合物IMC1的厚度T1與凸塊結構122的厚度TB之總和為100％時，第一金屬間化合物IMC1的厚度T1在5％至10％（T1 /(T1+TB)）的範圍內。
類似地，以第二金屬間化合物IMC2的厚度T2與凸塊結構的厚度TB之總和為100％時，第二金屬間化合物IMC2的厚度T2在5％至20％（T2/(T2 +TB)）的範圍內。在某些實施例中，以第二金屬間化合物IMC2的厚度T2與凸塊結構的厚度TB之總和為100％時，第二金屬間化合物IMC2的厚度T2在5％至10％（T2 /(T2+TB)）的範圍內。
接著回到參考圖17A，在將凸塊結構122接合至第一導電特徵114和連接結構120E後，可形成底部填充結構124以填充內連線結構120與重分佈層RDL1之間的間隙。所述底部填充結構124覆蓋並圍繞連接結構120E、凸塊結構122和第一導電特徵114的第一主體部分114B。
參考圖18，可以執行與圖9至圖13中所示相同的步驟以形成覆蓋內連線結構120和穿孔118的絕緣包封體126'，以及形成在絕緣包封體126'上方的重分佈層128。在重佈線層128上方形成導電端子130並進行剝離和鋸切製程之後，可以完成根據本公開一些實施例的封裝結構PK4（或半導體裝置）。
在圖18的實施例中，由於第一導電特徵114和連接結構120E由第二材料（例如，鎳）所製成，由於第二材料（例如，鎳）的較低反應性，因此，連接結構120E和第一導電特徵114與凸塊結構122的接點將導致較少的金屬間化合物的形成。基於此，第一金屬間化合物IMC1和第二金屬間化合物IMC2的厚度可以控制在最小範圍內，其可以提高接點良率，同時可靠性問題會更少。
圖19至圖25是根據本公開的一些其他示例性實施例的製造封裝結構的方法中的各個階段的示意性剖面圖。參考圖19，提供了載體401。載體401可以是玻璃載體或是適合於承載半導體晶圓或用於封裝結構製造方法的重組晶圓的任何載體。在一些實施例中，內連線層或重分佈層402形成在載體401上方。在一些實施例中，可以在重分佈層402和載體401之間提供剝離層（未示出）以幫助在隨後的步驟中去除載體401。在載體401上方（或在剝離層上方）形成重分佈層402包括形成交替堆疊的多個介電層402A和多個導電元件402B。舉例來說，此處所描述的介電層402A和導電元件402B可以類似於圖11中所描述的介電層128A和導電元件128B，因此，不再予以贅述。
如圖19所示，在一些實施例中，可以在最頂部的介電層402A上方和介電層402A的開口內共形地形成晶種層（未示出）。 接著，可以在晶種層上方形成導電材料，由此將晶種層圖案化以形成晶種層404A、404B，並且將導電材料圖案化以形成第一導電特徵406和第二導電特徵408。此處形成的第一導電特徵406和第二導電特徵408可以類似於圖5中所描述的第一導電特徵114和第二導電特徵116。舉例來說，第一導電特徵406和第二導電特徵408可以包括第二材料（例如，鎳），其不同於導電元件402B的第一材料（例如，銅）。
在一些實施例中，第一導電特徵406可以包括第一通孔部分406A和第一主體部分406B。第一主體部分406B可以由第二材料（例如，鎳）形成，而第一通孔部分406A可以由第二材料（例如，鎳）或是不同於第二材料的材料（例如，銅）形成。類似地，第二導電特徵408包括第二通孔部分408A和第二主體部分408B。 第二主體部分408B可以由第二材料（例如，鎳）形成，而第二通孔部分408A可以由第二材料（例如，鎳）或是不同於第二材料的材料（例如，銅）形成。
參考圖20，多個穿孔410可以形成在第二導電特徵408上。舉例來說，穿孔410是設置在第二導電特徵408的第二主體部分408B上，並電性連接到第二導電特徵408的第二主體部分408B。在一些實施例中，穿孔410的形成包括形成具有開口的罩幕圖案（未示出），然後通過電鍍或沉積形成填充開口的金屬材料（未示出），並且去除罩幕圖案後形成穿孔410。在一些實施例中，穿孔410由第一材料所製成。例如，穿孔410可以包括諸如銅或銅合金或類似的金屬材料。
參考圖21，在隨後的步驟中，通過倒裝晶片結合（flip-chip bonding）將第一半導體晶粒106和第二半導體晶粒107接合到重分佈層402上。第一半導體晶粒106和第二半導體晶粒107的細節已經於圖2中進行描述，因此，不再予以贅述。在一些實施例中，第一半導體晶粒106和第二半導體晶粒107通過多個連接結構412和多個凸塊結構414接合到第一導電特徵406。舉例來說，連接結構412設置在導電柱（106D/107D）上，並且包括第二材料（例如，鎳），而凸塊結構414設置在連接結構412和第一導電特徵406之間，並且包括第三材料（例如，錫）。在一些實施例中，是執行回焊製程以將凸塊結構414接合到連接結構412和第一導電特徵406。在某些實施例中，在執行回焊製程以將凸塊結構414接合到連接結構412和第一導電特徵406之後，可以形成類似於圖8A中所描述的第一金屬間化合物IMC1和第二金屬間化合物IMC2（圖21中未示出）。
參考圖22，在將第一半導體晶粒106和第二半導體晶粒107放置在重分佈層402上方之後，可以形成底部填充結構416以填充晶粒（106/107）和重分佈層402之間的間隙。舉例來說，底部填充結構416覆蓋並圍繞連接結構412、凸塊結構414和第一導電特徵406的第一主體部分406B。底部填充結構416可以減少應力並保護由凸塊結構414回焊時引起的接點。底部填充結構416可以用液體或是半液體形式方式施加，然後隨後進行固化。
參考圖23，在隨後的步驟中，是形成絕緣包封體418以包封第一半導體晶粒106、第二半導體晶粒107和穿孔410。接著，可以執行平坦化步驟使得絕緣包封體418的頂表面418-TS可以與穿孔410的頂表面410-TS、第一半導體晶粒106的背側表面106-BS和第二半導體晶粒107的背側表面107-BS共面並齊平。在一些實施例中，是將多個導電端子420放置在穿孔410的底表面上。舉例來說，導電端子420通過穿孔410電性連接到第二導電特徵408。在一些實施例中，導電端子420例如被回焊以與穿孔410的頂表面410-TS結合。
參考圖24，在形成絕緣包封體418和導電端子420之後，是剝離載體401，以將重佈線層402與載體401分離。舉例來說，剝離製程包括將例如雷射或紫外（ultra-violet，UV）光等光投射在剝離層（未示出）上，以便可以容易地去除載體401。在去除載體401之後，可以暴露出重分佈層402的頂表面402-TS。
參考圖25，在一些實施例中，重新分佈層402的頂表面402-TS被圖案化以形成多個開口，以暴露出下方的導電元件402B。接著，可以在導電元件402B的最頂層的暴露的頂表面上設置多個導電接墊422。在某些實施例中，導電接墊422例如是用於球安置的球下金屬（under-ball metallurgy，UBM）圖案。如圖25所示，導電接墊422形成於重分佈層402上並電性連接至重分佈層402。在形成導電接墊422後，多個導電端子424是設置於導電接墊422上及位於重分佈層402上方。在一些實施例中，導電端子424可以通過植球製程或回焊製程而設置在導電接墊422上。在執行切割製程以分離單獨的封裝之後，完成了根據本公開的一些實施例的封裝結構PK5（或半導體裝置）。
在圖25的實施例中，由於第一導電特徵406和連接結構412由第二材料（例如，鎳）所製成，由於第二材料（例如鎳）的較低反應性，因此，連接結構412和第一導電特徵406與凸塊結構414的接點將導致較少的金屬間化合物的形成。基於此，第一金屬間化合物IMC1和第二金屬間化合物IMC2的厚度可以控制在最小範圍內，其可以提高接點良率，同時可靠性問題會更少。
根據上述的實施例，封裝結構包括凸塊結構，其用於提供連接結構與第一導電特徵之間的互連。由於連接結構和第一導電特徵由鎳材料所製成，由於鎳的較低反應性，連接結構和第一導電特徵與凸塊結構（例如焊料）的接點將導致較少的金屬間化合物的形成。因此，可以解決由於在接合期間形成較厚金屬間化合物而導致的凸塊結構的低接合率（low joint yield）和可靠性問題。整體而言，即使將凸塊結構的尺寸按比例縮小以滿足設計需求，凸塊結構的接點之間形成的金屬間化合物也可控制在最少，其可以提高封裝結構的可靠性。
根據本公開的一些實施例，封裝結構包括半導體晶粒、第一絕緣包封體、多個第一導電特徵、內連線結構和凸塊結構。半導體晶粒包括由第一材料製成的多個導電柱。第一絕緣包封體包封半導體晶粒。第一導電特徵設置在半導體晶粒上並且電性連接到導電柱。第一導電特徵至少包括不同於第一材料的第二材料。內連線結構設置在第一導電特徵上，其中內連線結構包括由第二材料製成的多個連接結構。凸塊結構將第一導電特徵電性連接到連接結構，其中凸塊結構包括不同於第一材料和第二材料的第三材料。
在一些實施例中，封裝結構，更包括第一金屬間化合物以及第二金屬間化合物。第一金屬間化合物夾置在多個第一導電特徵與凸塊結構之間，其中以第一金屬間化合物的厚度T1與凸塊結構的厚度TB的總和為100％時，第一金屬間化合物的厚度T1在5%到20%的範圍內。第二金屬間化合物夾置在多個連接結構與凸塊結構之間，其中以第二金屬間化合物的厚度T2與凸塊結構的厚度TB的總和為100％時，第二金屬間化合物的厚度T2在5%到20%的範圍內。在一些實施例中，第一金屬間化合物包括基於Au-Sn的金屬間化合物，且第二金屬間化合物包括基於Ni-Sn的金屬間化合物。在一些實施例中，多個第一導電特徵中的每一者包括第一通孔部分和第一主體部分，第一通孔部分連接到多個導電柱，第一主體部分設置在第一通孔部分上並連接到凸塊結構，且其中第一通孔部分由第一材料製成，而第一主體部分由第二材料製成。在一些實施例中，封裝結構更包括晶種層設置在第一通孔部分和第一主體部分之間。在一些實施例中，封裝結構更包括多個第二導電特徵以及多個穿孔。多個第二導電特徵設置在多個半導體晶粒上並電性連接到多個導電柱，其中多個第二導電特徵至少包括第二材料。多個穿孔設置在多個第二導電特徵上並電性連接到多個第二導電特徵，其中多個穿孔環繞局部矽內連線結構並由第一材料製成。在一些實施例中，封裝結構更包括第二絕緣包封體設置在第一絕緣包封體上，且包封局部矽內連線結構以及凸塊結構。在一些實施例中，第一材料為銅，所述第二材料為鎳，且所述第三材料為錫。
根據本公開的一些實施例，一種半導體裝置包括內連線結構、通孔、導電柱、重分佈層、凸塊結構和第一金屬間化合物。內連線結構包括多個連接結構。通孔圍繞內連線結構。導電柱電性連接至內連線結構和通孔。重佈線層配置於導電柱上並包括多個第一導電特徵與多個第二導電特徵，第一導電特徵將連接結構電性連接至導電柱，第二導電特徵將通孔電性連接至導電柱。凸塊結構設置在連接結構與第一導電特徵之間。第一金屬間化合物夾置在第一導電特徵與凸塊結構之間，其中以第一金屬間化合物的厚度T1與凸塊結構的厚度TB之總和為100%時，第一金屬間化合物的厚度T1在5%到20%的範圍內。
在一些實施例中，多個第一導電特徵中的每一者包括第一通孔部分和第一主體部分，第一通孔部分連接到導電柱，並且第一主體部分設置在第一通孔部分上並連接到凸塊結構。多個第二導電特徵中的每一者包括第二通孔部分和第二主體部分，第二通孔部分連接到導電柱，並且第二主體部分設置在第二通孔部分上並連接到穿孔。在一些實施例中，第一通孔部分和第一主體部分由不同材料所製成，且第二通孔部分和第二主體部分由不同材料所製成。在一些實施例中，半導體裝置更包括將第一通孔部分和第一主體部分物理性分離的晶種層，以及將第二通孔部分和第二主體部分物理性分離的第二晶種層。在一些實施例中，重佈線層更包括導電元件層設置於導電柱與多個第一導電特徵之間，且設置於導電柱與多個第二導電特徵之間，其中導電元件層的材料與多個第一導電特徵和多個第二導電特徵的材料不同。在一些實施例中，半導體裝置更包括絕緣包封體以及第二重分佈層。絕緣包封體環繞內連線結構、穿孔以及凸塊結構。第二重分佈層配置於絕緣包封體上並且與內連線結構以及穿孔電性連接。在一些實施例中，半導體裝置更包括金屬化層設置在穿孔和多個第二導電特徵之間，其中金屬化層包括貴金屬。
根據本公開的又一實施例，描述了一種製造封裝結構的方法。所述方法包括以下步驟。提供半導體晶粒，所述半導體晶粒包括由第一材料製成的多個導電柱。形成包封半導體晶粒的第一絕緣包封體。在半導體晶粒上形成多個第一導電特徵並電性連接到多個導電柱，其中多個第一導電特徵件至少包括與第一材料不同的第二材料。在多個第一導電特徵上提供內連線結構，其中內連線結構包括由第二材料製成的多個連接結構。在多個第一導電特徵和多個連接結構之間提供凸塊結構，並執行回焊製程，使得凸塊結構將多個第一導電特徵電性連接到多個連接結構，其中凸塊結構包括不同於第一材料和第二材料的第三材料。
在一些實施例中，在執行回焊製程後，第一金屬間化合物會形成於多個第一導電特徵與凸塊結構之間，其中以第一金屬間化合物的厚度T1與凸塊結構的厚度TB的總和為100％時，第一金屬間化合物的厚度T1在5%到20%的範圍內；以及第二金屬間化合物會形成於多個連接結構與凸塊結構之間，其中以第二金屬間化合物的厚度T2與凸塊結構的厚度TB的總和為100％時，第二金屬間化合物的厚度T2在5%到20%的範圍內。在一些實施例中，所述的方法更包括在提供凸塊結構之前在多個第一導電特徵上方形成金質層，其中在執行回焊製程以將凸塊結構接合到多個第一導電特徵之後，金質層將溶解使得基於Au-Sn的金屬間化合物形成為多個第一導電特徵與凸塊結構之間的第一金屬間化合物。在一些實施例中，所述的方法更包括在半導體晶粒上形成多個第二導電特徵並電性連接到多個導電柱，其中多個第二導電特徵至少包括第二材料；以及在多個第二導電特徵上形成多個穿孔，其中多個穿孔環繞內連線結構，且是由第一材料所製成。在一些實施例中，所述的方法更包括形成第二絕緣包封體配置在第一絕緣包封體上，且包封內連線結構與凸塊結構。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各態樣。熟習此項技術者應理解，他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，此種等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
102、401:載體 104:緩衝層 104A:剝離層 104B、110、120B、128A、210、402A:介電層 105:晶粒貼合膜 106:第一半導體晶粒 106A、107A:半導體基底 106B、107B、120D、128C、422:導電接墊 106C、107C:鈍化層 106D、107D:導電柱 106E、107E:保護層 106-BS、107-BS:背側表面 106-TS、107-TS、108-TS、118-TS、120-TS、126-TS、402-TS、410-TS、418-TS:頂表面 107:第二半導體晶粒 108、126:絕緣材料 108’、126’、418:絕緣包封體 112A、112B、212、404A、404B:晶種層 112A-1:第一部分 112A-2:第二部分 114、406:第一導電特徵 114A、406A:第一通孔部分 114B、406B:第一主體部分 116、408:第二導電特徵 116A、408A:第二通孔部分 116B、408B:第二主體部分 117:金屬化層 117’:金屬元素 118、410:穿孔 120:內連線結構 120A:基底 120C:基底穿孔 120E、412:連接結構 120F:銅層 122、414:凸塊結構 124、416:底部填充結構 128、402、RDL1:重分佈層 128B、402B:導電元件 130、420、424:導電端子 216:導電元件層 302:框架 304:膠帶 IMC1:第一金屬間化合物 IMC2:第二金屬間化合物 PK1、PK2、PK3、PK4、PK5:封裝結構 T1、T2、TB:厚度
當結合附圖閱讀時，從以下詳細描述可以最好地理解本公開的各個方面。需要注意的是，根據本行業中的標準慣例，各種特徵並未按比例繪製。 事實上，為使論述清晰起見，可以任意增加或減少各種特徵的尺寸。 圖1至圖13是根據本公開的一些示例性實施例的製造封裝結構的方法中的各個階段的示意性剖面圖。 圖14為根據本公開的其他實施例的封裝結構的示意性剖面圖。 圖15為根據本公開的其他實施例的封裝結構的示意性剖面圖。 圖16至圖18是根據本公開的一些其他示例性實施例的製造封裝結構的方法中的各個階段的示意性剖面圖。 圖19至圖25是根據本公開的一些其他示例性實施例的製造封裝結構的方法中的各個階段的示意性剖面圖。
114:第一導電特徵
114A:第一通孔部分
114B:第一主體部分
120E:連接結構
122:凸塊結構
IMC1:第一金屬間化合物
IMC2:第二金屬間化合物
T1、T2、TB:厚度

Claims (1)

  1. 一種封裝結構，包括： 多個半導體晶粒，其包括由第一材料製成的多個導電柱； 第一絕緣包封體，包封所述多個半導體晶粒； 多個第一導電特徵設置在所述多個半導體晶粒上且與所述多個導電柱電性連接，其中所述多個第一導電特徵包括與所述第一材料不同的第二材料； 局部矽內連線結構，設置在所述多個第一導電特徵上，其中所述局部矽內連線結構包括由所述第二材料製成的多個連接結構，且所述局部矽內連線結構用以提供所述多個半導體晶粒之間的電性連接；以及 凸塊結構，將所述多個第一導電特徵電性連接至所述多個連接結構，其中所述凸塊結構包括不同於所述第一材料和所述第二材料的第三材料。
TW111101496A 2021-08-19 2022-01-13 半導體裝置、封裝結構及其製備方法 TW202310270A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/407,172 US20230057113A1 (en) 2021-08-19 2021-08-19 Semiconductor device, package structure and method of fabricating the same
US17/407,172 2021-08-19

Publications (1)

Publication Number Publication Date
TW202310270A true TW202310270A (zh) 2023-03-01

Family

ID=84363566

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111101496A TW202310270A (zh) 2021-08-19 2022-01-13 半導體裝置、封裝結構及其製備方法

Country Status (3)

Country Link
US (2) US20230057113A1 (zh)
CN (1) CN115472578A (zh)
TW (1) TW202310270A (zh)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
TWI359714B (en) * 2008-11-25 2012-03-11 Univ Yuan Ze Method for inhibiting the formation of palladium-n
US9177926B2 (en) * 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US9087832B2 (en) * 2013-03-08 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage reduction and adhesion improvement of semiconductor die package
US10115703B2 (en) * 2015-03-17 2018-10-30 Toshiba Memory Corporation Semiconductor device and manufacturing method thereof
US10763206B2 (en) * 2017-10-30 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating integrated fan-out packages
US10522470B1 (en) * 2018-07-15 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of fabricating the same
US11127688B2 (en) * 2019-08-22 2021-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof

Also Published As

Publication number Publication date
CN115472578A (zh) 2022-12-13
US20240014162A1 (en) 2024-01-11
US20230057113A1 (en) 2023-02-23

Similar Documents

Publication Publication Date Title
US11901320B2 (en) Contact pad for semiconductor device
US20200381357A1 (en) Package structure and package-on-package structure
CN111799227B (zh) 半导体器件及其形成方法
US11502040B2 (en) Package structure and semiconductor pacakge
US11776905B2 (en) Package structure, package-on-package structure and manufacturing method thereof
US11145562B2 (en) Package structure and method of manufacturing the same
US11562983B2 (en) Package having multiple chips integrated therein and manufacturing method thereof
US11257787B2 (en) Package structure and method of fabricating the same
TW202010084A (zh) 半導體封裝及其製造方法
US20230116818A1 (en) Package having multiple chips integrated therein and manufacturing method thereof
US10438934B1 (en) Package-on-package structure and manufacturing method thereof
US20230369273A1 (en) Package structure
TWI713858B (zh) 積體電路封裝及其形成方法
TW202114088A (zh) 封裝結構
US20230057113A1 (en) Semiconductor device, package structure and method of fabricating the same
US11916025B2 (en) Device die and method for fabricating the same
US11862594B2 (en) Package structure with solder resist underlayer for warpage control and method of manufacturing the same
US20230420331A1 (en) Semiconductor package and method
US20230343764A1 (en) Package structure
US20220359468A1 (en) Semiconductor device and manufacturing method thereof