CN102194804A - 封装结构 - Google Patents
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Abstract
本发明揭示一种封装结构,包括:一第一芯片;一第二芯片接合至第一芯片上方,其中第二芯片的尺寸小于第一芯片的尺寸;以及一辅助芯片接合至第一芯片上方。辅助芯片包括一部分围绕第二芯片。辅助晶片包括一材料,其择自于实质上由硅及金属所组成的群组。本发明可轻易散出底层芯片及顶层芯片所产生的热,形成低应力,以及降低底层晶片破损的可能性。
Description
技术领域
本发明涉及一种集成电路的封装,尤其涉及一种使用辅助(dummy)晶片的三维集成电路(three-dimensional integrated circuit,3DIC)的封装。
背景技术
随着半导体技术的发展,半导体芯片变得越来越小且越来越薄。如此一来,半导体封装变得更为紧密。
封装技术可分为两类型。一类型通常称为芯片级封装(chip-levelpackaging),其中在进行封装之前,芯片从晶片进行切割。优点在于只有已知良品(known-good-die)进行封装。此封装技术的另一优点在于形成扇出(fan-out)式芯片封装的可能性,其意味着芯片上的I/O接合垫可重布于大于芯片的区域,故可增加芯片表面上封装形成的I/O接合垫数量。
在将芯片接合至一晶片之后,形成了包含芯片及晶片的结构,由于芯片的高度与芯片之间的间隙而使该结构具有不平坦的表面,造成进行后续工艺步骤的困难度,例如芯片切割。另外,晶片很薄,不平坦的表面加上相对较厚的芯片,芯片容易有发生破损的情形。
可将成型材料(molding compound)填入芯片之间的间隙来平坦化形成的封装结构。然而,通常成型材料的导热性低,导致三维集成电路的散热(heat-dissipating)能力低。此外,由于三维集成电路变得更为紧密而在其中产生更多的热,因而使散热成为严重的问题。
发明内容
为了解决现有技术的问题,在本发明一实施例中,提供一种封装结构,包括:一第一芯片;一第二芯片接合至第一芯片上方,其中第二芯片的尺寸小于第一芯片的尺寸;以及一辅助芯片接合至第一芯片上方。辅助芯片包括一部分围绕第二芯片。辅助晶片包括一材料,其择自于实质上由硅及金属所组成的群组。
本发明另一实施例中,一种封装结构,包括:一中介芯片,其内不具有集成电路装置;一芯片接合至中介芯片上方,其中芯片的平面尺寸小于中介芯片的平面尺寸;以及一辅助芯片,其内不具有集成电路装置,接合至中介芯片上方。辅助芯片包括一部分围绕芯片。辅助晶片包括一材料,其择自于实质上由硅及金属所组成的群组。
本发明可轻易散出底层芯片及顶层芯片所产生的热,形成低应力,以及降低底层晶片破损的可能性。
附图说明
图1至图6B示出根据一实施例的封装结构的中间工艺阶段剖面示意图、立体图及俯视图,其中在进行芯片对晶片工艺之后,辅助晶片接合至底层晶片。
图7至图10示出根据另一实施例的封装结构的中间工艺阶段剖面示意图,其中顶层芯片接合至辅助晶片,且形成的结构接合至底层晶片。
图11至图13示出根据又一实施例的封装结构。
图14至图23示出图11至图13的封装结构的中间工艺阶段剖面示意图。
其中,附图标记说明如下:
10~底层晶片;
10’~底层芯片;
10’b、24’b~外侧边缘;
12~承载晶片;
16~金属凸块;
18~顶层芯片;
18a~背表面;
19~凸块;
20、143、147~底胶;
24、150~辅助晶片;
24’、150’~辅助芯片;
24a~上表面;
26、154~开口;
30、128~粘着层;
32、156~导热材料;
34~金属柱体;
40~间隙;
110~中介晶片;
110’~中介芯片;
112~基底;
114、118、158~重布局线
116、152~基底通孔电极;
117、132、134~接合垫;
118’~金属垫;
119~焊料凸块/接合垫
132A、132B~部分;
142~电子部件;
146~芯片;
140、140’~焊料凸块;
160~蓝胶带;
D~深度;
D1~顶部直径;
D2~底部直径;
T~厚度。
具体实施方式
以下说明本发明实施例的制作与使用。然而,可轻易了解本发明实施例提供许多合适的发明概念而可实施于广泛的各种特定背景。所揭示的特定实施例仅仅用于说明以特定方法制作及使用本发明,并非用以局限本发明的范围。
以下说明一种新的封装结构及其制造方法。利用图示说明一制造实施例的中间制造阶段并详述实施例的差异性。在不同的实施例中,使用相同的标记来表示相同的部件。
请参照图1,一底层晶片10组装于一承载晶片12上。底层晶片10可包括集成电路(未示出),例如互补式金属氧化物半导体(complementarymetal-oxide-semiconductor,CMOS)晶体管、电容、电阻等等。承载晶片12可为玻璃晶片,而底层晶片10可通过,例如,紫外光固化胶(UV glue)(未示出)而组装于承载晶片12上。在另一实施例中,承载晶片12可由其他普遍使用的材料所构成,例如有机材料、陶瓷等等。底层晶片10内包括多个底层芯片(chip/die)10’。金属凸块(bump)16,例如铜凸块、焊料凸块等等,形成于底层晶片10的上侧。
图2示出芯片对晶片接合(die-to-wafer bonding),其中顶层芯片18可通过,例如,倒装芯片(flip chip)法而接合至底层晶片10上方。顶层芯片18的尺寸可小于底层晶片10的个别的底层芯片10’。另外,顶层芯片18内可包括集成电路(未示出),例如CMOS晶体管。顶层芯片18与底层晶片10之间的接合表示对焊料凸块进行回流(reflow),或是直接铜对铜接合,取决于金属凸块16及/或顶层芯片18上的凸块的类型。在进行接合工艺之后,底胶(underfill)20可填入顶层芯片18与底层晶片10的间隙。在一实施例中,底胶20是在进行如图3A所示工艺之前先行固化。另外,在进行如图3A所示工艺之前也可不进行固化工艺,而底胶20是在辅助(dummy)晶片24(未示出于图2,请参照图3A及图3B)组装于底层晶片10之后进行固化。
图3A及图3B分别示出辅助晶片24接合至底层晶片10上的立体图及剖面示意图。辅助晶片24包括多个开口26,每一开口26的尺寸与位置都对应至一个顶层芯片18。开口26可为贯穿开口,其自辅助晶片24的一侧穿透置一相对侧。辅助晶片24可具有良好的导热率,例如,其大于20W/m-℃。另外,辅助晶片24的导热率可等于或大于硅的导热率。辅助晶片24可为硅晶片、金属晶片或由任何其他导热材料所构成。辅助晶片24内并未形成有源(active)及/或无源(passive)集成电路装置,或实质上未形成有源及/或无源集成电路装置。辅助晶片24的接合包括在辅助晶片24的表面上涂覆粘着层30、将开口26对准于顶层芯片18以及将辅助晶片24贴合于底层晶片10上。接着可进行固化工艺以固化粘着层30。在本实施例中,底胶20不是在先前工艺步骤中进行固化,其可同时进行固化。粘着层30也可具有良好的导热率,例如大于10W/m-℃,甚至大于30W/m-℃。另外,粘着层30的导热率可等于或大于硅的导热率。粘着层30的材料可包括热介面材料(thermalinterface material,TIM)、铟等等。请参照图3B,在将辅助晶片24组装于底层晶片10上方之后,顶层芯片18置于开口26内,并通过开口26而露出顶层芯片18。
接下来,请参照图4A,导热材料32具有良好的导热率,例如,大于例如大于10W/m-℃,将其填入顶层芯片18与辅助晶片24之间的间隙,接着进行固化。在一实施例中,如图4A所示,顶层芯片18的背表面18a大体上切齐于辅助晶片24的上表面24a。在另一实施例中,如图4B所示,顶层芯片18的背表面18a低于辅助晶片24的上表面24a。因此,导热材料32可位于顶层芯片18的背表面18a上,使形成的三维集成电路结构(3DIC)具有平坦的上表面。
请参照图5,在辅助晶片24为辅助硅晶片的实施例中,可选择性地将金属柱体34形成于辅助晶片24内。形成金属柱体34包括:可通过蚀刻在辅助晶片24内形成开口以及在开口内填入金属材料,例如铜、钨、铝等等。所进行的蚀刻工艺使形成的金属柱体34的顶部直径D1大于底部直径D2。可在将辅助晶片24接合至底层晶片10上方之前或之后,进行金属柱体34的制作。金属柱体34可延伸至底层晶片10的热点(hot spot),其中热点为使用底层芯片10’(请参照图6A,其由切割底层晶片10所构成)期间产生过量的热的地方。另外,金属柱体34可平均地形成于辅助晶片24内。金属柱体34可延伸至与粘着层30接触而不穿透粘着层30。另外,金属柱体34也可与底层晶片10接触。
接着,可通过对UV胶进行UV光照射,将承载晶片12自底层晶片10卸离。将形成的封装结构(其为包括底层晶片10及顶层芯片18的集成电路晶片)切割承多个芯片,而图6A及图6B则分别示出其中一个芯片的剖面示意图及俯视图。每一芯片包括底层芯片10’及顶层芯片18。如图6B所示的俯视图,辅助芯片24’(其为辅助晶片24的分割部分)围绕顶层芯片18。另外,导热材料32也可围绕顶层芯片18。辅助芯片24’的外侧边缘24’b垂直对准底层芯片10’的外侧边缘10’b。
一散热片(heat sink)(未示出)可贴合至辅助芯片24’,也可与金属柱体34及辅助芯片24’直接接触或是经由热介面材料(TIM)而热耦接至金属柱体34、辅助芯片24’及顶层芯片18。因此,底层芯片10’所产生的热可因金属柱体34及辅助芯片24’具有高导热率而往上消散。因此,底层芯片10’与顶层芯片18均具有高导热率的散热路径。
图7至图9示出另一实施例。本实施例与后续实施例中相同于前述实施例的部件使用相同的标记,且除非有特别指出,否则对应的材料及工艺也可实质上相同于前述的实施例。请参照图7,底层晶片10组装于承载晶片12上,接着以底胶20覆盖金属凸块16。
请参照图8,提供一辅助晶片24,其内形成了多个开口26。开口26仅局部穿过辅助晶片24。换句话说,开口26的深度D小于辅助晶片24的厚度T。开口的深度D可接近于后续接合的顶层芯片18(未示出于图8,请参照图9)的厚度。接着,在辅助晶片24上涂覆一导热材料32,其可为粘着剂。
接下来,请参照图9,通过导热材料32,顶层芯片18放置且固定于开口26内,而顶层芯片18的凸块19对准于底层晶片10(请参照图7)内的金属凸块16的所在位置。在固定顶层芯片18之后,凸块19可微微高于辅助晶片24的上表面24a。请参照图10,顶层芯片18及辅助晶片24组装于底层晶片10上,其中接合工艺可包括焊料凸块的回流或是直接铜对铜接合,取决于金属凸块16及/或凸块19的类型。另外,可进行固化工艺以固化底胶20及导热材料32。
在形成的结构中,顶层芯片18与开口26的侧壁之间的间隙可局部填入底胶20(其在将辅助晶片24组装于底层晶片10上方时,被挤压至间隙内)。然而,间隙40(其为未被填满的开口26)仍可维持净空。
在后续工艺步骤中,金属柱体34(请参照图5、图6A、图6B)可选择性地形成于辅助晶片24内且延伸至底层晶片10的热点,接着去除承载晶片12以及切割所形成的封装结构。一散热片(未示出)也可贴合至所形成的封装结构中的辅助芯片24’。详细的工艺已如图5及图6A所示,在此不再赘述。
图11示出根据另一实施例的封装结构。在本实施例中,顶层芯片18接合至中介(interposer)芯片110’,其可为已从晶片切割后的分离芯片或是未切割的晶片的一部分。同样施加底胶147。辅助芯片24’包括围绕顶层芯片18的一部分。在一实施例中,如图11所示,辅助芯片24’还包括一薄层位于顶层芯片18正上方。在另一实施例中,顶层芯片18正上方没有辅助芯片24’的薄层,而顶层芯片18位于辅助芯片24’的贯穿开口内,其中贯穿开口如图3A的开口26所示。
中介芯片110’实质上不具有集成电路装置,集成电路装置包括有源装置(例如,晶体管)及无源装置(例如,电容及电阻)。换句话说,中介芯片110’包括连接器,例如金属线、介层窗(via)、接合垫,但未使用于形成集成电路装置。中介芯片110’包括基底112,其可由半导体材料所构成,例如硅或介电材料。金属线及介层窗114形成于中介芯片110’内,以作为重布局线(redistribution line,RDL),其中重布局线(RDL)114可包括形成于多个介电层内的多个膜层。另外,基底通孔电极(through substrate via,TSV)116可形成于基底112内。
中介芯片110’与顶层芯片18接合,举例来说,通过焊料凸块119来进行接合。另外,也可使用直接金属对金属接合法。因此,重布局线114电性连接至顶层芯片18内的装置。导热材料32填入顶层芯片18与辅助芯片24’之间的空间。底胶20可填入顶层芯片18与中介芯片110’之间的空间,以保护接合结构。
辅助芯片24’进一步接合至中介芯片110’。在一实施例中,粘着层128用以将辅助芯片24’连接至中介芯片110’。在其他实施例中,辅助芯片24’通过接合垫而与中介芯片110’接合,其示出于图12A、图12B、图12C。请参照图12B,其为辅助芯片24’的底视图,接合垫132形成于辅助芯片24’的表面(即,面对图11及图12A中中介芯片110’的表面)。在一实施例中,接合垫132为一环型物,然而其也可为分离成多个部分的环型物。接合垫132(如图12A所示)可包括二部分132A及132B。部分132A比部分132B更突出于辅助芯片24’的表面。相似地,图12C为中介芯片110’的俯视图,其中接合垫134形成于中介芯片110’的表面上。虽然图12B及图12C仅分别示出一接合垫环132及一接合垫环134,然而可形成更多的接合垫环或分离的接合垫。接合垫132及134可为辅助接合垫而未电性连接至顶层芯片18及芯片14内的任何装置。
图12A示出具有辅助芯片24’接合至中介芯片110’的结构的剖面示意图。在一实施例中,接合垫132及134为金属接合垫,且接合法可为值接金属对金属接合法。因此,接合垫132的突出部分132A接合至接合垫134。在其他实施例中,焊料(未示出)可接合垫132及134,其中焊料可为共晶(eutectic)焊料。在另外的实施例中,接合垫132及134由氧化物所构成且通过氧化物对氧化物接合法来进行接合。可以理解的是接合垫134可具有图12B中所示的接合垫132的剖面外型,而接合垫132可具有图12C中所示的接合垫134的剖面外型。
请再参照图11,重布局线118可形成于基底112的底侧,因而重布局线114及118位于基底112的二相对侧。虽然仅示出一层重布局线118,然而重布局线118可包括多个膜层。焊料凸块114形成于中介芯片110’的下表面且电性耦接至基底通孔电极116、重布局线114及118及/或顶层芯片18。另外,焊料凸块140可用于将中介芯片110’接合至一额外的电子部件142,其可为封装基底、印刷电路板(printed circuit board,PCB)等等。底胶143可填入电子部件142与中介芯片110’之间的空间,以保护接合结构。
在一实施例中,芯片146(也称作第二层叠(second-tier)芯片,而顶层芯片18也称作第一层叠芯片)也接合至中介芯片110’,其中顶层芯片18及芯片146位于中介芯片110’的二相对侧。芯片146可通过中介芯片110’内的连接器而电性耦接至顶层芯片18及焊料凸块140。顶层芯片18及芯片146可为不同类型的芯片。举例来说,顶层芯片18可为逻辑芯片,例如中央演算单元(central computing unit,CPU)芯片,而芯片146可为存储器芯片。芯片146相对薄于焊料凸块140的外观尺寸,使芯片146可合适地位于电子部件142与中介芯片110’之间的空间。
图13示出另一实施例,除了一额外辅助芯片150’接合至中介芯片110’且位于中介芯片110’与焊料凸块140之间外,本实施例相似于图11所示的实施例。辅助芯片150’上不包括集成电路装置,例如晶体管、电阻及电容。电性连接器,例如基底通孔电极152形成于辅助芯片150’内,且可通过基底通孔电极116电性连接至芯片146及/或顶层芯片18。在本实施例中,辅助芯片150’包括开154,其中芯片146及导热材料156位于其中。将辅助芯片150’接合至中介芯片110’的接合法可相似于图8至图10或是图12A至图12C所示的方法。
请参照图11,由于存在芯片146,中介芯片110’有一部分的底表面无法用于形成焊料凸块140。然而,在图13所示的实施例中,由于一些焊料凸块140(也标示为140’)可形成于芯片146正下方,因此可形成更多的焊料凸块140。举例来说,可通过形成一或多个重布局线158以从焊料凸块14’进行布线连接至基底通孔电极152。
图14至图22示出形成图11的结构的工艺流程。为了简化附图,图11所示结构的细节部分可不示出于图14至图22中。请参照图14,提供中介晶片110的基底112,而基底通孔电极116形成于基底112内。接着重布局线114形成于基底112上方且电性连接至基底通孔电极116。另外,凸块或接合垫117形成于中介晶片110的表面,其中凸块/接合垫117可为焊料凸块或金属凸块,例如铜凸块,其可进一步被镍层(未示出)所覆盖。接合垫134(未示出,如图12A及图12C所示)可形成于中介晶片110的表面。
接下来,请参照图15,顶层芯片18接合至中介晶片110,接着施加底胶20。再将辅助晶片24接合至中介晶片110,如图16所示。辅助晶片24内的开口以提供顶层芯片18之用,且可填入适量的导热材料32。另外,开口可为贯穿开口,其相似于图3A及图3B所示的开口26。将辅助晶片24接合至中介晶片110实质上相同于将辅助晶片24接合至底层晶片10(如图1至图10所示),因而此处不再赘述。另外,接合方法如图12A至图12C所示。
请参照图17,将图16的结构颠倒翻转,且对基底112进行薄化(研磨)工艺而露出基底通孔电极116。图18至图19示出重布局线118(其包括金属垫118’)与凸块/接合垫119(如图19所示)的制作。如熟知的技术般,重布局线118与凸块/接合垫119的制作包括形成金属垫、形成介电层,例如聚酰亚胺(polyimide)层位于金属垫上方(未示出)、在介电层(未示出)内形成开口以露出金属垫、在开口内形成底层凸块金属化(under-bumpmetallurgy,UBM)层(未示出)并与金属垫接触以及在底层凸块金属化层上形成凸块/接合垫119。另外,如熟知的技术般,凸块/接合垫119可为焊料凸块或其他类型的金属凸块,例如铜凸块,其中可形成镍层来覆盖铜凸块。
请参照图20,将芯片146接合至中介晶片110,且将底胶147施加于芯片146与中介晶片110之间的空间。接着在凸块/接合垫119上形成焊料凸块140,如图21所示。
请参照图22,将图21的结构贴上胶带。举例来说,将蓝胶带160贴至焊料凸块140。在一实施例中,辅助晶片24从上表面研磨至一适当厚度,而研磨之后,可露出或不露出导热材料32。在其他实施例中,并不进行研磨工艺。接着对形成结构进行切割,而每一芯片(如图11所示)包括:中介芯片110’(其为中介晶片110的一部分)、辅助芯片24’(其为辅助芯片24的一部分)及顶层芯片18,或还包括芯片146。
图13所示结构的形成步骤相似于图14至图22的实施例。初始步骤实质上相同于图14至图18所示。在形成图18所示的结构之后,辅助晶片150(辅助芯片150’为切割的辅助晶片150的一部分)可接合至中介晶片110。接着在辅助晶片150内形成基底通孔电极152并电性耦接至接合垫118。图23示出形成的结构。辅助晶片150包括放置裸片146的开口。重布局线158及焊料凸块140(请参照图13)的制作实质上相同于图21及图22图示,因而此处不再赘述。
可注意到辅助晶片24具有良好的导热率,因此可轻易散出底层芯片10’及顶层芯片18(请参照图6A)所产生的热。另外,当辅助晶片24由硅所构成,辅助晶片24的热膨胀系数(coefficient of thermal expansion,CTE)可相同于底层芯片10’及顶层芯片18的基底的热膨胀系数,因而在3DIC结构中形成低应力。另外,由于辅助晶片24、顶层芯片18及导热材料32构成了3DIC结构的平坦表面,因此即使底层晶片10很薄,仍可降低其破损的可能性。
虽然本发明已以优选实施例揭示如上,然其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可作更动、替代与润饰。另外,本发明的保护范围并未局限于说明书内所述特定实施例中的工艺、机器、制造、物质组成、装置、方法及步骤,任何本领域普通技术人员可从本发明揭示内容中理解现行或未来所发展出的工艺、机器、制造、物质组成、装置、方法及步骤,只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果均可使用于本发明中。因此,本发明的保护范围包括上述工艺、机器、制造、物质组成、装置、方法及步骤。另外,每一权利要求构成个别的实施例,且本发明的保护范围也包括各个权利要求及实施例的组合。
Claims (10)
1.一种封装结构,包括:
一第一芯片;
一第二芯片,接合至该第一芯片上方,其中该第二芯片的尺寸小于该第一芯片的尺寸;以及
一辅助芯片,接合至该第一芯片上方,其中该辅助芯片包括一部分围绕该第二芯片,且其中该辅助晶片包括一材料,其择自于实质上由硅及金属所组成的群组。
2.如权利要求1所述的封装结构,其中该辅助芯片为辅助硅芯片,且该封装结构还包括多个金属柱体,自该辅助芯片的一上表面延伸至一下表面。
3.如权利要求1所述的封装结构,其中该第一芯片为中介芯片而不具有有源装置,且该封装结构还包括一第三芯片,接合至该中介芯片,其中该第二芯片与该第三芯片位于该中介芯片的二相对侧。
4.如权利要求3所述的封装结构,还包括多个焊料凸块,位于该中介芯片的一表面上,其中所述多个焊料凸块与该第三芯片位于该中介芯片的相同侧。
5.如权利要求3所述的封装结构,还包括:
一辅助硅芯片,接合至该中介芯片,其中该辅助硅芯片与该第二芯片位于该中介芯片的二相对侧,且其中该辅助硅芯片包括一开口,且该第三芯片位于该开口内;以及
多个焊料凸块,位于该辅助硅芯片的一侧,且电性连接至该辅助硅芯片内的多个硅通孔电极,其中该中介芯片与所述多个焊料凸块位于该辅助硅芯片的二相对侧。
6.如权利要求1所述的封装结构,其中该辅助芯片包括一开口,其自该辅助芯片的一上表面延伸至一下表面,而该第二芯片置于该开口内。
7.如权利要求1所述的封装结构,其中该辅助芯片包括一开口,其自该辅助芯片的一下表面延伸至一中间处,其中该辅助芯片包括一部分覆盖该开口,且其中该第二芯片置于该开口内。
8.如权利要求1所述的封装结构,还包括一导热材料,平向地置于该辅助芯片与该第二芯片之间且与其接触。
9.一种封装结构,包括:
一中介芯片,其内不具有集成电路装置;
一第一芯片,接合至该中介芯片上方,其中该第一芯片的平面尺寸小于该中介芯片的平面尺寸;以及
一辅助芯片,其内不具有集成电路装置,接合至该中介芯片上方,其中该辅助芯片包括一部分,围绕该第一芯片,且其中该辅助晶片包括一材料,其择自于实质上由硅及金属所组成的群组。
10.如权利要求9所述的封装结构,还包括:
一第二芯片,接合至该中介芯片,其中该第一芯片与该第二芯片位于该中介芯片的二相对侧;
一辅助硅芯片,接合至该中介芯片,其中该辅助硅芯片与该第一芯片位于该中介芯片的二相对侧,且其中该辅助硅芯片包括一开口,而该第二芯片位于该开口内;
多个焊料凸块,位于该辅助硅芯片的一侧且电性连接至该辅助硅芯片内的多个硅通孔电极,其中该中介芯片与所述多个焊料凸块位于该辅助硅芯片的二相对侧;以及
一导热材料,填入于该开口中未被该第二芯片占据的剩余部分。
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TWI445155B (zh) * | 2011-01-06 | 2014-07-11 | Advanced Semiconductor Eng | 堆疊式封裝結構及其製造方法 |
US8269350B1 (en) * | 2011-05-31 | 2012-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing the switching noise on substrate with high grounding resistance |
US9082832B2 (en) | 2011-09-21 | 2015-07-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming protection and support structure for conductive interconnect structure |
US9484259B2 (en) * | 2011-09-21 | 2016-11-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming protection and support structure for conductive interconnect structure |
US9312214B2 (en) * | 2011-09-22 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages having polymer-containing substrates and methods of forming same |
US8872312B2 (en) * | 2011-09-30 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | EMI package and method for making same |
US10049964B2 (en) | 2012-03-23 | 2018-08-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units |
US9842798B2 (en) | 2012-03-23 | 2017-12-12 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a PoP device with embedded vertical interconnect units |
US8810024B2 (en) | 2012-03-23 | 2014-08-19 | Stats Chippac Ltd. | Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units |
US9837303B2 (en) | 2012-03-23 | 2017-12-05 | STATS ChipPAC Pte. Ltd. | Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units |
US20130277855A1 (en) * | 2012-04-24 | 2013-10-24 | Terry (Teckgyu) Kang | High density 3d package |
US8772946B2 (en) | 2012-06-08 | 2014-07-08 | Invensas Corporation | Reduced stress TSV and interposer structures |
US20140070405A1 (en) * | 2012-09-13 | 2014-03-13 | Globalfoundries Inc. | Stacked semiconductor devices with a glass window wafer having an engineered coefficient of thermal expansion and methods of making same |
CN104752491A (zh) * | 2013-12-30 | 2015-07-01 | 晟碟半导体(上海)有限公司 | 用于半导体装置的间隔体层和半导体装置 |
US9299677B2 (en) * | 2013-12-31 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with multiple plane I/O structure |
US20150262902A1 (en) | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
US9355997B2 (en) | 2014-03-12 | 2016-05-31 | Invensas Corporation | Integrated circuit assemblies with reinforcement frames, and methods of manufacture |
US9165793B1 (en) | 2014-05-02 | 2015-10-20 | Invensas Corporation | Making electrical components in handle wafers of integrated circuit packages |
US9741649B2 (en) | 2014-06-04 | 2017-08-22 | Invensas Corporation | Integrated interposer solutions for 2D and 3D IC packaging |
US9412806B2 (en) | 2014-06-13 | 2016-08-09 | Invensas Corporation | Making multilayer 3D capacitors using arrays of upstanding rods or ridges |
US9252127B1 (en) | 2014-07-10 | 2016-02-02 | Invensas Corporation | Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture |
KR101672622B1 (ko) | 2015-02-09 | 2016-11-03 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US9478504B1 (en) * | 2015-06-19 | 2016-10-25 | Invensas Corporation | Microelectronic assemblies with cavities, and methods of fabrication |
US10141288B2 (en) | 2015-07-31 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Surface mount device/integrated passive device on package or device structure and methods of forming |
US9847320B2 (en) * | 2016-03-09 | 2017-12-19 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method of fabricating the same |
US9922964B1 (en) * | 2016-09-19 | 2018-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure with dummy die |
US9865567B1 (en) * | 2017-02-02 | 2018-01-09 | Xilinx, Inc. | Heterogeneous integration of integrated circuit device and companion device |
US10483187B2 (en) * | 2017-06-30 | 2019-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heat spreading device and method |
US11488880B2 (en) * | 2017-06-30 | 2022-11-01 | Intel Corporation | Enclosure for an electronic component |
KR102018616B1 (ko) * | 2017-07-04 | 2019-09-06 | 삼성전자주식회사 | 반도체 장치 |
KR102077455B1 (ko) * | 2017-07-04 | 2020-02-14 | 삼성전자주식회사 | 반도체 장치 |
US10568202B2 (en) | 2017-07-25 | 2020-02-18 | International Business Machines Corporation | Tamper-respondent assembly with interconnect characteristic(s) obscuring circuit layout |
KR101901711B1 (ko) | 2017-09-27 | 2018-09-27 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
US10957672B2 (en) * | 2017-11-13 | 2021-03-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of manufacturing the same |
US11004803B2 (en) * | 2018-07-02 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy dies for reducing warpage in packages |
KR20200017240A (ko) * | 2018-08-08 | 2020-02-18 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
JP7106753B2 (ja) | 2018-09-04 | 2022-07-26 | 中芯集成電路(寧波)有限公司 | ウェハレベルパッケージング方法及びパッケージング構造 |
KR102509644B1 (ko) * | 2018-11-20 | 2023-03-15 | 삼성전자주식회사 | 패키지 모듈 |
US10770430B1 (en) | 2019-03-22 | 2020-09-08 | Xilinx, Inc. | Package integration for memory devices |
US11901333B2 (en) * | 2019-10-08 | 2024-02-13 | Intel Corporation | No mold shelf package design and process flow for advanced package architectures |
US11127650B2 (en) | 2020-02-24 | 2021-09-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package including thermal dissipation element and method of manufacturing the same |
US11515268B2 (en) * | 2021-03-05 | 2022-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and manufacturing method thereof |
US11842946B2 (en) * | 2021-03-26 | 2023-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package having an encapsulant comprising conductive fillers and method of manufacture |
US20230139175A1 (en) * | 2021-11-01 | 2023-05-04 | Micron Technology, Inc. | Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same |
US20230139914A1 (en) * | 2021-11-01 | 2023-05-04 | Micron Technology, Inc. | Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6008536A (en) * | 1997-06-23 | 1999-12-28 | Lsi Logic Corporation | Grid array device package including advanced heat transfer mechanisms |
US6461891B1 (en) * | 1999-09-13 | 2002-10-08 | Intel Corporation | Method of constructing an electronic assembly having an indium thermal couple and an electronic assembly having an indium thermal couple |
US20040018667A1 (en) * | 2002-07-26 | 2004-01-29 | Haren Joshi | Method and apparatus for producing a silicon wafer chip package |
US20060163713A1 (en) * | 2005-01-25 | 2006-07-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US20080128916A1 (en) * | 2006-12-04 | 2008-06-05 | Nec Electronics Corporation | Semiconductor device including microstrip line and coplanar line |
Family Cites Families (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4323914A (en) * | 1979-02-01 | 1982-04-06 | International Business Machines Corporation | Heat transfer structure for integrated circuit package |
US4811082A (en) | 1986-11-12 | 1989-03-07 | International Business Machines Corporation | High performance integrated circuit packaging structure |
US4990462A (en) | 1989-04-12 | 1991-02-05 | Advanced Micro Devices, Inc. | Method for coplanar integration of semiconductor ic devices |
US5075253A (en) | 1989-04-12 | 1991-12-24 | Advanced Micro Devices, Inc. | Method of coplanar integration of semiconductor IC devices |
US5380681A (en) | 1994-03-21 | 1995-01-10 | United Microelectronics Corporation | Three-dimensional multichip package and methods of fabricating |
US6002177A (en) | 1995-12-27 | 1999-12-14 | International Business Machines Corporation | High density integrated circuit packaging with chip stacking and via interconnections |
US6213376B1 (en) | 1998-06-17 | 2001-04-10 | International Business Machines Corp. | Stacked chip process carrier |
US6281042B1 (en) | 1998-08-31 | 2001-08-28 | Micron Technology, Inc. | Structure and method for a high performance electronic packaging assembly |
US6271059B1 (en) | 1999-01-04 | 2001-08-07 | International Business Machines Corporation | Chip interconnection structure using stub terminals |
US6461895B1 (en) | 1999-01-05 | 2002-10-08 | Intel Corporation | Process for making active interposer for high performance packaging applications |
US6229216B1 (en) | 1999-01-11 | 2001-05-08 | Intel Corporation | Silicon interposer and multi-chip-module (MCM) with through substrate vias |
US6243272B1 (en) | 1999-06-18 | 2001-06-05 | Intel Corporation | Method and apparatus for interconnecting multiple devices on a circuit board |
US6355501B1 (en) | 2000-09-21 | 2002-03-12 | International Business Machines Corporation | Three-dimensional chip stacking assembly |
KR100364635B1 (ko) | 2001-02-09 | 2002-12-16 | 삼성전자 주식회사 | 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법 |
KR100394808B1 (ko) | 2001-07-19 | 2003-08-14 | 삼성전자주식회사 | 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법 |
KR100435813B1 (ko) | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법 |
DE10200399B4 (de) | 2002-01-08 | 2008-03-27 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung |
US6975016B2 (en) | 2002-02-06 | 2005-12-13 | Intel Corporation | Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof |
US6661085B2 (en) | 2002-02-06 | 2003-12-09 | Intel Corporation | Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack |
US6887769B2 (en) | 2002-02-06 | 2005-05-03 | Intel Corporation | Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same |
US6762076B2 (en) | 2002-02-20 | 2004-07-13 | Intel Corporation | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
US6600222B1 (en) | 2002-07-17 | 2003-07-29 | Intel Corporation | Stacked microelectronic packages |
US6790748B2 (en) | 2002-12-19 | 2004-09-14 | Intel Corporation | Thinning techniques for wafer-to-wafer vertical stacks |
US6908565B2 (en) | 2002-12-24 | 2005-06-21 | Intel Corporation | Etch thinning techniques for wafer-to-wafer vertical stacks |
US6924551B2 (en) | 2003-05-28 | 2005-08-02 | Intel Corporation | Through silicon via, folded flex microelectronic package |
US6946384B2 (en) | 2003-06-06 | 2005-09-20 | Intel Corporation | Stacked device underfill and a method of fabrication |
TWI275168B (en) * | 2003-06-06 | 2007-03-01 | Sanyo Electric Co | Semiconductor device and method for making the same |
US7320928B2 (en) | 2003-06-20 | 2008-01-22 | Intel Corporation | Method of forming a stacked device filler |
KR100537892B1 (ko) | 2003-08-26 | 2005-12-21 | 삼성전자주식회사 | 칩 스택 패키지와 그 제조 방법 |
US6953990B2 (en) * | 2003-09-19 | 2005-10-11 | Agilent Technologies, Inc. | Wafer-level packaging of optoelectronic devices |
US7345350B2 (en) | 2003-09-23 | 2008-03-18 | Micron Technology, Inc. | Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias |
KR100621992B1 (ko) | 2003-11-19 | 2006-09-13 | 삼성전자주식회사 | 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지 |
KR100570514B1 (ko) | 2004-06-18 | 2006-04-13 | 삼성전자주식회사 | 웨이퍼 레벨 칩 스택 패키지 제조 방법 |
KR100618837B1 (ko) | 2004-06-22 | 2006-09-01 | 삼성전자주식회사 | 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법 |
US7307005B2 (en) | 2004-06-30 | 2007-12-11 | Intel Corporation | Wafer bonding with highly compliant plate having filler material enclosed hollow core |
US7242101B2 (en) * | 2004-07-19 | 2007-07-10 | St Assembly Test Services Ltd. | Integrated circuit die with pedestal |
US7087538B2 (en) | 2004-08-16 | 2006-08-08 | Intel Corporation | Method to fill the gap between coupled wafers |
US7897503B2 (en) * | 2005-05-12 | 2011-03-01 | The Board Of Trustees Of The University Of Arkansas | Infinitely stackable interconnect device and method |
US7317256B2 (en) | 2005-06-01 | 2008-01-08 | Intel Corporation | Electronic packaging including die with through silicon via |
US7557597B2 (en) | 2005-06-03 | 2009-07-07 | International Business Machines Corporation | Stacked chip security |
US7402515B2 (en) | 2005-06-28 | 2008-07-22 | Intel Corporation | Method of forming through-silicon vias with stress buffer collars and resulting devices |
US7432592B2 (en) | 2005-10-13 | 2008-10-07 | Intel Corporation | Integrated micro-channels for 3D through silicon architectures |
US7528494B2 (en) | 2005-11-03 | 2009-05-05 | International Business Machines Corporation | Accessible chip stack and process of manufacturing thereof |
US7410884B2 (en) | 2005-11-21 | 2008-08-12 | Intel Corporation | 3D integrated circuits using thick metal for backside connections and offset bumps |
US7402442B2 (en) | 2005-12-21 | 2008-07-22 | International Business Machines Corporation | Physically highly secure multi-chip assembly |
US7279795B2 (en) | 2005-12-29 | 2007-10-09 | Intel Corporation | Stacked die semiconductor package |
JP4332567B2 (ja) * | 2007-03-27 | 2009-09-16 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法及び実装方法 |
US7576435B2 (en) | 2007-04-27 | 2009-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-cost and ultra-fine integrated circuit packaging technique |
TWI335059B (en) * | 2007-07-31 | 2010-12-21 | Siliconware Precision Industries Co Ltd | Multi-chip stack structure having silicon channel and method for fabricating the same |
KR101213175B1 (ko) | 2007-08-20 | 2012-12-18 | 삼성전자주식회사 | 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지 |
US7772691B2 (en) | 2007-10-12 | 2010-08-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermally enhanced wafer level package |
TWI372434B (en) * | 2008-01-30 | 2012-09-11 | Advanced Semiconductor Eng | Temperature cycle test apparatus and method for heating flip chip structure using the same |
US7951647B2 (en) | 2008-06-17 | 2011-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Performing die-to-wafer stacking by filling gaps between dies |
KR20100046760A (ko) * | 2008-10-28 | 2010-05-07 | 삼성전자주식회사 | 반도체 패키지 |
-
2010
- 2010-03-04 US US12/717,779 patent/US8378480B2/en active Active
- 2010-07-27 TW TW099124660A patent/TWI415236B/zh active
- 2010-08-13 CN CN201010254670.8A patent/CN102194804B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6008536A (en) * | 1997-06-23 | 1999-12-28 | Lsi Logic Corporation | Grid array device package including advanced heat transfer mechanisms |
US6461891B1 (en) * | 1999-09-13 | 2002-10-08 | Intel Corporation | Method of constructing an electronic assembly having an indium thermal couple and an electronic assembly having an indium thermal couple |
US20040018667A1 (en) * | 2002-07-26 | 2004-01-29 | Haren Joshi | Method and apparatus for producing a silicon wafer chip package |
US20060163713A1 (en) * | 2005-01-25 | 2006-07-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US20080128916A1 (en) * | 2006-12-04 | 2008-06-05 | Nec Electronics Corporation | Semiconductor device including microstrip line and coplanar line |
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103117279A (zh) * | 2011-11-16 | 2013-05-22 | 台湾积体电路制造股份有限公司 | 形成芯片在晶圆的总成的方法 |
CN103117279B (zh) * | 2011-11-16 | 2016-10-05 | 台湾积体电路制造股份有限公司 | 形成芯片在晶圆的总成的方法 |
CN108257877A (zh) * | 2012-03-23 | 2018-07-06 | 新科金朋有限公司 | 形成扇出封装体叠层器件的半导体方法和器件 |
CN108257877B (zh) * | 2012-03-23 | 2022-04-26 | 星科金朋私人有限公司 | 形成扇出封装体叠层器件的半导体方法和器件 |
CN103681542A (zh) * | 2012-09-04 | 2014-03-26 | 英飞凌科技股份有限公司 | 芯片封装和用于制作芯片封装的方法 |
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CN105280575A (zh) * | 2014-07-17 | 2016-01-27 | 联华电子股份有限公司 | 半导体封装结构及其制造方法 |
US9613931B2 (en) | 2015-04-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out stacked system in package (SIP) having dummy dies and methods of making the same |
US11417580B2 (en) | 2016-11-14 | 2022-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US10770365B2 (en) | 2016-11-14 | 2020-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US11527454B2 (en) | 2016-11-14 | 2022-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
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CN108074828A (zh) * | 2016-11-14 | 2018-05-25 | 台湾积体电路制造股份有限公司 | 封装结构及其形成方法 |
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US10867965B2 (en) | 2016-11-14 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
CN107993994B (zh) * | 2017-12-29 | 2023-07-25 | 长鑫存储技术有限公司 | 半导体封装结构及其制造方法 |
CN107993994A (zh) * | 2017-12-29 | 2018-05-04 | 睿力集成电路有限公司 | 半导体封装结构及其制造方法 |
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US11798914B2 (en) | 2019-10-12 | 2023-10-24 | Yangtze Memory Technologies Co., Ltd. | Methods and structures for die-to-die bonding |
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US20110215470A1 (en) | 2011-09-08 |
US8378480B2 (en) | 2013-02-19 |
TWI415236B (zh) | 2013-11-11 |
CN102194804B (zh) | 2016-01-20 |
TW201131715A (en) | 2011-09-16 |
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