WO2021114410A1 - 一种用于系统散热的封装结构及其封装工艺 - Google Patents

一种用于系统散热的封装结构及其封装工艺 Download PDF

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Publication number
WO2021114410A1
WO2021114410A1 PCT/CN2019/128945 CN2019128945W WO2021114410A1 WO 2021114410 A1 WO2021114410 A1 WO 2021114410A1 CN 2019128945 W CN2019128945 W CN 2019128945W WO 2021114410 A1 WO2021114410 A1 WO 2021114410A1
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chip
heat dissipation
active
active chip
tsv
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PCT/CN2019/128945
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English (en)
French (fr)
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孙鹏
徐成
任玉龙
曹立强
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上海先方半导体有限公司
华进半导体封装先导技术研发中心有限公司
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Publication of WO2021114410A1 publication Critical patent/WO2021114410A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • This application relates to the field of chip packaging, in particular to a packaging structure for system heat dissipation and its packaging process.
  • the traditional main path of chip heat dissipation includes two aspects, one is the back of the chip package, and the other is the PCB board.
  • heat dissipation is mainly carried out by adding a heat dissipation cover on the package surface, improving the thermal conductivity of the thermal interface material, adding forced cooling and other active heat dissipation structures, and improving the design of the package substrate. Without increasing the active heat dissipation structure, most of the heat is actually exported through the PCB board, which is mainly for products with low power consumption.
  • the main heat dissipation path has become a path such as the back of the chip-the heat sink-the air.
  • the active heat dissipation method is to add an active heat dissipation structure on the back of the packaged chip, so that the heat on the back surface of the packaged chip can be transferred to the active heat dissipation structure more quickly, and then the heat on the backside is discharged more quickly to achieve better Heat dissipation capabilities, such as increasing micro-channel heat dissipation, only increase the heat dissipation speed on the back surface of the packaged chip, and cannot fundamentally effectively improve the problems of excessive heat flow density and too small heat dissipation paths inside the package. Therefore, the use of traditional heat dissipation methods cannot improve the internal heat flow density of the packaged chip and the heat dissipation path is too small. In the face of high-power products, especially products with high system integration, traditional heat dissipation methods often cannot meet the heat dissipation requirements. .
  • a package structure for system heat dissipation including:
  • Memory chip mounted on the active chip
  • a heat conductor, the heat conductor and the memory chip are both mounted on the same surface of the active chip, and the heat conductor has a second TSV interconnected with the active chip;
  • the package body encapsulates the active chip, the memory chip and the heat conductor on a substrate, one end of the second TSV on the heat conductor is interconnected with the active chip, and the other end of the second TSV is exposed on the surface of the package body.
  • the back side of the active chip is mounted on the substrate, and the first TSV is arranged on the active chip; the memory chip and the heat conductor are both mounted on the front side of the active chip.
  • the second TSV is arranged in parallel with the first TSV.
  • the second TSV is provided with a metal heat conductor; the material of the heat conductor is silicon or glass.
  • BGA balls on the surface of the substrate opposite to the active chip.
  • the package body includes a first package body that seals the memory chip and the heat conductor on the front surface of the active chip, and a second package body located between the active chip and the substrate.
  • the second package body realizes the gap between the active chip and the substrate. Filling of gaps.
  • the height of the heat conductor is higher than the height of the memory chip.
  • a manufacturing process of a package structure for system heat dissipation including:
  • the plastic-encapsulated active chip is cut into a single module, the single module is mounted on the substrate, and finally the underfill between the active chip and the substrate is completed to form a second package body.
  • a manufacturing process of a package structure for system heat dissipation includes:
  • Wafer-level plastic encapsulation is performed on the front surface of the active chip, and after the plastic encapsulation, a first package body encapsulating both the thermal conductor and the memory chip is formed;
  • wafer cutting is performed to form a single module, and the single module is mounted on the substrate to complete the underfill between the active chip and the substrate to form a second package;
  • a ball planting operation is performed on the substrate to form BGA balls.
  • the height of the heat conductor is higher than the height of the memory chip.
  • the second TSV is filled with a metal medium; the material of the heat conductor is silicon or glass.
  • the third is to improve the heat dissipation performance, that is, increase the surface of the package.
  • the thermal conductivity of the structure In the prior art, based on structural limitations, the heat dissipation performance of the product is usually improved from the thermal conductivity of the material itself; for example, the use of high thermal conductivity plastic packaging materials and thermal conductive glue can improve heat dissipation to a certain extent, but The limitation of the material itself cannot greatly improve the heat dissipation performance.
  • the heat on the active chip can be effectively transferred to the package through the thermal conductor with minimal thermal resistance.
  • the surface expands the heat dissipation path of the package structure itself, thereby improving the heat dissipation performance; considering the overall stress of the package, the heat conductor in this application is made of a material that matches the material of the surrounding chip in terms of thermal expansion coefficient, such as silicon or glass; at the same time; Since a large amount of silicon or glass material is added to the plastic packaging area of the memory chip, the package thermal resistance of the memory chip is also greatly reduced, which further significantly expands the heat dissipation path of the package structure, and significantly improves the heat dissipation performance of the present application.
  • This application further optimizes the structure of the active chip. Specifically, by providing the first TSV on the active chip, the interconnection between the back of the active chip and the substrate can be realized in this setting mode, and the It is possible to mount a memory chip on the front side of the source chip. That is, in this application, by adding the first TSV, the memory chip can be mounted on the front side of the active chip, thereby realizing the shortest interconnection between the active chip and the memory chip. Therefore, the electrical performance can be effectively improved; and the electrical performance can be improved. At the same time, through the shortest interconnection between the active chip and the memory chip, the heat of the memory chip can be effectively transferred to the active chip with good thermal conductivity and larger area.
  • the connected heat conductor can transfer the heat from the memory chip to the package surface with minimum thermal resistance, and the heat dissipation path inside the package chip is enlarged by the heat conductor, thereby effectively dissipating the heat from the active chip, and significantly improving the heat dissipation performance; Moreover, due to the addition of TSV holes, the heat transfer performance in the vertical direction can be improved, and the purpose of heat dissipation can be better achieved.
  • This application provides a packaging process for a package structure for system heat dissipation. In this process step, only two packages are required to complete the preparation of the finished product, which can increase heat conduction to improve the heat dissipation performance during the packaging process.
  • the package structure greatly improves the flexibility of the packaged product, that is, in the subsequent program design process of using the package structure of the present application, active and passive heat dissipation devices such as heat dissipation covers, heat sinks, etc. can be flexibly added to the package structure of the present application as needed;
  • the packaging process of the present application is suitable for wafer-level packaging, with high manufacturability, high packaging efficiency, and simple operation.
  • FIG. 1 is a schematic diagram of a package structure used for system heat dissipation in this application.
  • Figure 2 is a flow chart of the packaging process of this application.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • the specific meanings of the above terms in this application can be understood under specific circumstances.
  • a package structure for system heat dissipation includes: a substrate 1, an active chip 2, a memory chip 3, a heat conductor 4, and a package body 5; wherein, the active chip 2 is mounted on the substrate 1
  • the memory chip 3 is mounted on the active chip 2; the thermal conductor 4 and the memory chip 3 are mounted on the same surface of the active chip 2, and the thermal conductor 4 has an interconnection with the active chip 2
  • the second TSV; the package body 5 encapsulates the active chip 2, the memory chip 3 and the heat conductor 4 on the substrate 1.
  • One end of the second TSV on the heat conductor 4 is interconnected with the active chip 2, and the other end of the second TSV is at The surface of the package 5 is exposed.
  • the heat on the memory chip 3 can be introduced to the active chip 2, and then the heat on the active chip 2 can be exported to the air through the second TSV through the heat conductor 4, which enlarges
  • the heat conduction path of the chip in the package structure significantly improves the thermal conductivity.
  • the heat conductor 4 occupies a large amount of the volume of the package body 5, the thermal resistance of the package body 5 is effectively reduced, and the efficiency of heat dissipation into the air through the package body 5 is further improved.
  • the active chip 2 can cover multiple types of digital chips such as ASIC, CPU, GPU, FPGA, etc.
  • the characteristic of this type of chip is high power consumption;
  • the memory chip 3 is an HBM chip, and the nature of the HBM chip is relatively simple. Dynamic memory.
  • the memory chip 3 is mounted on the front side of the active chip 2, the back side of the active chip 2 is mounted on the substrate 1, and the active chip 2 is connected to the substrate 1 through leads.
  • the leads can be wound around If the active chip 2 is connected to the substrate 1, the first TSV may also be provided on the active chip 2, and the first TSV on the active chip 2 is connected to the substrate 1.
  • the active chip 2 with the first TSV is selected and communicates with the substrate 1 through the first TSV.
  • the back of the active chip 2 is mounted on the substrate 1
  • the memory chip 3 and the heat conductor 4 are both mounted on the front of the active chip 2
  • the active chip 2 is connected to the substrate 1 through the first TSV .
  • the shortest interconnection method combined with the first TSV provided on the active chip 2 can effectively provide another heat dissipation path for the active chip 2 to effectively conduct the heat of the active chip 2 to the substrate 1, and the substrate 1 Heat dissipation improves heat dissipation performance.
  • the first TSV and the second TSV are both through-silicon vias.
  • each component is also optimized in this application, such as: arranging the second TSV in parallel with the first TSV to effectively improve the heat transfer performance in the vertical direction;
  • the second TSV is filled with a metal medium, that is, the second TSV is provided with a metal heat-conducting member, which effectively improves the thermal conductivity;
  • a BGA ball 6 is provided on the surface of the substrate 1 opposite to the active chip 2, and the BGA ball 6 can be used The heat transferred from the chip to the substrate 1 through the wire is effectively transferred to other carrying materials, and the heat dissipation performance is improved.
  • the package 5 includes a first package that seals the memory chip 3 and the heat conductor 4 on the front surface of the active chip 2, and is located between the active chip 2 and the substrate 1 and realizes a gap between the active chip 2 and the substrate 1.
  • the height of the heat conductor 4 is higher than the height of the memory chip 3, which can simplify the manufacturing process.
  • This embodiment provides a packaging process for a packaging structure for system heat dissipation, as shown in FIG. 2, and the specific process is as follows:
  • Step 1 Mount the memory chip 3 and the heat conductor 4 with the second TSV on the same side of the active chip 2.
  • the memory chip 3 is first mounted on the active chip 2 and then the heat conductor 4 is mounted on the active chip 2.
  • the memory chip 3 can be mounted on the front of the active chip 2 or on the back of the active chip 2; when mounted on the back, the active chip 2 and the memory chip 3 can be interconnected by wires; On the front side, the back of the memory chip 3 can be mounted on the front side of the active chip 2. At this time, the memory chip 3 can be interconnected with the active chip 2 through wires, or the memory chip 3 can be mounted on the active chip 2 on the front side.
  • the shortest interconnection between the active chip 2 and the active chip 2 can be effectively realized.
  • the front side of the active chip 2 and the front side of the memory chip 3 are mounted on each other to effectively realize the shortest interconnection between the memory chip 3 and the active chip 2.
  • the heat conductor 4 is distributed around the memory chip 3 and mounted on the front surface of the active chip 2, as shown in FIG. 2.
  • the central axis of the second TSV on the heat conductor 4 is perpendicular to the front surface of the active chip 2 so that the heat in the chip can be better discharged into the air.
  • Step 2 Plastic packaging of the active chip 2 is performed, and after plastic packaging, a first package body in which both the heat conductor 4 and the memory chip 3 are packaged is formed.
  • the height of the heat conductor 4 is set to be higher than that of the memory chip 3.
  • the plastic encapsulation in this step can be a wafer-level plastic encapsulation, and the heat conductor 4 and the memory chip 3 are all wrapped in the first package body.
  • the thermal conductor 4 is exposed by cutting and thinning. Without damaging the memory chip 3, the plastic packaging operation of multiple active chips 2 can be realized at the same time, and the operation is simpler and faster.
  • Step 3 Wafer cutting the plastic-encapsulated active chip 2 to form a single module, and set the back bump of the single module to facilitate the mounting of the single module on the substrate 1, as shown in FIG. 2. Finally, a single module is mounted on the substrate 1 to complete the underfill between the active chip 2 and the substrate 1 to form a second package.
  • the first package and the second package in the present application together constitute the package 5 in the present application.
  • a ball planting process can be performed on the other side of the substrate 1 to set the BGA balls 6.

Abstract

一种用于系统散热的封装结构，包括：基板（1）；有源芯片（2），其贴装在基板（1）上；内存芯片（3），其贴装在有源芯片（2）上；导热体（4），其与内存芯片（3）均贴装在有源芯片（2）的同一面上，该导热体（4）上具有与有源芯片（2）互连的第二TSV；封装体（5），其将有源芯片（2）、内存芯片（3）和导热体（4）封装在基板（1）上，导热体（4）上第二TSV的一端与有源芯片（2）互连，第二TSV的另一端在封装体（5）表面露出。该封装结构扩大了自身的散热路径，进而显著提高了散热性能。还涉及该封装结构的封装工艺。

Description

一种用于系统散热的封装结构及其封装工艺 技术领域
本申请涉及芯片封装领域，具体涉及一种用于系统散热的封装结构及其封装工艺。
背景技术
目前，芯片散热的传统主要路径包括两个方面，一个是芯片封装背面，另一个是PCB板。目前散热主要通过在封装表面增加散热盖、改善热界面材料热导率、增加强制制冷等主动散热结构，以及通过改善封装基板设计等等手段进行。在不增加主动散热结构的情况下，大部分的热量其实是通过PCB板导出的，这些这是主要面对一些低功耗的产品。在需要增加主动散热结构的产品中，主要的散热路径已变为芯片背面-散热片-空气这样的路径。
伴随着半导体工艺技术的持续提升、工艺节点不断缩小，导致芯片单位面积的功耗大幅提高；同时，随着3D堆叠技术在高端产品开始应用，多层芯片堆叠结构中存在热流密度过大、散热路径过小的问题，因此，如何散热将成为影响产品性能的关键之一。而现有技术中主动散热方式是在封装芯片的背面增加主动散热结构，促使封装芯片背部表面的热量能够更加快速地传递给主动散热结构，进而更加快速地将背面的热量排出，达到更好的散热能力，如：增加微流道散热等，其仅仅只是提高封装芯片背面表面的散热速度，并不能在根本上有效改善封装内部存在的热流密度过大、散热路径过小的问题。因此，采用传统散热方式存在无法改善封装芯片内部热流密度过大、散热路径过小的问题，在面对大功率产品，特别是系统集成度高的产品时，传统的散热方式往往不能满足散热需求。
发明内容
本申请要解决的技术问题在于：现有的传统散热方式无法改善封装芯片内部存在的热流密度过大、散热路径过小的问题；本申请提供了解决上述问题的一种用于系统散热的封装结构及其封装工艺。
一种用于系统散热的封装结构，包括：
基板；
有源芯片，贴装在基板上；
内存芯片，贴装在有源芯片上；
导热体，所述导热体与所述内存芯片均贴装在有源芯片的同一面上，所述导热体上具有与有源芯片互连的第二TSV；
封装体，将有源芯片、内存芯片和导热体封装在基板上，导热体上第二TSV的一端与有源芯片互连，第二TSV的另一端在封装体表面露出。
所述有源芯片的背面贴装在基板上，且有源芯片上设置第一TSV；所述内存芯片和导热体均贴装在有源芯片的正面。
所述第二TSV与所述第一TSV平行设置。
所述第二TSV中设置有金属导热件；所述导热体的材质为硅或玻璃。
所述基板上与有源芯片相对的一面上具有BGA球。
所述封装体包括将内存芯片和导热体密封在有源芯片正面的第一封装体，以及位于有源芯片与基板之间的第二封装体，第二封装体实现有源芯片与基板之间间隙的填充。
所述导热体高度高于内存芯片的高度。
一种用于系统散热的封装结构的制备工艺，包括：
将内存芯片和具有第二TSV的导热体贴装在有源芯片的相同一面上；
对有源芯片进行塑封，塑封后形成将导热体和内存芯片均封装在其内部的第一封装体；
对塑封后的有源芯片进行切割制成单颗模块，将单颗模块贴装在基板上，最后完成有源芯片与基板之间的底填形成第二封装体。
具体的，一种用于系统散热的封装结构的制备工艺，包括：
将内存芯片和具有第二TSV的导热体贴装在具有第一TSV的有源芯片的正面；
在有源芯片的正面进行晶圆级塑封，塑封后形成将导热体和内存芯片均封装在其内部的第一封装体；
对有源芯片背面处理后进行晶圆切割制成单颗模块，将单颗模块贴装在基板上，完成有源芯片与基板之间的底填形成第二封装体；
形成第二封装体后，在基板上进行植球操作形成BGA球。
所述导热体高度高于内存芯片的高度，在有源芯片的正面塑封后，对塑封晶圆进行减薄直至内含第二TSV的导热体的表面露出。
所述第二TSV中内填金属介质；所述导热体的材质为硅或玻璃。
本申请技术方案，具有如下优点：
1.由于传统散热方式无法改善封装芯片内部存在的热流密度过大、散热路径过小的问题，如何提升散热能力，通过芯片封装技术进行散热性能的改善则成为了一个可行的方向。但是对大功率产品而言，特别是系统集成度高的产品， 通过芯片封装技术进行散热方式的设置存在很多难点，主要是能在封装的层面入手的改善方式较少。芯片封装影响散热的主要因素包括三个方面，一是封装厚度，厚度越小热阻越小；二是封装面积，面积越大，热阻也越小；三是提高散热性能，即增加封装表面结构的热导率。在现有技术中，基于结构上的限制，通常是从材料本身的热导率上进行产品散热性能的改善；例如：采用高热导率的塑封材料、导热胶可以从一定程度上改善散热，但是材料本身的限制无法大幅提升散热性能。本申请通过在有源芯片上贴装导热体的方式，并结合导热体上与有源芯片互连的第二TSV，可以有效将有源芯片上的热量通过导热体以最小热阻传递到封装表面，扩大封装结构本身的散热路径，进而提高散热性能；考虑到封装整体的应力，本申请中的导热体选用在热膨胀系数上与周围芯片材质相匹配的材质组成，如硅或玻璃等；同时，由于内存芯片的塑封区域增加了大量的硅或玻璃材料，因此，内存芯片的封装热阻也大幅减小，进一步显著扩大封装结构的散热路径，显著提高本申请的散热性能。同时，由于本申请中的整个导热体的增加是在芯片封装的过程中完成的，因此，具有良好的灵活性，即，在后续方案的设计过程中，可以根据产品需要在本申请的结构上直接灵活增加散热盖、散热片等等主被动散热装置。
2.本申请进一步优化了有源芯片的结构，具体的，通过在有源芯片上设置有第一TSV，在该设置方式下，可以实现有源芯片背面与基板之间互连，进而为有源芯片正面贴装内存芯片提供可能。即，本申请通过增加第一TSV，可以在有源芯片正面贴装内存芯片，进而实现有源芯片和内存芯片之间的最短互连，因此，可以有效提高电学性能；并且，在提高电学性能的同时，还能通过有源芯片和内存芯片之间的最短互连，有效将内存芯片的热量传递到导热性好、面积更大的有源芯片上，通过本申请增加的与有源芯片互连的导热体，可以将内存芯片上的热量以最小热阻传递到封装表面，通过导热体扩大的封装芯片内部的散热路径，进而有效将有源芯片上的热量的导出，显著提高散热性能；而且，由于增加TSV孔，还能改善垂直方向热传递性能，更好的达到散热的目的。
3.本申请中提供了一种用于系统散热的封装结构的封装工艺，该工艺步骤中，仅仅只需通过两次封装即可完成成品的制备，能在封装过程中增加提高散热性能的导热体，极大地提高封装后成品的灵活性，即在后续使用本申请封装结构的方案设计过程中，可以根据需要在本申请的封装结构上灵活增加散热盖、散热片等等主被动散热装置；并且，本申请的封装工艺适用于晶圆级封装，可制造性高，封装效率高，操作简便。
附图说明
为了更清楚地显示本申请的产品结构，本申请还提供以下附图。
图1为本申请中一种用于系统散热的封装结构的示意图。
图2为本申请的封装工艺流程图。
附图标记说明：
1-基板，2-有源芯片，3-内存芯片，4-导热体，5-封装体，6-BGA球。
具体实施方式
提供下述实施例是为了更好地进一步理解本申请，并不局限于所述最佳实施方式，不对本申请的内容和保护范围构成限制，任何人在本申请的启示下或是将本申请与其他现有技术的特征进行组合而得出的任何与本申请相同或相近似的产品，均落在本申请的保护范围之内。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
实施例1
一种用于系统散热的封装结构，如图1所示，包括：基板1、有源芯片2、内存芯片3、导热体4和封装体5；其中，有源芯片2贴装在基板1上；内存芯片3贴装在有源芯片2上；导热体4与所述内存芯片3均贴装在有源芯片2的同一面上，所述导热体4上具有与有源芯片2互连的第二TSV；封装体5将有源芯片2、内存芯片3和导热体4封装在基板1上，导热体4上第二TSV的一端与有源芯片2互连，第二TSV的另一端在封装体5表面露出。
通过上述结构的设置，可以将内存芯片3上的热量导入到有源芯片2上，然后通过导热体4将有源芯片2上的热量通过第二TSV将其大量的导出到空气中，扩大了封装结构中芯片热量的导出路径，显著提高导热性能。同时，由于导热体4占用了大量封装体5的体积，进而有效降低封装体5的热阻，进一步提高通过封装体5散热到空气中的效率。
本申请中，该有源芯片2可以涵盖ASIC、CPU、GPU、FPGA等多类型的数字芯片，该类芯片的特点就是高功耗；内存芯片3为HBM芯片，该HBM芯片性质比较单一，既动态内存。通过本申请结构的优化设计，能有效解决运算芯片和内存芯片“合封”之后的系统散热问题，效果十分显著。
本申请中，该内存芯片3贴装在有源芯片2的正面，有源芯片2的背面贴 装在基板1上，且有源芯片2通过引线与基板1连通，本申请中该引线可以绕过有源芯片2与基板1连通，也可以在有源芯片2上设置第一TSV，通过有源芯片2上的第一TSV与基板1连通。
本实施例中选择具有第一TSV的有源芯片2，通过第一TSV与基板1连通。具体为：所述有源芯片2的背面贴装在基板1上，所述内存芯片3和导热体4均贴装在有源芯片2的正面，有源芯片2通过第一TSV与基板1连通。通过上述结构的设置，可以实现有源芯片2与内存芯片3之间的最短互连，具有更好的电学性能，相较于现有的封装结构封装尺寸更小、结构更简单、成本更低的特点。同时，该最短互连的方式结合有源芯片2上设置的第一TSV，能有效为有源芯片2提供另外一个散热路径，有效将有源芯片2的热量传导至基板1上，通过基板将热量导出，提高散热性能。本申请中该第一TSV和第二TSV均为硅片通孔。
为了达到更好的散热效果，本申请中还优化设置了各个部件的具体结构，如：将所述第二TSV与所述第一TSV平行设置，有效改善垂直方向热传递性能；在所述第二TSV中填充金属介质，即，所述第二TSV中设置有金属导热件，有效提高导热性能；所述基板1上与有源芯片2相对的一面上设置BGA球6，通过BGA球6可以有效将芯片通过导线传导到基板1上的热量传递给其他承载材料，提高散热性能。所述封装体5包括将内存芯片3和导热体4密封在有源芯片2正面的第一封装体，以及位于有源芯片2与基板1之间且实现有源芯片2与基板1之间间隙填充的第二封装体，通过该结构可以有效最大化的裸露有源芯片2的侧面，提高有源芯片2的散热性能。所述导热体4高度高于内存芯片3的高度，可以简化制备的工艺。
实施例2
本实施例提供了一种用于系统散热的封装结构的封装工艺，如图2所示，具体过程如下：
步骤一、将内存芯片3和具有第二TSV的导热体4贴装在有源芯片2的相同一面上。本申请中，先将内存芯片3贴装在有源芯片2上，再将导热体4贴装在有源芯片2上。内存芯片3可以贴装在有源芯片2的正面，也可以贴装在有源芯片2的背面；贴装在背面时，可以通过引线实现有源芯片2与内存芯片3的互连；贴装在正面时，可以采用内存芯片3背面贴装在有源芯片2正面，此时可以通过引线实现内存芯片3与有源芯片2互连，也可以采用内存芯片3正面贴装在有源芯片2的正面，此时可以有效实现有源芯片2与有源芯片2最短互连。本实施例中，采用有源芯片2正面与内存芯片3正面相互贴装的方式，有效实现内存芯片3与有源芯片2最短互连。在内存芯片3贴装在有源芯片2上后，再将导热体4分布在内存芯片3的周围，贴装在有源芯片2的正面，如图2所示。本实施例中导热体4上的第二TSV的中心轴线垂直于有源芯片2的正面，可以更好的将芯片中的热量导出到空气中。
步骤二、对有源芯片2进行塑封，塑封后形成将导热体4和内存芯片3均封装在其内部的第一封装体。本实施例中将导热体4的高度设置为高于内存芯片3的方式，此时，本步骤中的塑封可以采用晶圆级塑封，在第一封装体将导热体4和内存芯片3全部包覆在有源芯片2的正面后，在采用切割减薄的方式露出导热体4，在不损坏内存芯片3的情况下，同时实现多个有源芯片2的塑封操作，操作更加简单以及快速。
步骤三、对塑封后的有源芯片2进行晶圆切割制成单颗模块，对单颗模块进行背面凸块的设置，便于使单颗模块贴装到基板1上，如图2所示。最后将单颗模块贴装在基板1上，完成有源芯片2与基板1之间的底填形成第二封装体。本申请中的第一封装体和第二封装体共同构成本申请中的封装体5。在完成封装体5之前或者之后，均可以在基板1另一侧面上进行植球工艺设置BGA球6。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的 限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请创造的保护范围之中。

Claims (11)

  1. 一种用于系统散热的封装结构，其特征在于，包括：
    基板(1)；
    有源芯片(2)，贴装在基板(1)上；
    内存芯片(3)，贴装在有源芯片(2)上；
    导热体(4)，所述导热体(4)与所述内存芯片(3)均贴装在有源芯片(2)的同一面上，所述导热体(4)上具有与有源芯片(2)互连的第二TSV；
    封装体(5)，将有源芯片(2)、内存芯片(3)和导热体(4)封装在基板(1)上，导热体(4)上第二TSV的一端与有源芯片(2)互连，第二TSV的另一端在封装体(5)表面露出。
  2. 根据权利要求1所述的一种用于系统散热的封装结构，其特征在于，所述有源芯片(2)的背面贴装在基板(1)上，且有源芯片(2)上设置第一TSV；所述内存芯片(3)和导热体(4)均贴装在有源芯片(2)的正面。
  3. 根据权利要求2所述的一种用于系统散热的封装结构，其特征在于，所述第二TSV与所述第一TSV平行设置。
  4. 根据权利要求1～3任一项所述的一种用于系统散热的封装结构，其特征在于，所述第二TSV中设置有金属导热件；所述导热体(4)的材质为硅或玻璃。
  5. 根据权利要求1～4任一项所述的一种用于系统散热的封装结构，其特征在于，所述基板(1)上与有源芯片(2)相对的一面上具有BGA球(6)。
  6. 根据权利要求1～5任一项所述的一种用于系统散热的封装结构，其特征在于，所述封装体(5)包括将内存芯片(3)和导热体(4)密封在有源芯片(2) 正面的第一封装体，以及位于有源芯片(2)与基板(1)之间的第二封装体。
  7. 根据权利要求1～6任一项所述的一种用于系统散热的封装结构，其特征在于，所述导热体(4)高度高于内存芯片(3)的高度。
  8. 一种用于系统散热的封装结构的封装工艺，其特征在于，包括：
    将内存芯片(3)和具有第二TSV的导热体(4)贴装在有源芯片(2)的相同一面上；
    对有源芯片(2)进行塑封，塑封后形成将导热体(4)和内存芯片(3)均封装在其内部的第一封装体；
    对塑封后的有源芯片(2)进行切割制成单颗模块，将单颗模块贴装在基板(1)上，最后完成有源芯片(2)与基板(1)之间的底填形成第二封装体。
  9. 根据权利要求8所述的一种用于系统散热的封装结构的封装工艺，其特征在于，包括：
    将内存芯片(3)和具有第二TSV的导热体(4)贴装在具有第一TSV的有源芯片(2)的正面；
    在有源芯片(2)的正面进行晶圆级塑封，塑封后形成将导热体(4)和内存芯片(3)均封装在其内部的第一封装体；
    对有源芯片(2)背面处理后进行晶圆切割制成单颗模块，将单颗模块贴装在基板(1)上，完成有源芯片(2)与基板(1)之间的底填形成第二封装体；
    形成第二封装体后，在基板(1)上进行植球操作形成BGA球(6)。
  10. 根据权利要求8或9所述的一种用于系统散热的封装结构的封装工艺，其特征在于，所述导热体(4)高度高于内存芯片(3)的高度，在有源芯片(2) 的正面塑封后，对塑封晶圆进行减薄直至内含第二TSV的导热体(4)的表面露出。
  11. 根据权利要求8-10任一项所述的一种用于系统散热的封装结构的封装工艺，其特征在于，所述第二TSV中内填金属介质，所述导热体(4)的材质为硅或玻璃。
PCT/CN2019/128945 2019-12-12 2019-12-27 一种用于系统散热的封装结构及其封装工艺 WO2021114410A1 (zh)

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