JP5456103B2 - 配線基板及び半導体装置の製造方法 - Google Patents
配線基板及び半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5456103B2 JP5456103B2 JP2012154172A JP2012154172A JP5456103B2 JP 5456103 B2 JP5456103 B2 JP 5456103B2 JP 2012154172 A JP2012154172 A JP 2012154172A JP 2012154172 A JP2012154172 A JP 2012154172A JP 5456103 B2 JP5456103 B2 JP 5456103B2
- Authority
- JP
- Japan
- Prior art keywords
- support
- layer
- wiring board
- manufacturing
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1152—Replicating the surface structure of a sacrificial layer, e.g. for roughening
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base
- Y10T29/4916—Simultaneous circuit manufacturing
Description
図3及び図4は本発明の第1実施形態に係る配線基板の製造方法を工程順に示すものである。図3(a)において、支持体20を準備する。支持体20としては、例えば、Cu等からなる金属板、或いは同様にCu等からなる金属箔を用いるのが一般である。Cuから成る銅箔の場合は、圧延銅箔、電解銅箔等が好適に用いられる。
この際、支持体20の粗化面20aの表面形状が、半導体素子搭載面27の絶縁層23に転写され、半導体素子搭載面27が粗化面23aとなる。
この際、支持体20の粗化面20aの表面形状が、半導体素子搭載面27のソルダレジスト層29に転写され、半導体素子搭載面27が粗化面29aとなる。
1)第1及び2実施形態では、支持体20に粗面化処理を施した後、めっき層22(接続パッド)を形成している。よって、支持体20の粗化面にめっきレジスト層21が食い込むことにより、めっきレジスト層21と支持体20との密着性が向上し、めっきレジスト層21の下部におけるめっき形成用の開口部の縁等の不要部分へのめっき液しみ込みが発生せず、良好に安定した形状のめっき層22を形成できことができる。
このように、第1〜第3実施形態では、ソルダレジスト層29と支持体20との密着性が向上するため、製造工程中に、支持体20から製造途中の中間体40が剥離・脱落することを防止できる利点がある。
この際、支持体20の粗化面20aの表面形状が、半導体素子搭載面27の絶縁層23に転写され、半導体素子搭載面27が、粗化面23aとなる。
300nm ≦ Ra ≦ 800nm、
3.5μm ≦ Rz ≦ 7μm、
となるように、支持体の表面の粗さを調整するのが好適である。
20a 支持体の粗化面
21 めっきレジスト層
21a 開口部
22 めっき層
23 絶縁層(誘電体層)
23a 絶縁層の粗化面
24 ビア孔(開口)
25 配線層(金属層)
26 ソルダレジスト層(誘電体層)
27 半導体素子搭載面
28 外部接続端子面
29 ソルダレジスト層
29a ソルダレジスト層の粗化面
30 半導体素子
40 中間体
42 配線基板(多層配線基板ないし半導体パッケージ)
Claims (24)
- 金属からなる支持体の表面に直接粗化処理を施して、粗化面を形成する工程と、
該支持体の粗化面に直接配線層を形成する工程と、
該支持体の粗化面と該配線層上に誘電体層を積層する工程と、
このように構成した中間体から支持体を除去し、配線基板を得る工程と、
から成ることを特徴とする配線基板の製造方法。 - 支持体上に形成される配線層が、接続パッドであることを特徴とする請求項1に記載の配線基板の製造方法。
- 前記接続パッドは、Auめっき層とNiめっき層とを積層したもの、Auめっき層とNiめっき層とを積層したもの、Auめっき層とNiめっき層とCuめっき層とを積層したもの、Auめっき層とPdめっき層とNiめっき層とCuめっき層とを積層したもの、Niめっき層とCuめっき層とを積層したもの、のいずれかであることを特徴とする請求項2に記載の配線基板の製造方法。
- エッチングにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項1〜3のいずれか1項に記載の配線基板の製造方法。
- 酸化処理により酸化膜を設けることにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項1〜3のいずれか1項に記載の配線基板の製造方法。
- めっきにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項1〜3のいずれか1項に記載の配線基板の製造方法。
- 前記支持体の表面は、ブラスト処理により、粗化面に形成されることを特徴とする請求項1〜3のいずれか1項に記載の配線基板の製造方法。
- 誘電体層が、樹脂からなる絶縁層又はソルダレジスト層であることを特徴とする請求項1〜7のいずれか1項に記載の配線基板の製造方法。
- 前記支持体の粗化面の表面形状が、配線基板の支持体除去面の誘電体層及び配線層の表面に転写され、該誘電体層及び配線層の表面が粗化面に形成されることを特徴とする請求項1〜8のいずれか1項に記載の配線基板の製造方法。
- 前記支持体の表面の粗化の程度は、
300nm ≦ Ra ≦ 800nm、
3.5μm ≦ Rz ≦ 7μm、
であることを特徴とする請求項1〜9のいずれか1項に記載の配線基板の製造方法。 - 該支持体の粗化面に配線層としての接続パッドを形成し、該支持体の粗化面の表面形状が該接続パッドの表面に転写され、該接続パッド表面が粗化面に形成されることを特徴とする請求項2〜10のいずれか1項に記載の配線基板の製造方法。
- 前記誘電体層に、配線層を底面に露出し、開口部の面積が底部側の面積より大きい逆円錐台形状の開口部を形成し、該誘電体層上に、開口部の底面及び側面を含む領域を覆う金属層からなる配線を形成することを特徴とする請求項1〜11のいずれか1項に記載の配線基板の製造方法。
- 金属からなる支持体の表面に直接粗化処理を施し、粗化面を形成する工程と、
該支持体の粗化面に直接配線層を形成する工程と、
該支持体の粗化面と該配線層上に誘電体層を積層する工程と、
このように構成した中間体から支持体を除去し、配線基板を得る工程と、
該配線基板の支持体除去面に、半導体素子を搭載する工程と、
から成ることを特徴とする半導体装置の製造方法。 - 支持体上に形成される配線層が、接続パッドであることを特徴とする請求項13に記載の半導体装置の製造方法。
- 金属からなる支持体の表面に直接粗化処理を施し、粗化面を形成する工程と、
該支持体の粗化面に直接配線層を形成する工程と、
該支持体の粗化面と該配線層上に誘電体層を積層する工程と、
このように構成した中間体から支持体を除去し、配線基板を得る工程と、
該配線基板の支持体除去面と対向する面に、半導体素子を搭載する工程と、
から成ることを特徴とする半導体装置の製造方法。 - 支持体上に形成される配線層が、接続パッドであることを特徴とする請求項15に記載の半導体装置の製造方法。
- 金属からなる支持体の表面に直接粗化処理を施し、粗化面を形成する工程と、
該支持体の粗化面に直接配線層を形成する工程と、
該支持体の粗化面と該配線層上に誘電体層を積層し、中間体を得る工程と、
該中間体の、前記支持体との接触面と対向する面上に、半導体素子を搭載する工程と、
該中間体から支持体を除去し、半導体装置を得る工程と、
から成ることを特徴とする半導体装置の製造方法。 - 支持体上に形成される配線層が、接続パッドであることを特徴とする請求項17に記載の半導体装置の製造方法。
- 誘電体層が、樹脂からなる絶縁層又はソルダレジスト層であることを特徴とする請求項13〜18のいずれか1項に記載の半導体装置の製造方法。
- エッチングにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項13〜19のいずれか1項に記載の半導体装置の製造方法。
- めっきにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項13〜19のいずれか1項に記載の半導体装置の製造方法。
- 酸化処理により酸化膜を設けることにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項13〜19のいずれか1項に記載の半導体装置の製造方法。
- 前記支持体の表面は、ブラスト処理により、粗化面に形成されることを特徴とする請求項13〜19のいずれか1項に記載の半導体装置の製造方法。
- 前記支持体の粗化面の表面形状が、配線基板の支持体除去面の誘電体層及び配線層の表面に転写され、該誘電体層及び配線層の表面が粗化面に形成されることを特徴とする請求項13〜23のいずれか1項に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012154172A JP5456103B2 (ja) | 2007-10-05 | 2012-07-09 | 配線基板及び半導体装置の製造方法 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007262753 | 2007-10-05 | ||
JP2007262753 | 2007-10-05 | ||
JP2012154172A JP5456103B2 (ja) | 2007-10-05 | 2012-07-09 | 配線基板及び半導体装置の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008259027A Division JP5398217B2 (ja) | 2007-10-05 | 2008-10-03 | 配線基板及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012209580A JP2012209580A (ja) | 2012-10-25 |
JP5456103B2 true JP5456103B2 (ja) | 2014-03-26 |
Family
ID=40533076
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008259027A Active JP5398217B2 (ja) | 2007-10-05 | 2008-10-03 | 配線基板及び半導体装置の製造方法 |
JP2012154173A Pending JP2012231167A (ja) | 2007-10-05 | 2012-07-09 | 配線基板及び半導体装置 |
JP2012154172A Active JP5456103B2 (ja) | 2007-10-05 | 2012-07-09 | 配線基板及び半導体装置の製造方法 |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008259027A Active JP5398217B2 (ja) | 2007-10-05 | 2008-10-03 | 配線基板及び半導体装置の製造方法 |
JP2012154173A Pending JP2012231167A (ja) | 2007-10-05 | 2012-07-09 | 配線基板及び半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (2) | US8502398B2 (ja) |
JP (3) | JP5398217B2 (ja) |
KR (2) | KR101551898B1 (ja) |
CN (1) | CN101404259A (ja) |
TW (1) | TWI447874B (ja) |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8240036B2 (en) | 2008-04-30 | 2012-08-14 | Panasonic Corporation | Method of producing a circuit board |
JP5138459B2 (ja) * | 2008-05-15 | 2013-02-06 | 新光電気工業株式会社 | 配線基板の製造方法 |
JP5101451B2 (ja) * | 2008-10-03 | 2012-12-19 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
TWI468093B (zh) * | 2008-10-31 | 2015-01-01 | Princo Corp | 多層基板之導孔結構及其製造方法 |
JP2011060892A (ja) * | 2009-09-08 | 2011-03-24 | Renesas Electronics Corp | 電子装置、電子装置の製造方法 |
US8929092B2 (en) | 2009-10-30 | 2015-01-06 | Panasonic Corporation | Circuit board, and semiconductor device having component mounted on circuit board |
US9332642B2 (en) * | 2009-10-30 | 2016-05-03 | Panasonic Corporation | Circuit board |
US20110110061A1 (en) * | 2009-11-12 | 2011-05-12 | Leung Andrew Kw | Circuit Board with Offset Via |
US8742561B2 (en) * | 2009-12-29 | 2014-06-03 | Intel Corporation | Recessed and embedded die coreless package |
US8389337B2 (en) * | 2009-12-31 | 2013-03-05 | Intel Corporation | Patch on interposer assembly and structures formed thereby |
JP5566200B2 (ja) * | 2010-06-18 | 2014-08-06 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP5680401B2 (ja) * | 2010-12-22 | 2015-03-04 | 新光電気工業株式会社 | 配線基板及び半導体パッケージ |
TWI455268B (zh) * | 2011-03-22 | 2014-10-01 | Nan Ya Printed Circuit Board | 封裝載板及其製造方法 |
TWI473551B (zh) * | 2011-07-08 | 2015-02-11 | Unimicron Technology Corp | 封裝基板及其製法 |
US20130098659A1 (en) * | 2011-10-25 | 2013-04-25 | Yiu Fai KWAN | Pre-plated lead frame for copper wire bonding |
US8927875B2 (en) * | 2011-10-28 | 2015-01-06 | Ibiden Co., Ltd. | Wiring board and method for manufacturing wiring board |
CN103249263A (zh) * | 2012-02-07 | 2013-08-14 | 景硕科技股份有限公司 | 线路积层板的线路结构的制作方法 |
CN103379726A (zh) * | 2012-04-17 | 2013-10-30 | 景硕科技股份有限公司 | 线路积层板的复层线路结构 |
JP5502139B2 (ja) * | 2012-05-16 | 2014-05-28 | 日本特殊陶業株式会社 | 配線基板 |
JP5341227B1 (ja) * | 2012-05-16 | 2013-11-13 | 日本特殊陶業株式会社 | 配線基板 |
JP6266907B2 (ja) * | 2013-07-03 | 2018-01-24 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
JP6223909B2 (ja) | 2013-07-11 | 2017-11-01 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP6131135B2 (ja) | 2013-07-11 | 2017-05-17 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
CN104299919B (zh) * | 2013-07-15 | 2017-05-24 | 碁鼎科技秦皇岛有限公司 | 无芯层封装结构及其制造方法 |
KR101442423B1 (ko) | 2013-08-14 | 2014-09-17 | 삼성전기주식회사 | 전자부품 내장기판 제조 방법 및 전자부품 내장기판 |
CN104793026B (zh) * | 2014-01-20 | 2018-09-28 | 旺矽科技股份有限公司 | 应用于探针测试装置的支撑结构及其制作方法 |
TW201539596A (zh) * | 2014-04-09 | 2015-10-16 | Tong Hsing Electronic Ind Ltd | 中介體及其製造方法 |
DE102014115815B4 (de) * | 2014-10-30 | 2022-11-17 | Infineon Technologies Ag | Verfahren zur herstellung eines schaltungsträgers, verfahren zur herstellung einer halbleiteranordung, verfahren zum betrieb einer halbleiteranordnung und verfahren zur herstellung eines halbleitermoduls |
US10285277B1 (en) * | 2015-12-31 | 2019-05-07 | Lockheed Martin Corporation | Method of manufacturing circuits using thick metals and machined bulk dielectrics |
JP2016105512A (ja) * | 2016-03-01 | 2016-06-09 | 京セラサーキットソリューションズ株式会社 | 配線基板の製造方法 |
JP2017157739A (ja) | 2016-03-03 | 2017-09-07 | イビデン株式会社 | 電子部品付き配線板の製造方法 |
JP2017191688A (ja) * | 2016-04-12 | 2017-10-19 | デクセリアルズ株式会社 | 電気特性の検査方法 |
JP6594264B2 (ja) * | 2016-06-07 | 2019-10-23 | 新光電気工業株式会社 | 配線基板及び半導体装置、並びにそれらの製造方法 |
KR102534940B1 (ko) * | 2016-07-28 | 2023-05-22 | 삼성전기주식회사 | 인쇄회로기판 |
JP6935539B2 (ja) * | 2016-11-30 | 2021-09-15 | 新光電気工業株式会社 | 配線基板の製造方法 |
CN108271313B (zh) * | 2016-12-30 | 2021-03-16 | 奥特斯(中国)有限公司 | 用于部件承载件的具有纳米和/或微米结构的片材 |
JP7464352B2 (ja) * | 2018-03-09 | 2024-04-09 | 日東電工株式会社 | 配線基板およびその製造方法 |
JP7202869B2 (ja) | 2018-12-10 | 2023-01-12 | ヌヴォトンテクノロジージャパン株式会社 | 半導体装置及び半導体装置の製造方法 |
JP7338991B2 (ja) * | 2019-03-04 | 2023-09-05 | リンクステック株式会社 | 支持体付き配線基板、支持体付き電子部品パッケージ及びこれらの製造方法 |
US11004819B2 (en) * | 2019-09-27 | 2021-05-11 | International Business Machines Corporation | Prevention of bridging between solder joints |
AT17082U1 (de) * | 2020-04-27 | 2021-05-15 | Zkw Group Gmbh | Verfahren zur befestigung eines elektronischen bauteils |
US20220161817A1 (en) * | 2020-11-20 | 2022-05-26 | Here Global B.V. | Method, apparatus, and system for creating doubly-digitised maps |
CN112445035A (zh) * | 2020-11-30 | 2021-03-05 | 深圳同兴达科技股份有限公司 | 导电贴以及液晶显示模组 |
US11735529B2 (en) | 2021-05-21 | 2023-08-22 | International Business Machines Corporation | Side pad anchored by next adjacent via |
KR20230097817A (ko) * | 2021-12-24 | 2023-07-03 | 삼성전기주식회사 | 인쇄회로기판, 캐리어 부착 인쇄회로기판 및 인쇄회로기판 패키지의 제조방법 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3635219B2 (ja) | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | 半導体装置用多層基板及びその製造方法 |
JP4691763B2 (ja) | 2000-08-25 | 2011-06-01 | イビデン株式会社 | プリント配線板の製造方法 |
EP1915041A1 (en) * | 2001-09-28 | 2008-04-23 | Ibiden Co., Ltd. | Printed wiring board and printed wiring board manufacturing method |
JP2003297973A (ja) | 2002-03-28 | 2003-10-17 | Hitachi Chem Co Ltd | 半導体パッケージ用基板、その製造方法、半導体パッケージおよびその製造方法 |
JP3888943B2 (ja) | 2002-04-12 | 2007-03-07 | イビデン株式会社 | 多層プリント配線板及び多層プリント配線板の製造方法 |
JP2004319660A (ja) * | 2003-04-15 | 2004-11-11 | Toray Ind Inc | 回路基板用部材および回路基板の製造方法 |
JP4547164B2 (ja) | 2004-02-27 | 2010-09-22 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
JP5046481B2 (ja) | 2004-09-27 | 2012-10-10 | 日立電線株式会社 | 半導体装置及びその製造方法 |
JP2006186321A (ja) * | 2004-12-01 | 2006-07-13 | Shinko Electric Ind Co Ltd | 回路基板の製造方法及び電子部品実装構造体の製造方法 |
JP4538373B2 (ja) | 2005-05-23 | 2010-09-08 | 日本特殊陶業株式会社 | コアレス配線基板の製造方法、及びそのコアレス配線基板を有する電子装置の製造方法 |
JP4146864B2 (ja) | 2005-05-31 | 2008-09-10 | 新光電気工業株式会社 | 配線基板及びその製造方法、並びに半導体装置及び半導体装置の製造方法 |
CN101171894B (zh) * | 2005-06-30 | 2010-05-19 | 揖斐电株式会社 | 印刷线路板 |
JP2008258520A (ja) * | 2007-04-09 | 2008-10-23 | Shinko Electric Ind Co Ltd | 配線基板の製造方法及び配線基板 |
-
2008
- 2008-10-02 US US12/244,232 patent/US8502398B2/en active Active
- 2008-10-02 KR KR1020080097094A patent/KR101551898B1/ko active IP Right Grant
- 2008-10-03 TW TW097138060A patent/TWI447874B/zh active
- 2008-10-03 JP JP2008259027A patent/JP5398217B2/ja active Active
- 2008-10-06 CN CNA2008101695036A patent/CN101404259A/zh active Pending
-
2012
- 2012-02-24 US US13/404,627 patent/US8779602B2/en active Active
- 2012-07-09 JP JP2012154173A patent/JP2012231167A/ja active Pending
- 2012-07-09 JP JP2012154172A patent/JP5456103B2/ja active Active
-
2015
- 2015-02-12 KR KR20150021511A patent/KR20150033625A/ko active Search and Examination
Also Published As
Publication number | Publication date |
---|---|
TW200919672A (en) | 2009-05-01 |
KR20150033625A (ko) | 2015-04-01 |
JP2009105393A (ja) | 2009-05-14 |
CN101404259A (zh) | 2009-04-08 |
KR101551898B1 (ko) | 2015-09-09 |
US20120155048A1 (en) | 2012-06-21 |
KR20090035449A (ko) | 2009-04-09 |
JP5398217B2 (ja) | 2014-01-29 |
TWI447874B (zh) | 2014-08-01 |
US8502398B2 (en) | 2013-08-06 |
US8779602B2 (en) | 2014-07-15 |
US20090095514A1 (en) | 2009-04-16 |
JP2012231167A (ja) | 2012-11-22 |
JP2012209580A (ja) | 2012-10-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5456103B2 (ja) | 配線基板及び半導体装置の製造方法 | |
JP5324051B2 (ja) | 配線基板の製造方法及び半導体装置の製造方法及び配線基板 | |
US9119319B2 (en) | Wiring board, semiconductor device, and method for manufacturing wiring board | |
US9179552B2 (en) | Wiring board | |
JP2005310946A (ja) | 半導体装置 | |
JP6840935B2 (ja) | 配線回路基板の製造方法 | |
JP2017163027A (ja) | 配線基板、半導体装置及び配線基板の製造方法 | |
JP2017084997A (ja) | プリント配線板及びその製造方法 | |
TWI458416B (zh) | 配線基板製造方法 | |
JP5157455B2 (ja) | 半導体装置 | |
JP2014179430A (ja) | 半導体素子搭載用多層プリント配線板 | |
JP6473002B2 (ja) | バンプ付きプリント配線板 | |
KR100908986B1 (ko) | 코어리스 패키지 기판 및 제조 방법 | |
JP4196606B2 (ja) | 配線板の製造方法 | |
JP2013122962A (ja) | 配線基板 | |
JP2012074487A (ja) | 半導体パッケージの製造方法 | |
JP2013122963A (ja) | 配線基板 | |
JP2017045923A (ja) | バンプ付きプリント配線板およびその製造方法 | |
JP2016127066A (ja) | バンプ付きプリント配線板およびその製造方法 | |
JP7412735B2 (ja) | 半導体パッケージの製造方法 | |
JP2013122961A (ja) | 配線基板、配線基板の製造方法 | |
JP6464774B2 (ja) | 配線基板およびその製造方法 | |
JP5753521B2 (ja) | 配線基板の製造方法 | |
JP2005093930A (ja) | 多層基板とその製造方法 | |
JP2013084812A (ja) | 半導体パッケージの製造方法及び半導体パッケージ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130425 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130514 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130702 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131210 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140107 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5456103 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |