JP4547164B2 - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
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- JP4547164B2 JP4547164B2 JP2004054996A JP2004054996A JP4547164B2 JP 4547164 B2 JP4547164 B2 JP 4547164B2 JP 2004054996 A JP2004054996 A JP 2004054996A JP 2004054996 A JP2004054996 A JP 2004054996A JP 4547164 B2 JP4547164 B2 JP 4547164B2
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- Prior art keywords
- layer
- thin film
- metal
- film layer
- conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
支持基板として用いる金属板の第一主表面の全体を覆うように、該金属板に対して選択エッチング性を有する金属薄膜層を被膜する被膜工程と、
前記被膜工程後に、前記金属薄膜層の第一主表面に、該金属薄膜層に対して選択エッチング性を有し、且つ表面粗化処理の可能な薄膜層を形成し、該薄膜層の第一主表面を粗化処理する粗化処理工程と、
粗化処理が施された前記薄膜層の第一主表面に、金属端子パッドをなす導体パターンを形成した上で、高分子材料からなる誘電体層と金属導体層とを交互に積層して配線積層部を形成する積層工程と、
前記積層工程後に、前記金属板を選択エッチングにより除去し、次いで、前記金属薄膜層及び前記薄膜層をそれぞれ選択エッチングにより除去することで、前記薄膜層の第一主表面側に形成された前記導体パターンを露出させるエッチング工程と、
をこの順で行うことを特徴とする。
なお、配線基板の製造方法としては、支持基板として用いる金属板の第一主表面の全体を覆うように、該金属板に対して選択エッチング性を有する金属薄膜層を被膜する被膜工程と、
前記被膜工程後に、前記金属薄膜層の第一主表面に、下部第一誘電体層を形成し、該下部第一誘電体層の所定位置に開口を貫通形成し、該開口の壁部および底部を含む領域を覆うように金属端子パッドとなるべき被覆導体部を形成する金属端子パッド形成工程と、
前記下部第一誘電体層上に形成された上部第一誘電体層に、前記被覆導体部のうち、前記開口の底部を覆う部位と接続するビア導体を形成するビア導体形成工程と、
前記上部第一誘電体層の第一主表面側に、金属導体層と誘電体層とを交互に積層して配線積層部を形成する積層工程と、
前記積層工程後に、前記金属板を選択エッチングにより除去し、次いで、前記金属薄膜層を選択エッチングにより除去することで、前記金属薄膜層の第一主表面側に形成された前記被覆導体部を露出させるエッチング工程と、をこの順で行うようにすることも考えられる。
2 金属板(Cu板)
3 金属薄膜層
10,10a,10b 配線積層部(ビルドアップ層)
11,11a,12,13,14 導体パターン
21,22,23 ビア導体
30 樹脂フィルム
SR ソルダーレジスト
FB ハンダバンプ
SB ハンダボール
ST 補強枠(スティフナー)
Claims (3)
- 支持基板として用いる金属板の第一主表面の全体を覆うように、該金属板に対して選択エッチング性を有する金属薄膜層を被膜する被膜工程と、
前記被膜工程後に、前記金属薄膜層の第一主表面に、該金属薄膜層に対して選択エッチング性を有し、且つ表面粗化処理の可能な薄膜層を形成し、該薄膜層の第一主表面を粗化処理する粗化処理工程と、
粗化処理が施された前記薄膜層の第一主表面に、金属端子パッドをなす導体パターンを形成した上で、高分子材料からなる誘電体層と金属導体層とを交互に積層して配線積層部を形成する積層工程と、
前記積層工程後に、前記金属板を選択エッチングにより除去し、次いで、前記金属薄膜層及び前記薄膜層をそれぞれ選択エッチングにより除去することで、前記薄膜層の第一主表面側に形成された前記導体パターンを露出させるエッチング工程と、
をこの順で行うことを特徴とする配線基板の製造方法。 - 前記薄膜層の第一主表面に前記導体パターンを形成した後、該導体パターンの露出表面を粗化処理する請求項1に記載の配線基板の製造方法。
- 前記エッチング工程により露出した前記導体パターンの露出面に、電子部品が搭載されるハンダバンプを形成する請求項1又は2に記載の配線基板の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004054996A JP4547164B2 (ja) | 2004-02-27 | 2004-02-27 | 配線基板の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004054996A JP4547164B2 (ja) | 2004-02-27 | 2004-02-27 | 配線基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005244104A JP2005244104A (ja) | 2005-09-08 |
JP4547164B2 true JP4547164B2 (ja) | 2010-09-22 |
Family
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Family Applications (1)
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JP2004054996A Expired - Fee Related JP4547164B2 (ja) | 2004-02-27 | 2004-02-27 | 配線基板の製造方法 |
Country Status (1)
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JP (1) | JP4547164B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007180529A (ja) * | 2005-12-02 | 2007-07-12 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US20070126085A1 (en) | 2005-12-02 | 2007-06-07 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US7692284B2 (en) * | 2005-12-12 | 2010-04-06 | Intel Corporation | Package using array capacitor core |
JP4783692B2 (ja) * | 2006-08-10 | 2011-09-28 | 新光電気工業株式会社 | キャパシタ内蔵基板及びその製造方法と電子部品装置 |
JP4994988B2 (ja) * | 2007-07-31 | 2012-08-08 | 京セラSlcテクノロジー株式会社 | 配線基板の製造方法 |
KR101551898B1 (ko) | 2007-10-05 | 2015-09-09 | 신꼬오덴기 고교 가부시키가이샤 | 배선 기판, 반도체 장치 및 이들의 제조 방법 |
JP5693977B2 (ja) | 2011-01-11 | 2015-04-01 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP2012146990A (ja) * | 2012-02-22 | 2012-08-02 | Sumitomo Bakelite Co Ltd | 多層回路基板、多層回路基板の製造方法および半導体装置 |
JP6266907B2 (ja) * | 2013-07-03 | 2018-01-24 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08204333A (ja) * | 1995-01-31 | 1996-08-09 | Toshiba Corp | 印刷配線板の製造方法 |
JP2000208936A (ja) * | 1999-01-13 | 2000-07-28 | Ngk Spark Plug Co Ltd | プリント配線板の製造方法 |
JP2002076578A (ja) * | 2000-08-25 | 2002-03-15 | Ibiden Co Ltd | プリント配線板及びその製造方法 |
JP2002111205A (ja) * | 2000-07-27 | 2002-04-12 | Sumitomo Bakelite Co Ltd | 多層配線板の製造方法および多層配線板 |
JP2004006829A (ja) * | 2002-04-25 | 2004-01-08 | Matsushita Electric Ind Co Ltd | 配線転写シートとその製造方法、および配線基板とその製造方法 |
-
2004
- 2004-02-27 JP JP2004054996A patent/JP4547164B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08204333A (ja) * | 1995-01-31 | 1996-08-09 | Toshiba Corp | 印刷配線板の製造方法 |
JP2000208936A (ja) * | 1999-01-13 | 2000-07-28 | Ngk Spark Plug Co Ltd | プリント配線板の製造方法 |
JP2002111205A (ja) * | 2000-07-27 | 2002-04-12 | Sumitomo Bakelite Co Ltd | 多層配線板の製造方法および多層配線板 |
JP2002076578A (ja) * | 2000-08-25 | 2002-03-15 | Ibiden Co Ltd | プリント配線板及びその製造方法 |
JP2004006829A (ja) * | 2002-04-25 | 2004-01-08 | Matsushita Electric Ind Co Ltd | 配線転写シートとその製造方法、および配線基板とその製造方法 |
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