TWI259045B - Wiring board and semiconductor package using the same - Google Patents
Wiring board and semiconductor package using the same Download PDFInfo
- Publication number
- TWI259045B TWI259045B TW094113919A TW94113919A TWI259045B TW I259045 B TWI259045 B TW I259045B TW 094113919 A TW094113919 A TW 094113919A TW 94113919 A TW94113919 A TW 94113919A TW I259045 B TWI259045 B TW I259045B
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- Taiwan
- Prior art keywords
- wiring board
- insulating film
- line
- base insulating
- layer
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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Description
1259045 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種適用於半導體封裝與模組之接線 板,以及關於使用該接線板之半導體封裝。特別地,本發 明係關於一種接線板,其可以在高密度度下包含各種裝 置,例如半導體裝置,並以高速驅動此些裝置且具有高可 罪性’以及關於一種使用該接線板之半導體封裝。 【先前技術】 近年來,隨半導體裝置端子數目的增加、節距的縮小、 以及操作速度的提昇,裝置具有更高的效能與更強的功 能,因此,對於可以提供半導體裝置高密度微細接線以及 高速運作之封裝用接線板之需求有增加之趨勢。例如,習 用之封裝用接線板係為組合式印刷電路板,亦即一種多層 印刷電路板。 0 第1圖係顯示習知組合式印刷電路板之剖面圖。如i 圖所示’此習知之組合式板具有-玻璃環氧樹脂構成之核 土板73以及穿孔7卜具係於核心基板73上鑽出約 崎m之直徑。導線72係形成於核心基板”之兩側層 =緣膜75係覆蓋導線72。介層孔74係形成於層間絕緣 、5上並連接至導線72 ’導線76係形成於層間絕緣膜π 之表面’錢過介射L 74連接轉線 ::由重複形成層間絕緣層形成多層導線結構,= 介層孔以及導線76。 τ /风 然而’由於❹麵環氧樹脂作為核心基板?3使得組
2143-7057-PF 5 1259045
合式印刷電路板耐熱性不足,導致核心基板73於熱處理以 形成層間絕緣膜75時產生形變,如收縮、翹曲以及波浪。 當使用導線圖形(未顯示)形成導線76時必須有一光阻曝 光製程,但是曝光的位置精度卻十分低下,因此,使得於 層間絕緣_ 75形成高密度且微細化導線圖形顯得十分困 難。此外’於導線72以及連接至其之穿孔72之接點處需 形成腳位區。即使於具有層間絕緣臈75以及導線76之組 合式疊層上設計高速運作之接線’將由於腳位區而使得阻 抗控制困難且迴路電感上升。故將使得整體組合式印刷電 路板之操作速度下降’而有無法高速運作之問題。 為解決組合式電路板之穿孔所造成之問題,例如曰本 專利公開帛2000-269647號,以及第^屆微電子會議論文 集’ PP. 13卜134 ’揭露其他形成印刷電路板之方式以替代 於玻璃環氧樹脂基板上鑽出穿孔之方式。 第2A至2C圖係顯示習知製造印刷電路板流程之剖面 圖。首先,於預浸材料82上形成既定之導線81,如第Μ 圖所示。以雷射處理於預浸材料82上形成直徑i5㈠_ m之通孔83。接著,如第2B圖所示,於通孔83内填充導 電膏84。如第2C圖所示,製造複數個具有填充導電膏84 之通孔83之預浸材料82,並將其層疊合一。苴中,導線 81之腳位圖形86係連接至相鄰預浸材料之通孔、83,因此 不需於印刷電路板8 5上製造通孔。 然而,於此習知技術中 位精度低下,使得腳位圖形 ’因層疊之預浸材料82中之對 86之直徑難以降低。因此,很
2143-7057-PF 6 1259045 難實現高密度接線,並且阻抗以及迴路電感之控制亦嫌不 足,再者,層疊後之通孔連接之可靠度亦不良。 為解決此數個問題,本案發明人發展出一種製造接線 板之方法,係藉由於諸如金屬板之支撐結構上形成導線 層,再移除支撐結構。此方法係接露於日本專利公開第 2002-198462號(第8及第11頁、及第17圖)。 第3A與3B圖係顯示習知製造接線板流程之剖面圖。
首先,準備一金屬板或類似物所製程之支撐板91,如第3A 鲁圖所不。於支撐板91上形成導線92,並形成層間絕緣膜 93以覆蓋導線92,於層間絕緣膜93上形成介層孔94以連 接導線92。接著,於層間絕緣膜93上形成導線95。使導 線95透過介層孔94連接至導線92。重複形成層間絕緣膜 9 3、"層孔9 4以及導線9 5之步驟,可以形成一多層接線。 接著,如第3B圖所示,藉由蝕刻移除部分之支撐板91以 暴露出導線92以及並形成支撐結構96,如此完成接線板 97 〇 • 層間絕緣膜93係由單層之絕緣材料所構成,其薄膜強 度係為70Mpa以上,斷裂後伸長比率係為5%以上,玻璃轉 移溫度係為15(TC以上,熱膨脹係數係為6〇ppm以下,或 • 者絕緣材料所構成之單層膜之彈性模數係為1〇(;卯以上, 熱膨脹係數係為30PPm以下,玻璃轉移溫度係為ι5(Γ(:α 上。 依據此技術,由於接線板97沒有穿孔,因此解決了穿 孔的問題,而可以達成高速傳輸設計。此外,由於使用高 2143-7057-PF 7 1259045 φ w ................. ' .................... ............... ·--、—------------------------ 而才熱金屬板或類似材料作為支撐板91 ’與使用玻璃環氧樹 脂相較,避免了如收縮、翹曲以及波浪之形變,而可能實 現高密度微細導線。再者,接線板之強度可以藉由上述層 間絕緣膜93之機械特性決定。 然而,習知技術具有以下之問題。由於缺少核心基板 使得第3B圖所示之接線板97太細,但是藉由決定上述之 層間絕緣膜93之機械強度可以使接線板97達到足夠之強 度。 • 然而,接線板97通常用於大面積半導體裝置以形成一 半導體封裝,此半導體封裝再固定於一固定基板,如印刷 電路板。半導體裝置於運作中產生熱而使溫度提高,於靜 止時停止產生熱而使溫度降低。因此,於半導體裝置運作 中’由於半導體裝置與固定基板間之熱膨脹係數的差異於 接線板97上產生熱應力。之後,隨著半導體裝置反覆操作 於上述半導體裝置固定於接線板9 7之狀態,接線板9 7亦 反覆承受熱應力,使得接線板97之層間絕緣膜93等可能 _ 產生裂縫。所以,並不可能牢固地結合接線板與半導體封 裝。 【發明内容】 • 本發明之目的係提供一種可信賴之接線板,其可以在 •而密度度下包含各種裝置,例如半導體裝置,並可以輕易 實現南速傳輸與高密度微細接線,以及一種使用該接線板 之半導體封裝。 本發明之接線板包含一基層絕緣膜。該基層絕緣膜之
2143-7057-PF 8 1259045 厚度係為2 0〜1 0 0 // m,並具有一介層孔;一下部線路,係 形成於該基層絕緣層之下表面上,並連接至該介層孔;及 上部線路’係形成於該基層絕緣層上,並連接至該下部 線路及該介層孔;其中該基層絕緣膜係由一耐熱樹脂構 成’該耐熱樹脂之玻璃轉換溫度係為1 5 〇艺或以上,並包 含玻璃或芳族聚酰胺(aramid)構成之強化纖維,其T〇c溫 度之彈性模數係為〇1((^3),了。(:溫度之斷裂強度係為1^ (MPa ) ’具有下列(!)〜(6 )項之物理特性。 (1)厚度方向之熱膨脹係數係為90ppm/k或以下; ⑵ D23- 5 ; (3) Dis〇^ 2. 5 ; ⑷(D-65/ Dl5〇) ^3.0; (5) H23- 140 ;以及 (6) ( H-65/H丨5〇) $ 2· 3。 關於製造接線板之方法,形成接線板於金屬板等之支 撐構件,再移除此支撐構件,本發明人認為足夠的斷裂強 度與彈性模數可以避免因半導體裝置操作時反覆加諸於基 層絕緣膜之熱負荷所引起之破裂。並且本發明人已提出一 申請案關於無會產生破裂之製造接線板之方法(曰本專利 申吻案第2003-38241 8號)。然而,隨著研究此方法的進 步,已發現,即使符合所需之斷裂強度與彈性模數,亦即, 23 C之彈性拉數達5GPa或以上,若—65它之斷裂強度設為 a,150°C之斷裂強度設為b,則(a/b)為45或以 65 C之彈性模數設為c,15(rc之彈性模數設為d,貝(
2143-7057-PF 1259045 為4.7或以下,半導體裝置之可靠度將因結構不同而有所 差異。 此研究的成果發現,以下條件可以獲得高可靠度之接 線板:耐熱樹脂所構成之基層絕緣材料,其玻璃轉移溫度 為150°C以上,並包含玻璃或芳族聚酰胺(aramid)所構成 之強化纖維,其符合斷裂強度與彈性模數之需求,且其厚 度方向之熱膨脹係數為90ppm/K以下。此外,並發現最佳 的斷裂強度與彈性模數。 如上所述,檢驗玻璃轉移溫度l5〇〇cw上或包含玻璃 或芳族聚酰胺(aramid)所構成之已知強化纖維之耐熱樹脂 材料,例如:揭露於日本專利申請案第2〇〇3 —382418號之 Ajinomoto Fine Techno Co·,lnc·所製造之材料(品名 ABF-GX-l031),a&Shin-K〇beElectricMachineryC〇,
Ud.所製造之EA — 541 (品名),且其之厚度方向之熱膨脹 係數皆為90Ppm/k以上。至於這些材料,更發現當介層孔 直接形成於固定半導體裝置之電極焊墊之下,以及用以固 定基板之焊球直接形成於介層孔之下,該些材料之可靠度 低於具有本發明之物理特性之基層絕緣膜材料。 相較之,使用具有本發明之物理特性之基層絕緣膜材 料,可以降低厚度方向之應變應力。因此,當介層孔直接 形成於固定半導體裝置之電極焊墊之下,以及用以固定基 板之焊球直接形成於介層孔之下時,可以避免介層孔連接 發生斷路,故可以獲得較為可靠之半導體封裝。 此外,更參考其他物理性質檢驗出最佳化值。亦即,
2143-7057-PF 10 1259045 當T°c溫度之彈性模數係為Dt ( GPa ),fc—ϋ之斷裂強度 係為HT ( MPa),有下列不等式關係。 E»23 - 5 :基層絕緣膜之數值低於5時,於半導體封裝組 立時之移動性不佳,因此,此種薄膜沒有實用性。
Dm - 2. 5 :基層絕緣膜之數值低於2· 5時,其接線連 接性質將不;1 ’因此,此種薄膜沒有實用性。為滿足此不 等式’必須渗入具有玻璃轉移溫度至少為l5(rC2樹脂之 強化纖維。 (Dw/ Dm) $ 3.0 :當數值大於此時,高低溫下之彈 性核數之變異將變大。基層絕緣膜之數值大於3· 〇時,由 於半導體封裝組立中反覆的加熱與冷卻所生之應變應力使 侍半導體封裝產生翹曲,因此,此種薄膜沒有實用性。
Hu-140:基層絕緣膜之數值低於14〇時,不利於處理 2〇/zm厚之接線板之半導體封裝之組立,因此,此種薄膜 沒有實用性。 ' (H w/Hiso ) $ 2. 3 :當此數值較大,高低溫下之斷裂 強度之變異將變大。基層絕緣膜之數值大於2.3將特別不 利於高溫之機械強度,因此,基層絕緣膜將些微破裂於諸 如接線連接之半導體封裝組立流程中,故此種薄膜沒有實 用性。 因此,只有當這些因素能夠整合時,才可能獲得可靠 的接線板。 當樹脂’亦即,耐熱樹脂具冑150°C以上之玻璃轉移 溫度’且制具有厚度方向之熱膨脹係數約為6Qppm/K,
2143-7057-PF 11 1259045 其包含之玻璃或芳族聚酰胺(ar am id)所構成之強化纖維之 厚度方向之熱膨脹係數約為1〇〇 ppm/K時,可以最佳化此 厚度方向之熱膨脹係數且維持最佳之彈性模數與斷裂強 度0 此時,當強化纖維之直徑小於等於1 〇 // m,具有較佳 形狀之微細介層孔不僅可以使用二氧化碳雷射更可以使用 短波長之UV-YAG雷射形成於基層絕緣膜中。
本發明之接線板可以具有一個或多個接線結構層。各 該接線結構層具有··介於該基層絕緣膜與該上部線路間並 透過該介層孔連接至該下部線路之中間線路;以及一中間 絕緣膜覆蓋該中間線路,並形成連接該中間線路至該上部 線路之其他介層孔於該中間絕緣膜中。因此,可以實現希 望之而密度接線板。 此外,於這些接線板中,形成一凹部於基層絕緣膜之 下表面,並且為了提高以焊料固定具有窄小節距焊墊之半 導體裝置之對位精度,較佳地,下部線路係嵌入凹部,且 下部線路之下表面係較基層絕緣膜之下表面高〇 5〜i〇^m。 再者,當基層絕緣膜之下表面與下部線路之下表面係 共面,以金圖塊等固定具有窄小節距焊墊之半導體裝置 時’可以獲得對位裕度,所以可以增進連接可靠度。 此外,接線板可以具有一保護膜,係形成於基層絕緣 膜之下,並覆蓋下部線路之部分而暴露其他部分。再者, 接線板可以具有-焊料抗㈣,覆蓋上部線路之部分 露其他部分。因此’焊料可以輕易地藉由印刷或類似方;
2143-7057-PF 12 1259045 形成於接線板上Γ並且^ 置時由炫接將I導體纟置上之焊料與纟等之金屬 鬼連接至接線板上焊料,故可以獲得具有優良凸塊接合 之半導體封裝。 可乂將半導體裝置連接至下部線路或上部線路以製造 使用上述接線板之半導體封裝。此外,可以設置連接端子 以連接諸如電路板之外部裝置。 本發明可以提供一接線板,藉由使用與基層絕緣膜具 •冑低溫度相依機械性之絕緣膜,可以實現高速傳輸與高密 度之微細接線,且承受半導體裝置操作時之反覆熱負荷 夺不a於基層絕緣膜、焊球或類似物上形成破裂現象, 並與介層孔有優良可靠之連接。 【實施方式】 以下,本發明之各實施將搭配圖式詳細說明之。首先, 說明本發明之第一實施例。第4圖係顯示本發明第一實施 例所示之接線板之剖面圖,第5圖係顯示第一實施例所示 _ 之半導體封裝之剖面圖。 如第4圖所示,本實施例之接線板13具有一基層絕緣 膜7基層絕緣膜7係由一财熱樹脂所構成,其玻璃轉移 溫度係150°C以上,並包含玻璃或芳族聚酰胺(aramid)所 構成之強化樹脂。基層絕緣膜7之厚度係為2〇〜1〇〇#m, 若其T°C溫度之彈性模數係為Dt ( GPa ),T°C溫度之斷裂強 度係為Ητ ( MPa),則具有下列(丨)〜(6)項之物理特性。 (1 )厚度方向之熱膨脹係數係為90ppm/k或以下;
2143-7057-PF 13 1259045 (2 ) D23 ^ 5 » (3) Diso^ 2. 5 ; (4) ( D-65/ Dl5〇) <3 Q ; (5) H23^ 140 ; 50 6 ) ( H-65/H1 玻璃轉移溫度為15(rca上之耐熱樹脂較佳地係為可 以摻雜強化纖維之環氧樹脂,但是polyimide樹脂、 cyanate樹脂、液晶聚合物或類似材料亦可使用。 凹部7a係形成於基層絕緣膜7之下表面,線體6係分 別形成於凹部7a中,且㈣終止層5係分別形成於線體6 下蝕亥J、's止層5與線體6形成下部線路,而下部線路係 t於凹4 7a中。#刻終止層5之下表面係暴露形成接線板 13之下表面之部分。線體6係由銅、錦、金、鋁、或鈀等 戶:構成’且厚度為〇.卜7.0"m。蝕刻終止層5之下表面係 门於基層絕緣膜7之下表面〇. 5〜1Q/z m,亦即,姓刻、终止 層5之下表面係位於凹部7a之深處。 此外,I層孔1 〇係分別形成於基層絕緣膜7中而位於 凹部7a之上側之部分。當接線板13係用於CSPs
UhiP-size packages)之半導體封裝時介層孔ι〇之直 徑係如75#m,而當接線板13係用於FCBGAs(fHp_chip baU gridarrays)之半導體封裝時介層孔^之直和係 如4〇“。再者’介層孔10係填充導電材料,且上部線路 11係形成於基層絕緣膜7上。介層孔1〇與上部線路 之導電材料係形成為-體。上部線路u之厚度係如2】
2143-7057-PF 14 1259045 # 111,並透過介層孔1 〇連接至下部線路。甚. Μ 1 9及π丄 甚者,焊料抗蝕 曰2係形成於基層絕緣膜7上並暴露出上部線路u之部 二而,之部分則為焊料抗#層12所覆蓋。焊料抗姓層 之尽度係如5〜4Mm。上部線路u暴露之部分係作為焊 聖*電極。 接著’說明本實施例之半導體封裝之配置。本實施例 中之半導體封们9,複數個凸塊14係分 13之_終止層5,如第5圖所示。半導體裝置 接線板13之下,半導體裝置15之電極(未顯示)係分別 連接凸塊14。半導體裝置15係例示LSI ( large scale integrated circuit)。接線板13與半導體裝置15間之凸 塊14之周圍係填入填充層16。焊球18係設置於接線板u 之上部線路1丨之暴露部分,亦即,焊墊電極之部分。焊球 1 8係透過上部線路丨丨、介層孔丨〇 (見第4圖)、線體6與 蝕刻終止層5構成之下部線路、以及凸塊14連接至半導體 裝置15之電極。半導體封裝19係藉由焊球18固定於封裝 基板(未顯示)。 本發明之個別結構之關鍵值將描述如下。 基層絕緣膜之原度:20〜100丨/ m 當基層絕緣膜之厚度小於2 0 # m,耐熱樹脂無法有效 地容置玻璃或芳族聚酰胺(arami d)所構成之強化纖維。相 反地,當基層絕緣膜之厚度大於1 〇〇 # m,使用雷射處理形 成介層孔之可實施性將大幅降低,而無法形成微細之介層 孔。因此,基層絕緣膜之厚度係設定為20〜1 00 // m。 2143-7057-PF 15 1259045 美羞」厚度方向u膨脹係數:9〇Dpm/k蛊以 若基層絕緣膜之厚度方向之熱膨脹係數大於 90ppm/k,當介層孔直接形成於用以固定半導體裝置之電極 知墊且基板封裝用之焊球直接形成於介層孔上,如第5 图所示之介層孔之接點1 〇 a將因熱循環測試下因半導體裝 置之運作之假設反覆所產生之熱負荷產生空缺陷。因此, 基層絕緣膜之厚度方向之熱膨脹係數設定為90ppm/k或以 Φ 下。 23°C之彈性槿數:5GPa成以卜 當基層絕緣膜於23°C之彈性模數係小於5GPa,包含 2 〇 # m厚之基層絕緣膜之接線板於半導體封裝組立時移動 性不佳,將大幅降低生產率。因此,基層絕緣膜於23°C之 彈性模數設定為5GPa或以上。 基i絕緣膜於1 50°C之彈性模數:2· 5GPa或以上 於單一材料構成之基層絕緣膜中,當基層絕緣膜於j 5〇 _ C之彈性模數為1 · 〇GPa以上,通常可以獲得優良之接線連 接特性。然而,由包含玻璃或芳族聚酰胺(aramid)之強化 纖維之樹脂所構成之基層絕緣膜中,由於強化纖維於15〇 C之彈性模數係高於1 〇GPa,即使基層絕緣膜於工5〇它之彈 性模數為1. OGPa,樹脂於1 50 °c之彈性模數將低於 〇· 1 GPa。因此,當進行接線連接時,線體6將被壓縮,如 此將無法形成具有高強度之接線連接。有鑑於此,以實驗 里測1 5 0 C之基層絕緣膜之彈性模數與接線連接強度之關 2143-7057-PF 16 1259045
係,發現當150°C之彈性模數為2.5GPa可以得到較佳之接 線連接特性。因此,基層絕緣膜於1 5(rc之彈性模數設定 為2· 5GPa或以上。此外,為達到於15(rc之彈性模數為 2· 5GPa或以上,發現混入強化纖維之耐熱樹脂之玻璃轉移 溫度必須為150 °C以上。玻璃轉移溫度係符合JIS (Japanese Industrial Standard)並由 DMA (dynamic mechanical analysis)量測。
羞·T°C溫度之基層絕緣膜之彈性模數為D/ GPa ),Γ U φ Di5〇 ) : 3· 0 或以下 (D_65/ Disg)之值越大表示彈性模數於高低溫之變異 越大。曰本專利申請第2003-382418號中有如此描述,當 (D_65/ D15。)之值越大,連接至接線板之焊球會破裂,因 此(D-65/ Dl5G )之值必須小於4· 7。然而,當(D-65/ Dl50 ) 之值大於3.0時,半導體封裝組立時反覆的加熱與冷卻對 接線板之熱應力會使得半導體基板本身翹曲。所以,(j) 65/ Dl5G )係為3· 0或以下。 # gj°c之基層絕緣膜之斷裂強度:1 4ΠΜΡ。或以上 具有20/z m厚之基層絕緣膜之接線板,當23〇c之基層 絕緣膜之斷裂強度小於14〇MPa,基層絕緣膜於半導體封裝 組立搬運時會破裂。因此,23°C之基層絕緣膜之斷裂強度 設定為140MPa以上。 ^~T Cj度之基層絕緣膜之斷_強唐為HT ( GPa ), (H-65/H150) : 2· 3 或以下 (Η-μ/Ηβο )之值越大表示斷裂強度於高低溫之變異越 2143-7057-PF 17 1259045 大。日本專利申請第2003-38241 8號中有如此描述,當 (H-65/Hm)之值越大’基層絕緣膜會破裂,因此(H 65/Hi5〇) 之值必須小於4.5。然而,當(H 65/Hi5〇)之值大於2·3時, 局溫时基層絕緣膜之機械強度將巨幅降低,因此,於半導 體封裝於高溫組立時,例如接線結合,基層絕緣膜將輕微 破裂。所以,(H-65/H15Q)係為2· 3或以下。 h卩導緣^基層絕綾膜之下表面間之距離: 0. 5〜1 〇 // m Φ S下部線路之下表面與基層絕緣膜之下表面間之距離 小於〇· 5//m,將無法避免凸塊的位置偏移。另一方面,當 距離超過10 β m,當半導體裝置固定至接線板時,基層絕 緣膜與半導體裝置之縫隙將縮小。因此,於半導體裝置固 疋後,於縫隙内填充未充滿(underfilling)樹脂以形成填 充層將顯得困難。所以,此距離較佳地係為0.5〜10//m。 本實施例之半導體封裝1 9中,半導體裝置1 5係藉由 焊球18、上部線路丨丨、介層孔丨〇、線體6與蝕刻終止層5 φ 構成之下部線路、以及凸塊14,自固定基板(未顯示)提 供電源以及輸出入信號予半導體裝置。同時,半導體裝置 15產生熱,且熱透過接線板13傳遞至固定基板。由於半 導體裝置15與固定基板之熱膨脹係數之差異於凸塊14、 接線板1 3、以及焊球丨8產生熱應力。因此,當半導體裝 置15反覆運作與停止,熱應力亦反覆產生於凸塊14、接 線板1 3、以及焊球1 8。 依據本實施例,由於基層絕緣膜之厚度為20〜100 // m,
2143-7057-PF 18 1259045 =二彈性模數係為—研-之斷裂強度為 _a以上’ 15〇t之彈性模數係為2鳥以上,若τ C溫度之彈性模數為Dt,(“/ Di5。)小於3.。,若代溫 度之斷裂強度為ht,(hwh15。….3以下,基層絕緣膜 t搬運性與接線連接特性較適於半導體封冑19之組立製 私而可以製造出無麵曲且高品質之半導體封裝19。此外, 由於基層絕緣膜之厚度方向之熱膨脹係數㈣9GPPm/k或 、下即使熱循%測試下因半導體褒置之運作而假設反覆 產生之熱負荷’亦可以避免於第5圖所示之介層孔之接點 1 〇a產生空缺陷。 〃再者,因為餘刻終止層5與線體6構成之下部線路係 係位於凹部7a,以及下部線路之下表面係高於基層絕緣膜 7之下表面0.5〜1〇 ,將可能避免凸塊14連接時位置偏 移與凸塊流動。所以,凸塊14具有優良之連接可靠性並可 以提供微細之節距,而允許固定高速之半導體裝置丨5。
甚者,由於接線板13沒有穿孔,因穿孔所引發之問 題,亦即阻抗控制的困難以及迴路電感的增加將不會發 生,而可以達成高速傳輸以及高密度微細導線之設計。 於本實施例中,填充層16可以省略。此外,倒裝片式 半導體封裝通常不需模鑄,本實施例之半導體封裝亦不需 模鑄。然而,當半導體封裝需要較高等級之防潮可靠度, 當半導體裝置需要提高密封性質,以及需要提高半導體封 裝之機械強度即使接線板很薄,則可以於接線板13之下表 面模鑄以覆蓋填充層16與導體裝置15。 2143-7057-PF 19 1259045 再者,於第一實施例中,已例示以倒裝型接合固定於 凸塊14之半導體裝置15,但是半導體裝置之定固定方式 並不限於此,連線焊接、膠帶自動接合等亦適用。
接下來說明本實施例之變形。第6圖係顯示第一實施 例所示之另一半導體封裝之剖面圖。本變形之半導體封 裝,如第β圖所示,半導體裝置係分別固定於接線板13之 兩側。亦即,除半導體裝置15透過凸塊14連接至下部線 路,半導體裝置l5a亦透過凸塊14a連接至上部線路u。 半導體裝置15之部分電極透過凸塊14、#刻終止層5盘 線體6構成之下部線路、介層孔1()、上部線路u、及凸塊 14&連接至半導體裝置15a (未顯示)之電極。除上述部分 之結構係相同於第一實施例。因&,根據本實施例,可能 將二個半導體裝置固定於單_接線板13。 日/妾著,說明本發明之第二實施例。第7圖係顯示本發 第實施例所不之接線板之剖面圖,第8圖係顯示第二 實施例所示之半導體封裝之剖面圖。 :第7圖所示,本實施例之接線板21具有基層絕緣膜 土曰絕緣膜7之厚度與機械性質係相同於第—實施例之 基層絕緣膜7。凹部7a带#认# α 形成於基層絕緣膜7之下表面,線 體6形成於凹部7 φ 之中餘刻終止層5形成於線體6之上。 下部線路係由蝕刻終止芦 也山 、θ 5與線體6所構成,且下部線路 ^ 蝕刻終止層5與線體Θ之配置係相同於 弟一實施例。 、 介層孔 1 〇係形成於基層絕緣膜7中並位於凹部7a之
2143-7057-PF 20 1259045 上側之部分。介層孔1 〇係填入導電材i 形成於美声绍故 具入導電材科’中間線路22係 、:曰、、’邑、味膜7上。介層孔1〇與中間線路Μ中之導 電材料係形成為一體,中間複 蒞τ間綠路22透過介層孔1 0連接至 二 =路。此外,中間絕緣膜23形成於基層絕緣膜7上以 旻盍Μ導線22 ’介層孔24係形成於中間絕緣膜23中並 ^,中間導線22上側之部分。介層孔24係填入導電材料, 上部線路11形成於中間絕緣膜23上。介層孔24與上部線
路中之導電材料係形成為—體,上部線路η透過介層 孔24連接至中間導線22。再者,焊料抗钱層㈣成於中 間絕緣膜23上以暴露出上部線路J】之部分,並覆蓋上部 線路11之其他部f上料路u暴露之部㈣作為焊墊 電極。中間絕緣膜23之厚度與機械性質較佳地係相同於基 層絕緣膜7,但亦可以不同於基層絕緣膜7。 此外,第二實施例之接線板中,絕緣膜具有二層,但 是本發明並不限於此結構;接線板亦可以有三層以上之絕 緣膜。 接著,說明本實施例之半導體封裝結構。本實施例之 半導體封裝2 5,如第8圖所示,複數個凸塊丨4係連接至 接線板21之蝕刻終止層5。半導體裝置15係位於接線板 21之下,半導體裝置15之電極(未顯示)係連接凸塊I*。 半導體裝置 15 係例示[SI ( large scale integrated circuit)。接線板21與半導體裝置i5間之凸塊i4之周圍 係填入填充層16。焊球18係設置於接線板21之上部線路 11之暴露部分,亦即,焊墊電極之部分。焊球18係透過
2143-7057-PF 21 1259045 上部線路11、介層孔2、中間if ” 6與蝕刻““ 中間導線22、介層孔1〇、線體 導體成之下部線路、以及凸塊14連接至半 導體封# 未描述於上之本實施例之接線板與半 導體封褒之結構與運作係相同於第一實施例。 牛 Η蜗:本時實施例中’接線板21為包含基層絕緣膜7與中 間絕緣膜23之-声砝谣介Β 、Τ 板,接^ 亦即,不同於第—實施例之接線 =線广有中間導線22,因此,可以增加輸出入 ^置15之信號量。本實施例所未描述之效果係 於弟一實施例。 太辂a著說明本發明之第三實施例。第9Α〜9C圖係顯示 —實鈿例所不之製造接線板流程以及配置之叫面 圖二實施例之接線板,基層絕緣膜7之下表面與蚀刻終 曰及線體6所構成之下部線路之下表面係共面。㈣ 膜4!形成於基層絕緣膜7上。保護膜41係如環氧樹脂或 P〇iylmide樹脂’其厚度係如卜5〇“。㈣膜41具有— 作為開口之_部42。亦即,保護膜41使得下部線路之 部分於敍刻部42暴露出來,而下部線路之其他部分則為不 包含蝕刻部42之其他保護膜41所覆蓋。當半導體裝置固 定於接線板,蚀刻部42係連接至凸塊14 (見第Η圖)之 部分。未描述於上之本實施例之接線板與半導體封裝之結 構與運作係相同於第一實施例。 於本實施例巾,可以使㈣賴41以增強用以黏接接 線板與樹脂層之填充層。本實施例所未描述之效果係相同 於第一實施例。
2143-7057-PF 22 1259045 —接著,說明本發明之第四實施例。第Ϊ0圖係顯示本發 明第四實施例之接線板之剖面圖。如第10圖所示,不同於 第一實轭例之接線板,本實施例之接線板不具有保護膜41 (見第9圖)。因此,下部線路之下表面不為接線板“之 下表面壓縮,亦即,下部線路之下表面與接線板43之下表 面共面。本實施例所未描述之接線板與半導體封裝之結構 與運作係相同於第三實施例。 不同於第二實施例之接線板,本實施例之接線板不具 有保護膜’因此,生產成本可以降低。此外,+同於第一 實施例所述,可省略形成易㈣層4 (見第ι圖),所以可 以降低生產成本。考量生產成本,本實施例之接線板適用 於以下狀況:帛導體裝置之電極節距不會過於窄小;若凸 塊14被度(見第4圖)不高而不需要高定位精度;禱模與 接線板間不需黏接而不論是否有鑄模。本實施例所未描述 之效果係相同於第一實施例。 ,,接著,說明各實施例之接線板與半導體封裝之製程。 首先說明第-實施例之接線板與半導體封裝之製程。第 iia〜ue圖係顯示本發明一實施例所示之製造接線板流程 之剖面圖。第m# 12B圖係顯示本發明一實施例所示之 製造半導體封裝流程之剖面圖。帛12C圖係具有鑄模之半 導體裝置之剖面圖。如帛11A圖所示,準備一個由例如銅 等之金屬或合金所構成支撑結構i,形成光阻2於支料 構1上以形成圖案。接著,例如藉由電鍍,依序形成易姓 刻層4、㈣終止層5、以及線體6。同時,於支撐結構上
2143-7057-PF 23 1259045 光阻2移除之區域形成由易蝕刻層4、蝕刻終止層5、以及 線體6所構成之導線層3,而不形成於光阻2遺留之區域。 易蝕刻層4係為由單一層銅所構成之電鍍層、銅與鎳所構 成之雙電鍍層、或單一層鎳所構成之電鍍層,其厚度係為 〇.5〜10# m。雙電鍍層中之鎳層係用以預防高溫時易蝕刻層 4之銅層與蝕刻終止層5間之擴散,其厚度係為以 上。蝕刻終止層5係為電鍍鎳層、電鍍金層、或電鍍鈀層, 其厚度係為0.1〜7.0//m。線體6係由電鍍導電層所構成, • 例如:銅、鎳、金、鋁或鈀,其厚度係為〇〜2〇//m。此外, 當蝕刻終止層5係由金所構成,蝕刻終止層5與線體6間 形成有錄層以避免姓刻終止層5與銅線體6間之擴散。 如第11B圖所示,光組2已除去。如第nc圖所示, 形成基層絕緣膜7以覆蓋導線層3。形成基層絕緣膜7之 方法係如下所例示:疊合層狀絕緣膜與支撐結構丨,或壓 合層狀絕緣膜至支樓結構丨上;以1〇〇〜4〇〇。〇之溫度熱處 理10分鐘至2小時;最後硬化之。熱處理之溫度與時間係 • 根據絕緣膜之種類而定。此外,介層孔10係藉由雷射處理 形成於基層絕緣膜7上並位於導線層3之上側部分。 如第11D圖所不,介層孔1 〇係填充導電材料,上部線 路11形成於基層絕緣膜7上。同時,上部線路u透過介 層孔10連接至線體6。當接線板13係用於csps (chip-size packages)之半導體封裝時,介層孔ι〇之直 徑係如75/zm,而當接線板13係用於FCBGAs(fHp_chip ball grid arrays)之半導體封裝時,介層孔1〇之直徑係 2143-7057-PF 24 1259045 m了嵌入於介π ir之導電材料以及上部線路u 為2錦金m所構成,上部線路u之厚度係 : 焊料抗蝕層12覆蓋上部線路11之部分並晨 露出其他部分。焊料f 4 刀知枓抗敍層12之厚度係為5〜4〇々m。然而 了以不形成焊料抗蝕層12。 移☆如LUE圖所示’支推結構1係藉由化學姑刻或抛光 示 者,如第4圖所示,以蝕刻移除易蝕刻層4。咭 :形成如第4圖所示接線板13。同時,若支撐結構1之; 料不同於易餘刻層4’則需進行二次上述 支撐結構1之封粗…、向右 再1之材科荨同於易钱刻層4,則僅需進行一次蚀 刻0 M 所示’複數個凸塊14分別連接至㈣終止 曰5之暴露部分。接著以倒裝方式藉由凸塊14固定半導體 裝置15至接線板13,以連接半導體裝置丨5(未顯示)之 電極至凸塊14。 斤不於接線板1 3與半導體裝置1 5注入 填充層1 6並固化夕。^ β 之如此將使侍凸塊14嵌入填充層16。 然而填充層16可以省略。此外,如帛12C圖所示,鑄膜 、車乂佳地係形成於接線板i 3之下表面以覆蓋填充層⑶與 半導體裝置15。 接著’如第5圖所示’形成焊球1於接線板13之上部 線路11之暴露部分。如此形成第5圖所示之[實施例之 半導體封纟1 9。於第—實施例中,可以增進接線板i 3於 銅所構成之硬貝支撐結才冓i上形成導線層3、基層絕緣膜
2143-7057-PF 25 1259045 7、上部線路11等之平坦度。 — 於第一實施例中,係例示使用金屬或合金作為支撐結 構1,然而,諸如矽晶圓、玻璃、陶瓷或樹脂等絕緣體亦 可作為支撐結構1。當使用絕緣體時,導線層3可以在光 阻2形成後以無電極電鍍形成,於光阻2形成後可以使用 無電極電鍍、濺鍍或汽相沉積法形成供能導體層,接著以 電鍍法形成導線層3。 此外,於本實施例中,係描述以倒裝方式將半導體裝 置15固定至接線板13,然而,半導體裝置15亦可以藉由 其他方法’如:連線焊接以及膠帶自動接合,固定至接線 板1 3 〇 接著’說明第二實施例之製造接線板以及半導體封」 之方法。第13A〜13D圖係顯示本發明二實施例所示之製: 接線板以及半導體封裝流程之剖面圖。首先,於支撑結; 1上形成由易餘刻層4、姓刻炊 ^ a 止層5以及線體6所構成- 導線層3,形成基層絕緣膜7蓿 、 覆盍導線層3,以及藉由: 第 至11C圖所示之方法开^出 万成介層孔10於基層絕緣膜 接著,如第13Α圖所 # ^ ^ ^ ^ 將導電材料填入介層孔1 0 並形成中間線路22於基層絕緣 〇〇^ ^ 緣膜7上。同時,中間線; 22透過介層孔1〇連接至 Ψ λ Φ Η ® ^ 、 · 6。之後,如第13Β圖所示 形成中間絕緣膜23覆苔 w復盖中間線路22。 之方式係相同於形成基層絕緣?中間:緣膜 於中間絕緣膜23中並使其位於 工。形成”層孔 、中間線路2 2之上側之部名
2143-7057-PF 26 1259045 接著’如第13C圖所示,將ϋ材料填入介層孔24, 並形成上部線路11於中間絕緣膜2 3上。同時,上部線路 11透過介層孔24連接至中間線路22。然後,形成焊料抗 蝕層1覆蓋上部線路11之部分,並暴露其他上部線路。之 後,如第1 3D圖所示,以化學蝕刻或拋光移除支撐結構工。 接著,如第7圖所示,以蝕刻移除易蝕刻層4。如第7 圖所示,形成本實施例之接線板21。
此外’如第8圖所示’複數個凸塊14連接至#刻終止 層5之暴露部分。半導體襄置15係以倒裝方式透過凸塊 14固定至接線板21,使得半導體裝置15之電極(未顯示) 連接至凸塊14。於接線板21與半導體裝置15間注入填充 層16並固化之。如此將使得凸塊14嵌人填充層16。焊球 18連接至接線板21之上部線路u之暴露部分。如第“ 圖所不,形纟本實施例之半導體封$ 25。如@第一與第二 實施例’可以不形成填充層16。或者,鑄膜可以形成於: 線板21,上表面以覆蓋填充層16與半導體裝置以。 接著,說明第三實施例之製造接線板之方法。首先 圖所示,藉由疊合或壓合,形成保護膜Ο於支揮 ::整個上表面。然後以跡錢之溫 刀鐘至2小時以硬化保護膜41。熱處理之溫度與 據保護膜41之材料錄_ & + ^ ’、根 “。 材枓種類而定。保護膜41之厚度係如卜5〇 接著,形成光阻(未顯示)於保護膜41 形成由蝕刻終止層5與線體6所構成之下 上以形成圖案。 部線路於光阻移
2143-7057-PF 27 1259045 除之區域。再;^,形成i豕絕緣辰7以S蓋下部線路,形 成介層孔1 0於基層絕緣膜7中,將導電材料填入介層孔 1 〇中,並形成上部線路於基層絕緣膜7上。之後,形成焊 料抗蝕層以覆蓋上部線路11之部分。 接著,如第9B圖所示,移除支撐結構1。然後,如第 9C圖所示,以蝕刻法選擇性移除保護膜4丨,並使下佈線路 於#刻部42,亦即保護層41被移除之處,暴露出來,而 形成本實施例之接線板。此外,凸塊丨4 (見第4圖)係連 • 接至餘刻部42,以固定半導體裝置15 (見第4圖),以及 於接線板與半導體裝置15間注入填充層16 (見第4圖)。 之後,焊球18 (見第4圖)連接至上部線路丨丨。如此,形 成本實施例之半導體封裝。未描述於上之本實施例之接線 板與半導體封裝之製造方法係相同於第一實施例。 於各實施例中,係例示於最後移除支撐結構丨,然而, 本發明並不限於此。例如,僅移除支撐結構丨之部分,保 留其餘之部分,而此其餘之部分可以作為強化結構。此外^ 籲-次將支撐結構1完全移除後,可以將—個強化結構固定 至接線板。 如上所述,本發明之各個實施例之接線板、製造該接 、線板之方法、基層絕緣膜、以及半導體封裝已搭配圖式說 日月之,然而’本發明之特定配置並限於上述之第一至第四 實施例,在不脫離本發明之牿妯々 月芡精神與乾圍内仍可為設計之變 化。 接下來,將與未描述於#I% 不赞明之申睛專利範圍之比較
2143-7057-PF 28 1259045 例相比較說明本發明之效果。第u圖-係^^^ 半導體封裝之剖面圖。 如第14圖所示,具有二個絕緣膜之接線板21係藉由 如第二實施例所示之方法所製造。然後半導體裝置15a以 倒裝方式固定至接線板21以形成填充層16。半導體裝置 15b藉由固定材料26設置於半導體裝置上,並藉由連 線焊接形成導線27連接至接線板21。之後,形成禱膜Η
以覆蓋半導體裝置15a與15b,,並提供焊球18以製造用 以測忒用之半導體封裝。半導體封裝之數據係載於表^。 (表1) 半導體裝 半導體裝尺寸 封裝尺寸 BGA球之數目 BGA球之節距 絕緣膜之層數 ------- 如第14圖A區段所示,測試用一部 分使半導體裝置15a固定至凸塊14,介層孔1()與24,以 =:18皆垂直對齊。此外’如B區段所示,半導體封裝 有—部分使得介層孔1()與24,以及焊球18非垂 、,狀 <機械性買,亦 P,斷4強度、彈性模數、以及 孫蔣料i 辦裂後伸長比率。此量現 係將、、、邑緣膜切割為寬lcm之長 保並進行符合” JPCA #
2143-7057-PF 29 1259045 準,組合式接線板,JPCA-BU01,4. 2節: 測溫度係設定為三個標準-65°C、23°C及 係如表2所示。 之拉力測試。量 150°C。量測結果
2143-7057-PF 30 1259045
2143-7057-PF 31 對照樣本 對照樣本 對照樣本 對照樣本 樣本 樣本 樣本 樣本 CO oo CD CJl CO DO 1—^ 號碼 芳族聚酰胺 (aramid) 芳族聚酰胺 (aramid) 芳族聚酰胺 (aramid) 玻璃 芳族聚酰胺 (aramid) 芳族聚酰胺 (aramid) 芳族聚酰胺 (aramid) 芳族聚酰胺 (aramid) 玻璃 強化纖維 t—^ οι INO IND OO CsD DO oo to 1—^ CD OO H-^ H-* oo CO to to CD 斷裂強度 Mpa CT> •CD CD 私 12.2 -<I CJl oo 私 CO <=> CO H—^ h—^ OO 彈性模數 -65〇C, Gpa CO GO OO CJ5 oo to OO to oo oo CD GO to h—i GO 斷裂後伸 長比率 GO to CO oo CO U1 CJl CO CT> C=> Η-* CJl cn h—* 1—^ oo CO oo CJl 斷裂強度 Mpa 产 to •oo CD oo 1—^ H—* cn •U1 c=> •cn oo cn 03 私 10.5 彈性模數 23〇C,Gpa •GO l—i C=> CO JND h- •CO oo GO CT> GO OO OO CO 斷裂後伸 長比率 i_ CT> σ> H—A g OO oo OO CD CO A h—k IND to H-^ CT> C5 斷裂強度 Mpa 1_ r° d> 4^ OO CO JND CJl GO <〇 CO CD GO CO oo 彈性模數 150°C,Gpa CO CJl Η—λ 4^ CO JND 1—^ GO GO GO CO O 斷裂後伸 長比率 CD CJl H- <X> CD g oo g ?〇 厚度方向之 熱膨脹係 數,ppm/k ϊ 2) 1259045 此外,測試樣本之溫度依存性係ιϋ 计异得出。亦即,(D-65/Dl5G)與(Η-65/Η150) °C溫度之彈性模數係為dt ( Gpa),rc溫度之 Ητ ( Mpa)。計算結果如表3所示。 2之機械性質 之值,其中T 斷裂強度係為
2143-7057-PF 32 1259045
2143-7057丨 PF 33 對照樣本 對照樣本 對照樣本 對照樣本 樣本 樣本 樣本 樣本 樣本 CO oo -<1 cn GO 號碼 IND cn I—»· σί 1—1 CJ1 1— cn tNO CO DO 1—^ IND CZ5 h— 〇〇 1—^ ΟΊ D-65/ Dl50 -Si CO INO CsO IND CsD ISO GO ◦ IND OO IND cn IND 1—^ Η-6δ/Ηΐ50 It 超過1500 1250 1000 1100 超過1500 超過1500 超過1500 超過1500 超過1500 介層斷路,區段 A 單一半導體封裝 熱應力财用性(損壞之循環次數) 超過1500 超過1500 超過1500 超過1500 超過1500 超過1500 超過1500 超過1500 超過1500 介層斷路,區段 B CD cn ◦ 超過1500 超過1500 超過1500 超過1500 超過1500 超過1500 超過1500 超過1500 接線斷路 超過1000 ◦ g ◦ ◦ 超過1000 超過1000 超過1000 超過1000 超過1000 介層斷路,區段 A 固定於基板之封裝 超過1000 超過1000 超過1000 超過1000 超過1000 超過1000 超過1000 超過1000 超過1000 介層斷路,區段 B g 超過1000 超過1000 超過1000 超過1000 超過1000 超過1000 超過1000 超過1000 接線斷路 ί 3) 1259045 接著,4 m 熱應力之耐用性之量測係使用單一半導體封裝與固定於封 裝板之半導體封裝。單一半導體封裝係置於熱循環測試, 基本循環係樣本置於-65°C之溫度30分鐘,再置於15(rc 之温度30分鐘,如此重複一預設次數。此外,固定於封裝 板之半導體封裝係置於熱循環測試,基本循環係樣本置於 一45°C之溫度30分鐘,再置於125t:之溫度3〇分鐘,如此 重複一預設次數。接著量測各樣本之電連接斷路,亦即, _ 斷裂發生之循環次數。樣本溫度由低溫(—65〇c或—45它) 改變至高溫(15(TC或125°c )之轉移時間,以及樣本溫度 由高溫改變至低溫之轉移時間係取決於熱循環測試機之性 能與樣本之熱容量。 至於半導體裝置之熱應力之耐用性之量測,當熱循環 測試係於實際使用條件(251至7(rc )下進行,將花費長 時間進行測試。因此,樣本係於(—6yc至l5(rc )或(一4〇 〇至125(3)之熱循環進行加速測試。使用£1八41-£1'-7404 _ 中之Coffin — Manson方程式(1 999,4月)計算溫度循環 測試之加速性質,-40°C至125°C之熱循環,其加速性質係 高於實際使用條件(25°C至70°C,1循環/天)5. 7倍。因 此’(-40°C至125°C )溫度下之600次循環相當於實際使 用條件下之1 〇年。 熱應力之耐用性之測試結果如表3所示。表3中之” 介層斷路,區段A”與”介層斷路,區段B”表示第14 圖所示之區段A與區段B所包含之介層孔連接發生斷路。
2143-7057-PF 34 1259045 —-------------------—____________________________________________ — 此外,”接線斷路,,表示電連接第14—圖—所示之半導體裝置 1 5b與接線板21上之蝕刻終止層5之導線3〇發生斷路。 此外,”超過1 500”與,,超過1 000”表示斷路分別發生於 1 5 0 G次與1 〇 〇 〇次熱循環之後。 表2與表3中之第1至5號樣本係為本發明之實施例。 實施例之樣本,由於厚度方向之熱膨脹係數係9〇ρριη/κ或 以下區段Α之介層孔連接不會發生斷路,其中凸塊14、 介層孔10與24、以及焊球18係垂直排列,因此,熱應例 之耐久性極佳。再者,實施例之樣本。23。(:下絕緣膜之彈 性模數為5GPa或以上,15(rc下絕緣膜之彈性模數為 2.5GPa或以上,23艺下絕緣膜之斷裂強度為或以 上(D-65/ Dl5°)為3.0或以下,沒有斷路發生於導線連接 處,且整個半導體封裝之熱應力之耐久性極佳。 :對地表2與表3之樣本第6至9號為對照樣本。 :第6至8號對照樣本之厚度方向之熱膨脹係數為 9〇PPm/K或以上,區段B之介層孔連接無斷路發生,但是, 凸免14 ,丨層孔1〇與24、以及焊球μ垂直對齊之區段b 中之介層孔連接發生斷路,因此,其熱應力耐久性不佳。 纟於第9號對照樣本之厚度方向之熱膨脹係數為 9〇PPm/K或以下,因此,區段A與B之介層孔連接皆無斷 路^生》而,由於第9號對照樣本並不符合23°C下絕緣 ,之彈性模數為5GPa或以上,15。。口之彈性模數為 •5GPa或以上,咖下之斷裂強度$或以上,(“/ )為3’ °或以下’(H-65/Hl5Q)為2· 3或以下之要求,故
2143-7057-PF 35 1259045 .............. —— _____ 其接線接合性質與半導體« ^ 佳。因此’接線結合處會發生斷路,所以整體半導體封裝 之熱應力耐久性並不佳。 【圖式簡單說明】 第1圖係顯示習知、组合式基板之剖面圖; 第2A 2C圖係顯示習知製造印刷電路板流程之剖面 圖, 圖; 第3A與3B圖係顯示習知製造接線板流程之剖面圖; 第4圖係顯示本發明第—實施例所示之接線板之剖面 圖; 第5 係顯示第一實施例所示之半導體封裝之剖 面 第6圖係顯示第-實施例所示之另—半導體封裝之剖 面圖; 第7圖係顯示本發明篦-香% _ 圖, χ乃弟一實轭例所不之接線板之剖面 圖, 第8圖係顯示第二實施例所示之半導體封 裝之剖面 示之製造接線板 第9A〜9C圖係顯示本發明三實施例所 流程以及配置之剖面圖; 第10圖係顯示本發明第四實施例之接線板之剖面圖; 第11A〜11E圖係顯示本發明一實施例所示之製造接線 板流程之剖面圖; 第1 2A與1 2C圖係顯示本發明一實摊 x ^ X她例所示之製造半
2143-7057-PF 36 1259045 導體封裝流程之剖面圖; 第13H3D圖係顯示本發明二實 一 板以及半導體封裝流程之剖面圖;及 不 第14圖係顯示評估測試用之半導體 【主要元件符號說明】 Κ 1〜支撐結構; 2〜光阻; 3〜導線層;
之製造接線 剖面圖。 4〜易餘刻層; 5〜蝕刻終止層; 6〜線體; 7〜基層絕緣膜; 7a〜凹部; 1 〇〜介層孔; l〇a〜接點; 11〜上部線路; 1 2〜焊料抗餘層; 13〜線路板; 14〜凸塊; 15〜半導體裝置; 15a〜半導體裝置; 15b〜半導體裝置; 1 6〜填充層; 1 7〜鑄膜;
2143-7057-PF 37 1259045 18〜焊球; 19〜半導體封裝; 21〜接線板, 22〜中間線路; 23〜中間絕緣膜; 24〜介層孔; 25〜半導體封裝; 2 6〜固定材料, • 27〜導線; 30〜導線; 41〜保護膜; 42〜蝕刻部; 43〜接線板; 71〜穿孔; 72〜導線; 7 3〜核心基板, _ 7 4〜介層孔; 75〜層間絕緣膜; 76〜導線; 82〜預浸材料; 8 3〜通孔; 84〜導電膏; 85〜印刷電路板; 8 6〜聊位圖形; 38
2143-7057-PF 1259045 91〜支撐板; 92〜導線; 93〜層間絕緣膜; 9 4〜介層孔; 95〜導線; 96〜支撐結構; 97〜線路板。
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Claims (1)
1259045 干--------------------------------------------------- 1 · 一種接線板,包含: 一基層絕緣膜,其厚度係為20〜lOO/^m,並具有一介 層孔; 下。卩線路’係形成於該基層絕緣層之下表面上,並 連接至該介層孔;及 一上部線路,係形成於該基層絕緣層上,並透過該介 層孔連接至該下部線路; _ 《中該基層絕緣膜係由—耐熱樹脂構成,該耐熱樹脂 之玻璃轉換溫度係為150°C或以上,並包含玻璃或芳族聚 酰胺(aramid)構成之強化纖維,其rc溫度之彈性模數係 為() ’ T C溫度之斷裂強度係為[Jt ( MPa ),具有下列 (1)〜(6)項之物理特性: (1) 尽度方向之熱膨服係數係為g〇ppm/k或以下; (2) D23 > 5 ; (3) Di5〇> 2. 5 ; (4) ( D - 6 5 / D15 ◦) $ 3 · 0 ; (5) H23- 14〇 ;以及 (6) ( Η - 6 5 / Η15 〇) S 2 · 3。 ^ 2·如申請專利範圍第1項所述之接線板,其中該強化 纖維之直徑係為10/zm或以下。 3·如申請專利範圍第1項所述之接線板,更包含一或 多個線路結構層,各該線路結構層包含·· 一中間線路,設置於該基層絕緣膜及該上部線路間, 2143-7057-PF 40 1259045 —.-----------------------------------------------------------------------_ 並藉由該介層孔連接至兮二 受成下部線路;及 並形成另一介層孔 一中間絕緣膜,霜苔兮+扣 、 復盍叇中間線路, 連接該中間線路至該上部線路。 4·如申晴專利範圍 係形成於該基層絕緣膜 於該凹部。 第1項所述之接線板,其中一凹部 之遠下表面,且該下部線路係嵌置 所述之接線板,其中該下部 緣膜之該下表面〇5〜1〇βπι。 所述之接線板,其中該下部 膜之該下表面係共面。 所述之接線板,更包含一保 下,並覆蓋該下部線路之部 分0
5.如申請專利範圍第4項 線路之下表面係高於該基層絕 6·如申請專利範圍第4項 線路之該下表面與該基層絕緣 7·如申請專利範圍第6項 濩膜,形成於該基層絕緣膜之 分,暴露該下部線路之剩餘部 8·如申請專利範圍第1項 料抗蝕層,係覆蓋該上部線路 剩餘部分。 所述之接線板,更包含一焊 之部分,暴露該上部線路之
9. 一種半導體封裝,包含·· 至8項中任一項所述 一接線板,如申請專利範圍第 者;及 -半導體裝置’ gj定於該接線板上。 …1〇·如申請專利範圍帛9項所述之半導體封裝,其中該 半導體裝置係連接至該下部線路。 ,.μ請專利範圍第9項所述之半導體封裝,其t該 半導體裝置係連接至該上部線路。 2143^7057-PF 41 1259045 ΤΖ ·1口 申 I 辜 一連接端子,用以連接一外部裝置,並連接至該上部線路 與該下部線路。
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JP2004142133A JP4108643B2 (ja) | 2004-05-12 | 2004-05-12 | 配線基板及びそれを用いた半導体パッケージ |
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JP (1) | JP4108643B2 (zh) |
CN (1) | CN100380637C (zh) |
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Publication number | Publication date |
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US7397000B2 (en) | 2008-07-08 |
TW200539776A (en) | 2005-12-01 |
CN100380637C (zh) | 2008-04-09 |
US20080258283A1 (en) | 2008-10-23 |
JP4108643B2 (ja) | 2008-06-25 |
JP2005327780A (ja) | 2005-11-24 |
CN1697163A (zh) | 2005-11-16 |
US7566834B2 (en) | 2009-07-28 |
US20050252682A1 (en) | 2005-11-17 |
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