JP5740372B2 - 半導体メモリカード - Google Patents
半導体メモリカード Download PDFInfo
- Publication number
- JP5740372B2 JP5740372B2 JP2012200159A JP2012200159A JP5740372B2 JP 5740372 B2 JP5740372 B2 JP 5740372B2 JP 2012200159 A JP2012200159 A JP 2012200159A JP 2012200159 A JP2012200159 A JP 2012200159A JP 5740372 B2 JP5740372 B2 JP 5740372B2
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- external connection
- connection terminal
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- lead
- resin layer
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
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Description
図1ないし図3は第1の実施形態による半導体メモリカードを示す図である。図1は第1の実施形態による半導体メモリカードの上面図であって、半導体メモリカードの構成を透過して示す図(上面透過図)、図2は第1の実施形態による半導体メモリカードの下面図、図3は第1の実施形態による半導体メモリカードを長辺方向(カードスロットに挿入する方向)に切断した断面図である。これらの図に示される半導体メモリカード1は、各種規格のメモリカードとして使用されるものである。
次に、第2の実施形態によるメモリカードについて、図11ないし図18を参照して説明する。第1の実施形態と同一部分には同一符号を付し、その説明を一部省略する。第2の実施形態によるメモリカード31は、図11に示すように、封止樹脂層10から露出された外部接続端子3の表面3aおよび側面3b上に設けられた金属めっき層32を備えている。第2の実施形態によるメモリカード31において、基本的な構成は外部接続端子3上に金属めっき層32が設けられていることを除いて、第1の実施形態のメモリカード1と同様とされている。封止樹脂層10の第1の面10aには、外部接続端子3の表面3aおよび側面3bの一部を露出させつつ、外部接続端子3の周囲を囲う凹部15が設けられている。凹部15の具体的な構成等も第1の実施形態と同様である。
Claims (5)
- 複数の外部接続端子と、少なくとも一部が前記外部接続端子に接続された複数のリードを有するリード部と、前記リード部に設けられたチップ部品搭載部と、半導体チップ搭載部とを備えるリードフレームと、
前記チップ部品搭載部に搭載され、前記リードと電気的に接続されたチップ部品と、
前記半導体チップ搭載部に搭載され、前記リードと電気的に接続されたコントローラチップ、および前記コントローラチップと電気的に接続されたメモリチップと、
前記リードフレームを前記チップ部品、前記コントローラチップ、および前記メモリチップと共に封止する封止樹脂層であって、前記外部接続端子の露出面となる第1の面と、前記外部接続端子の表面を露出させると共に前記外部接続端子の側面の一部を露出させつつ、前記外部接続端子の周囲を囲うように前記第1の面に設けられ、かつ前記第1の面からの深さが10〜300μmの範囲である凹部とを有する封止樹脂層と、
前記外部接続端子の露出された前記表面および前記側面に設けられた金属めっき層とを具備し、
前記リードフレームは、前記外部接続端子とは別に、前記封止樹脂層から露出しためっき用接続端子を有し、
前記リードフレームは、前記封止樹脂層の一方の側面に設けられた第1の吊りリードと、前記封止樹脂層の他方の側面に設けられた第2の吊りリードとを有し、
前記半導体チップ搭載部は、前記第1の吊りリードと前記第2の吊りリードとの間で電気的に独立していることを特徴とする半導体メモリカード。 - 複数の外部接続端子と、少なくとも一部が前記外部接続端子に接続された複数のリードを有するリード部と、前記リード部に設けられたチップ部品搭載部と、半導体チップ搭載部とを備えるリードフレームと、
前記チップ部品搭載部に搭載され、前記リードと電気的に接続されたチップ部品と、
前記半導体チップ搭載部に搭載され、前記リードと電気的に接続されたコントローラチップ、および前記コントローラチップと電気的に接続されたメモリチップと、
前記リードフレームを前記チップ部品、前記コントローラチップ、および前記メモリチップと共に封止する封止樹脂層であって、前記外部接続端子の露出面となる第1の面と、前記外部接続端子の表面を露出させると共に前記外部接続端子の側面の一部を露出させつつ、前記外部接続端子の周囲を囲うように、前記第1の面に設けられた凹部とを有する封止樹脂層と
を具備することを特徴とする半導体メモリカード。 - さらに、前記外部接続端子の露出された前記表面および前記側面に設けられた金属めっき層を具備し、
前記リードフレームは、前記外部接続端子とは別に、前記封止樹脂層から露出しためっき用接続端子を有する、請求項2に記載の半導体メモリカード。 - 前記リードフレームは、前記封止樹脂層の一方の側面に設けられた第1の吊りリードと、前記封止樹脂層の他方の側面に設けられた第2の吊りリードとを有し、
前記半導体チップ搭載部は、前記第1の吊りリードと前記第2の吊りリードとの間で電気的に独立している、請求項2または3に記載の半導体メモリカード。 - 複数の外部接続端子と、少なくとも一部が前記外部接続端子に接続された複数のリードを有するリード部と、前記リード部に設けられたチップ部品搭載部と、半導体チップ搭載部とを備えるリードフレームを用意する工程と、
前記チップ部品搭載部にチップ部品を搭載する工程と、
前記半導体チップ搭載部にコントローラチップとメモリチップとを搭載する工程と、
前記コントローラチップと前記リードとを電気的に接続する工程と、
前記メモリチップと前記コントローラチップとを電気的に接続する工程と、
前記リードフレームを前記チップ部品、前記コントローラチップ、および前記メモリチップと共に封止する封止樹脂層を形成する工程と、
前記外部接続端子の表面を露出させると共に前記外部接続端子の側面の一部を露出させつつ、前記外部接続端子の周囲を囲う凹部を、前記封止樹脂層の前記外部接続端子の露出面となる第1の面に形成する工程と
を具備することを特徴とする半導体メモリカードの製造方法。
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CN201310056269.7A CN103681571B (zh) | 2012-09-12 | 2013-02-21 | 半导体存储卡及其制造方法 |
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