TW201411783A - 半導體記憶卡及其製造方法 - Google Patents

半導體記憶卡及其製造方法 Download PDF

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TW201411783A
TW201411783A TW102101518A TW102101518A TW201411783A TW 201411783 A TW201411783 A TW 201411783A TW 102101518 A TW102101518 A TW 102101518A TW 102101518 A TW102101518 A TW 102101518A TW 201411783 A TW201411783 A TW 201411783A
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Taiwan
Prior art keywords
external connection
connection terminal
lead
resin layer
mounting portion
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TW102101518A
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English (en)
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TWI508236B (zh
Inventor
Kazuhide Doi
Soichi Homma
Katsuyoshi Watanabe
Taku Nishiyama
Takeshi Ikuta
Naohisa Okumura
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Toshiba Kk
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

本發明提供一種利用引線架而實現低成本化，並且提高外部連接端子之露出性的半導體記憶卡及其製造方法。實施形態之半導體記憶卡1包括：引線架2，其具有外部連接端子3、引線部4、晶片零件搭載部5、及半導體晶片搭載部6；晶片零件7，其搭載於晶片零件搭載部5；控制器晶片8及記憶體晶片9，其搭載於半導體晶片搭載部6。引線架2係藉由樹脂密封。密封樹脂層10包含凹部15，該凹部15係以使外部連接端子3之正面及側面之一部分露出，並且包圍外部連接端子3之周圍的方式設置於第1面10a。

Description

半導體記憶卡及其製造方法 [相關申請案]
本申請案享有以日本專利申請案2012-200159號(申請日：2012年9月12日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體記憶卡及其製造方法。
作為內置有NAND(Not-AND，與非)型快閃記憶體等之記憶卡(半導體記憶卡)，其小型化與高容量化不斷進步。又，不僅實現記憶卡之高容量化，記憶體晶片本身之高密度化及基於其之高容量化亦得到進步。一般而言，記憶卡係藉由如下方式構成，即，於具有外部連接端子之配線基板上搭載記憶體晶片或控制器晶片等半導體晶片，並且於配線基板上形成密封樹脂層而將半導體晶片密封。進而，為了謀求記憶卡之低成本化等，亦研究有如下方法，即，將記憶體晶片或控制器晶片等半導體晶片與電容器或保險絲等晶片零件搭載於具有外部連接端子之引線架上。
於使用有引線架之記憶卡中，將半導體晶片或晶片零件搭載於引線架上後，形成將引線架與半導體晶片或晶片零件一併密封之密封樹脂層。於形成密封樹脂層時，需要使外部連接端子之正面露出。密封樹脂層例如使用令外部連接端子之正面露出的成形模，並藉由轉移成形等而形成。然而，由於記憶卡之外部連接端子係配置於密封樹脂 層之一正面內，故而例如於密封樹脂層之形成時難以完全抑制樹脂毛邊之產生。因此，外部連接端子之正面之一部分由樹脂覆蓋，從而易導致由外部連接端子實現之與外部機器之連接性降低。
本發明所欲解決之問題在於提供一種使用引線架而謀求低成本化，並且提高外部連接端子之露出性的半導體記憶卡及其製造方法。
實施形態之半導體記憶卡包括：引線架，其包含複數個外部連接端子、具有至少一部分連接於上述外部連接端子之複數個引線的引線部、設置於上述引線部之晶片零件搭載部、及半導體晶片搭載部；晶片零件，其搭載於上述晶片零件搭載部，且與上述引線電性連接；控制器晶片及記憶體晶片，該控制器晶片係搭載於上述半導體晶片搭載部且與上述引線電性連接，該記憶體晶片係與上述控制器晶片電性連接；及密封樹脂層，其將上述引線架與上述晶片零件、上述控制器晶片、及上述記憶體晶片一併密封。上述密封樹脂層包含：第1面，其成為上述外部連接端子之露出面；及凹部，其以使上述外部連接端子之正面及側面之一部分露出、並且包圍上述外部連接端子之周圍的方式設置於上述第1面。
1、31‧‧‧記憶卡
2、2‧‧‧引線架
3‧‧‧外部連接端子
3a‧‧‧正面
3b‧‧‧側面
4‧‧‧引線部
5‧‧‧晶片零件搭載部
5A‧‧‧第1晶片零件搭載部
5B‧‧‧第2晶片零件搭載部
5C‧‧‧第3晶片零件搭載部
6‧‧‧半導體晶片搭載部
6a‧‧‧擴張部
7‧‧‧晶片零件
7A‧‧‧第1晶片零件
7B‧‧‧第2晶片零件
7C‧‧‧第3晶片零件
7D‧‧‧第4晶片零件
8‧‧‧控制器晶片
9‧‧‧記憶體晶片
10‧‧‧密封樹脂層
10a‧‧‧第1面
10b‧‧‧第2面
10c‧‧‧傾斜部
10d‧‧‧抓持部
10e‧‧‧前端面
11A‧‧‧第1短邊
11B‧‧‧第2短邊
11C‧‧‧第1長邊
11D‧‧‧第2長邊
12‧‧‧缺口部
13‧‧‧內縮部
14A‧‧‧固定膠帶
14B‧‧‧固定膠帶
15‧‧‧凹部
15a‧‧‧壁面
16‧‧‧加工部
17‧‧‧懸掛引線
18‧‧‧固定部
19、22‧‧‧電極墊
19A‧‧‧電極墊
19B‧‧‧電極墊
20、26、27‧‧‧金屬線
21‧‧‧晶片本體
22a‧‧‧異電位之電極墊
23‧‧‧絕緣樹脂膜
24‧‧‧再配線層
24A‧‧‧再配線
25‧‧‧連接墊
32‧‧‧金屬鍍敷層
33‧‧‧鍍敷用連接端子
33A‧‧‧鍍敷用連接端子
33B‧‧‧鍍敷用連接端子
33C‧‧‧鍍敷用連接端子
33D‧‧‧鍍敷用連接端子
34‧‧‧電解鍍敷用連接器接腳
35、37‧‧‧絕緣樹脂層
36‧‧‧開口部
41、42‧‧‧引線
41A‧‧‧第1引線
41B‧‧‧第2引線
41C‧‧‧第3引線
41C1‧‧‧分支部
41C2‧‧‧分支部
42A‧‧‧第4引線
42B‧‧‧第5引線
42C‧‧‧第6引線
D1‧‧‧深度
D2‧‧‧深度
L‧‧‧雷射光
T1‧‧‧樹脂厚度
T2‧‧‧樹脂厚度
圖1係表示第1實施形態之半導體記憶卡的上表面透視圖。
圖2係圖1所示之半導體記憶卡之仰視圖。
圖3係圖1所示之半導體記憶卡的剖面圖。
圖4係圖1所示之半導體記憶卡之下表面之另一例的圖。
圖5係放大表示圖1所示之半導體記憶卡中之外部連接端子及設置於密封樹脂層之凹部的剖面圖。
圖6係圖5所示之外部連接端子及凹部的俯視圖。
圖7係表示圖5所示之外部連接端子及凹部之另一例的剖面圖。
圖8(a)、(b)係表示圖5所示之凹部之形成步驟的剖面圖。
圖9係表示圖1所示之半導體記憶卡中之記憶體晶片之再配線層之第1構成例的剖面圖。
圖10係表示圖1所示之半導體記憶卡中之記憶體晶片之再配線層之第2構成例的剖面圖。
圖11係放大表示第2實施形態之半導體記憶卡之外部連接端子的剖面圖。
圖12係表示第2實施形態之半導體記憶卡之第1構成例及其製造步驟的剖面圖。
圖13係表示圖12所示之半導體記憶卡之最終構成的剖面圖。
圖14係表示第2實施形態之半導體記憶卡之第2構成例及其製造步驟的剖面圖。
圖15係表示第2實施形態之半導體記憶卡之第3構成例及其製造步驟的剖面圖。
圖16係表示圖15所示之半導體記憶卡之最終構成的剖面圖。
圖17係表示第2實施形態之半導體記憶卡之第4構成例及其製造步驟的剖面圖。
圖18係表示圖17所示之半導體記憶卡之最終構成的剖面圖。
以下，參照圖式對實施形態之半導體記憶卡進行說明。
(第1實施形態)
圖1至圖3係表示第1實施形態之半導體記憶卡的圖。圖1係第1實施形態之半導體記憶卡之上表面圖，且係透視半導體記憶卡之構成而表示之圖(上表面透視圖)，圖2係第1實施形態之半導體記憶卡之仰視 圖，圖3係將第1實施形態之半導體記憶卡沿長邊方向(插入至卡槽之方向)切斷的剖面圖。該等圖所示之半導體記憶卡1可用作各種規格之記憶卡。
記憶卡1具備引線架2，該引線架2係作為兼用作端子構件、配線構件、及元件搭載構件之引線電路構件。引線架2包括：複數個外部連接端子3；引線部4，其具有至少一部分連接於外部連接端子3之複數個引線；晶片零件搭載部5，其設置於引線部4；及半導體晶片搭載部6。於晶片零件搭載部5搭載有晶片零件(被動零件)7。於半導體晶片搭載部6搭載有控制器晶片8及NAND型快閃記憶體之類的記憶體晶片9。控制器晶片8係進行向記憶體晶片9之資料寫入或對記憶體晶片9中所記憶之資料進行讀出等的半導體晶片。
引線架2由密封樹脂層10而密封。密封樹脂層10係藉由如下方法而形成，即，以使外部連接端子3之正面露出、並且將引線架2與晶片零件7、控制器晶片8、及記憶體晶片9等一併密封之方式，將例如環氧樹脂等密封樹脂轉移成形。密封樹脂層10具有大致矩形狀之外形，且構成記憶卡1之整體形狀。密封樹脂層10之露出有外部連接端子3之第1面10a(圖2)相當於記憶卡1之背面。密封樹脂層10之與第1面10a相反側之第2面10b(圖1)相當於記憶卡1之正面。
密封樹脂層10之外形邊11中之靠近外部連接端子3之第1短邊11A係相當於記憶卡1的前端部。於密封樹脂層10之前端設置有表示記憶卡1之前方的傾斜部10c。密封樹脂層10之第2短邊11B係相當於記憶卡1之後方部。於密封樹脂層10之後方設置有使其一部分向第2面10b側隆起之抓持部10d。於密封樹脂層10之第1長邊11C，為了表示記憶卡1之前後及正反之朝向，而形成有缺口部12及內縮部13。密封樹脂層10之第2長邊11D形成為直線形狀。
複數個外部連接端子3之前端配置於密封樹脂層10內。於第1實 施形態中，於外部連接端子3之前端未設置懸掛引線。藉此，可防止懸掛引線殘留於密封樹脂層10之前端。由於複數個外部連接端子3係與未圖示之框架分離，故而於其上接著有固定膠帶14A。複數個外部連接端子3係藉由固定膠帶14A而保持。複數個外部連接端子3之正面分別露出於密封樹脂層10之第1面10a。於使外部連接端子3之正面露出於密封樹脂層10之第1面10a時，對引線架2之外部連接端子3與引線部4之連接部分進行彎曲加工，並且於密封樹脂層10之第1面10a設置包圍外部連接端子3之周圍的凹部15。
即，外部連接端子3露出於密封樹脂層10之第1面10a，與此相對，連接於外部連接端子3之引線部4及半導體晶片搭載部6等埋設於密封樹脂層10內。因此，引線架2具有對外部連接端子3與引線部4之連接部分進行彎曲加工而成之加工部16。加工部16係使外部連接端子3露出於外部、並且使引線部4及半導體晶片搭載部6等配置於密封樹脂層10內者，且具有使外部連接端子3與引線部4之連接部分暫時向上方彎曲後彎回水平方向的形狀。藉由將此種加工部16設置於引線架2，可使外部連接端子3露出於外部，並且提高除外部連接端子3以外之引線架2之構成部(引線部4、晶片零件搭載部5、及半導體晶片搭載部6等)或晶片零件7、控制器晶片8、及記憶體晶片9等之樹脂密封性。
於第1實施形態之記憶卡1中，為了提高外部連接端子3之向外部之露出性，除於引線架2設置加工部16以外，還於密封樹脂層10之第1面10a設置使外部連接端子3之正面及側面之一部分露出的凹部15。凹部15係以包圍外部連接端子3之周圍之方式設置。凹部15可如圖2所示以分別包圍複數個外部連接端子3之方式而設置，亦可如圖4所示以一併包圍複數個外部連接端子3之方式而設置。如圖5及圖6放大所示，凹部15具有不僅使外部連接端子3之正面3a而且使側面3b之一部分露 出之形狀。藉由將此種凹部15設置於密封樹脂層10之第1面10a，而提高外部連接端子3之正面3a之露出性。進而，藉由以包圍外部連接端子3之周圍之方式設置凹部15，而使外部連接端子3之外周形狀穩定。藉由該等方式，可充分地發揮外部連接端子3之功能。
凹部15係以自密封樹脂層10之第1面10a凹陷之方式而設置。凹部15之距第1面10a之深度D1較佳為10~300 μm之範圍。於凹部15之深度D1未達10 μm之情形時，有無法使外部連接端子3之正面3a完全露出之虞。若凹部15之深度D1超過300 μm，則於將記憶卡1自外部機器之插槽拔出時，有凹部15卡在插槽側之端子上等記憶卡1難以取出之虞。凹部15之外形形狀只要為可包圍外部連接端子3之全周、並且使外部連接端子3之側面3b之一部分露出的形狀即可，凹部15之寬度(自外部連接端子3之側面3b至密封樹脂層10之壁面15a的距離)並無特別限定。
圖5係表示將外部連接端子3之正面3a設為與密封樹脂層10之第1面10a大致相同之高度的構造，但是外部連接端子3之配置構造並不限定於此。如圖7所示，外部連接端子3亦能夠以使正面3a自密封樹脂層10之第1面10a凹陷之方式配置。但是，若外部連接端子3之正面3a之距密封樹脂層10之第1面10a的深度D2過深，則反而有記憶卡1之插拔性降低之虞，故而深度D2較佳為100 μm以下。藉由使外部連接端子3之正面3a凹陷，可抑制外部連接端子3之損傷及磨耗等之產生。此外，如第2實施形態所詳細敍述般，於在外部連接端子3之正面3a形成金屬鍍敷層之情況下，可防止端子表面自第1面10a突出。
密封樹脂層10之凹部15係例如藉由如下方法而形成，即，對密封樹脂層10照射雷射、紫外線、或電漿等，而除去密封樹脂層10之相當於凹部15之形成位置的部分。參照圖8對凹部15之形成步驟進行說明。首先，於引線架2上搭載晶片零件7、控制器晶片8、及記憶體晶 片9，進而形成將其等與引線架2一併密封之密封樹脂層10。密封樹脂層10例如可藉由轉移成形而形成。因此，如圖8(a)所示，外部連接端子3之側面3b成為藉由密封樹脂層10而覆蓋之狀態。
於將外部連接端子3之正面3a設為與密封樹脂層10之第1面10a為同一面之情形時，由於外部連接端子3之正面3a被成形模覆蓋，故而密封樹脂層10不會形成於正面3a上。但是，於通常之轉移成形中，難以完全抑制朝向外部連接端子3之正面3a之樹脂毛邊之產生。因此，於形成密封樹脂層10之階段，無法避免外部連接端子3之正面3a之至少一部分成為由構成密封樹脂層10之樹脂覆蓋的狀態。為此，如圖8(b)所示，包括外部連接端子3之正面3a上在內，對密封樹脂層10之凹部15之形成區域照射雷射光L。亦可代替雷射光L而照射紫外線或電漿等。
藉由對密封樹脂層10照射雷射光L，而除去外部連接端子3之正面3a上存在之樹脂，同時以包圍外部連接端子3之全周之方式形成使外部連接端子3之側面3b之一部分露出的凹部15。凹部15可如圖2及圖6所示以分別包圍各個外部連接端子3之外周之方式而形成，亦可如圖4所示以一併包圍複數個外部連接端子3之外周之方式而形成。藉由使此種凹部15形成於密封樹脂層10之第1面10a，可確實地使外部連接端子3之正面3a露出，並且使外部連接端子3之外周形狀穩定。因此，可充分地發揮外部連接端子3之功能。
引線部4包括：引線41，其直接連接於外部連接端子3；及引線42，其與外部連接端子3電性獨立。於該等引線41、42中，第1、第2及第3引線41A、41B、41C之一端部直接連接於外部連接端子3。第1引線41A之另一端部配置於控制器晶片8之附近區域。於第2引線41B及與其電性獨立之第4引線42A上設置有第1晶片零件搭載部5A。於第1晶片零件搭載部5A搭載有保險絲等第1晶片零件7A，且該保險絲等 第1晶片零件7A與第2引線41B及第4引線42A電性連接。第4引線42A進而被迴繞至控制器晶片8之附近區域。
第3引線41C於被迴繞至控制器晶片8之附近區域後產生分支。於第3引線41C之一分支部41C1及與其電性獨立之第5引線42B設置有第2晶片零件搭載部5B。於第2晶片零件搭載部5B搭載有電容器等第2晶片零件7B，且該電容器等第2晶片零件7B與第3引線41C之分支部41C1及第5引線42B電性連接。於第3引線41C之另一分支部41C2及與其電性獨立之第6引線42C上設置有第3晶片零件搭載部5C。於第3晶片零件搭載部5C搭載有電容器等第3及第4晶片零件7C、7D，且該電容器等第3及第4晶片零件7C、7D與第3引線41C之分支部41C2及第6引線42C電性連接。第5及第6引線42B、42C進而被迴繞至記憶體晶片9之附近。
半導體晶片搭載部6具有向密封樹脂層10之短邊11B擴張之擴張部6a，於該擴張部6a設置有與未圖示之框架連接之懸掛引線17。進而，引線架2具有沿密封樹脂層10之兩長邊11C、11D而設置之固定部18。於固定部18設置有懸掛引線17。半導體晶片搭載部6與固定部18電性獨立。半導體晶片搭載部6及引線部4之一部分係藉由接著於設置有懸掛引線17之固定部18的固定膠帶14B而得以保持。固定膠帶14B自固定部18跨及半導體晶片搭載部6、進而是引線部4之一部分而接著，且將半導體晶片搭載部6及引線部4之一部分固定於由懸掛引線17支撐之固定部18。
如此，半導體晶片搭載部6於密封樹脂層10之兩側面(具有長邊11C、11D之面)之間電性獨立。即，半導體晶片搭載部6不與設置於密封樹脂層10之兩側面之懸掛引線17導通，而是於兩側面之懸掛引線17之間電性獨立。藉由使用此種半導體晶片搭載部6，即便於密封樹脂層10之兩側面與外部之導通構件等接觸之情形時，亦不會使半導體 晶片搭載部6短路。因此，即便於在密封樹脂層10之兩側面之間發生短路之類的情形時，亦可抑制控制器晶片8或記憶體晶片9發生不良等，從而可提高記憶卡1之可靠性。
配置於半導體晶片搭載部6上之控制器晶片8及記憶體晶片9分別具有矩形狀之外形。控制器晶片8係配置於外部連接端子3與記憶體晶片9之間。即，控制器晶片8係配置於較記憶體晶片9更靠近外部連接端子3之側。控制器晶片8具有：電極墊19A，其沿靠近外部連接端子3之側之長邊而排列；及電極墊19B，其沿靠近記憶體晶片9之側之長邊而排列。控制器晶片8之靠近外部連接端子3之側的電極墊19A經由金屬線20而與第1、第3、第4引線41A、41C、42A電性連接。
例如圖9所示，記憶體晶片9包括：晶片本體21，其具有省略圖示之半導體元件部等；電極墊22，其形成於晶片本體21；絕緣樹脂膜23，其以使電極墊22露出，並且覆蓋晶片本體21之正面之方式而形成；及再配線層24，其形成於絕緣樹脂膜23上。根據控制器晶片8與記憶體晶片9之電極墊19、22之排列及種類等，而需要再配置記憶體晶片9之電極墊22。設置於包含聚醯亞胺樹脂等之絕緣樹脂膜(保護膜)23上的再配線層24係將電極墊22再配置於記憶體晶片9上之所需的位置者，例如一端部與電極墊22電性連接，於另一端部形成有成為金屬線之接合部的連接墊25。
考慮到金屬線相對於再配線層24之接合性，再配線層24之至少最表面層較佳為由Al、Al-0.5質量%之Cu合金等Al合金、或者Au或Pd等貴金屬材料等形成。進而，若考慮再配線層24之向絕緣樹脂膜23上之形成性及密著性等，則再配線層23之最下層較佳為由Ti或Cr等形成。作為再配線層24之具體構成，可列舉Al/Ti、Al-Cu/Ti、Au/Ni/Ti、及Au/Ni/Cu/Ti等積層膜。於利用Al層(包含Al合金層)或貴金屬層形成再配線層24之最表面層之情形時，就確保接合性而言，最 表面層之厚度較佳為設為2 μm以上。即便使最表面層變得過厚，亦無法獲得更佳之效果，故而其厚度較佳為設為5 μm以下。
於構成再配線層24之再配線中，至少一部分之再配線24A之一端部與電極墊22電性連接，並且於另一端部形成有連接墊25。在形成於再配線24A之端部的連接墊25上接合有金屬線26之一端部。金屬線26之另一端部係接合於控制器晶片8之電極墊19B及引線41C、42B、42C。即，再配線24A經由金屬線26而與控制器晶片8之電極墊19B及引線41C、42B、42C電性連接。
再配線24A與電極墊22之電性連接構造可為如圖9所示般之直接連接之構造，亦可為如圖10所示般之經由金屬線27而連接之構造。於在連接再配線24A之電極墊22之附近存在其他電極墊(例如異電位之電極墊22a)之情形時，如圖10所示，可藉由以跨過異電位之電極墊22a之方式配置金屬線27，而使再配線24A連接於電極墊22。利用金屬線27之跨越構造對於跨過異電位之再配線及引線的構造而言亦有效。第4引線42A係經由以跨過異電位之第1引線41A之方式而配置之金屬線27而與同電位之第6引線42C電性連接。藉由使用此種利用金屬線27之跨越構造，可提高利用單層構造之再配線層24的電路之形成性。
於第1實施形態之記憶卡1中，由於在密封樹脂層10之第1面10a設置凹部15，該凹部15使外部連接端子3之正面3a及側面3b之一部分露出、並且包圍外部連接端子3之周圍，故而可利用引線架2實現記憶卡1之低成本化，並且可提高外部連接端子3之露出性。進而，亦使外部連接端子3之外周形狀穩定。因此，可提高記憶卡1之利用外部連接端子3實現之與外部機器之連接可靠性，即記憶卡1之動作可靠性。
(第2實施形態)
其次，參照圖11至圖18，對第2實施形態之記憶卡進行說明。對與第1實施形態相同部分標註相同符號，並省略其一部分說明。如圖 11所示，第2實施形態之記憶卡31具備設置於自密封樹脂層10露出之外部連接端子3之正面3a及側面3b上的金屬鍍敷層32。於第2實施形態之記憶卡31中，除於外部連接端子3上設置有金屬鍍敷層32以外，其他基本構成均與第1實施形態之記憶卡1相同。於密封樹脂層10之第1面10a設置有凹部15，該凹部15使外部連接端子3之正面3a及側面3b之一部分露出、並且包圍外部連接端子3之周圍。凹部15之具體構成等亦與第1實施形態相同。
一般而言，引線架2係藉由Fe-Ni系合金(例如Fe-42%Ni合金)或Cu合金等而形成。因此，就露出於外部之外部連接端子3之正面3a及側面3b而言，於使用時有形成表面氧化膜、或者發生腐蝕或鏽等之虞。為了抑制此種表面氧化膜、腐蝕、或鏽等發生，而於外部連接端子3之露出之正面3a及側面3b形成有金屬鍍敷層32。作為金屬鍍敷層32之代表性構成材料，可列舉Au及Pd等貴金屬。金屬鍍敷層32並不限於Au及Pd之單層膜，亦可為Au/Cu、Pd/Cu、Au/Ni、Pd/Ni、Au/Ni/Cu、Pd/Ni/Cu、Au/Pd/Ni、或Au/Pd/Ni/Cu等積層膜。再者，根據記憶卡31之使用用途等，亦可在不於外部連接端子3上形成金屬鍍敷層32的情況下使用記憶卡31。
為了於外部連接端子3之露出之正面3a及側面3b上利用電解鍍敷法形成金屬鍍敷層32，需要於外部連接端子3連接電解鍍敷用連接器接腳。於金屬鍍敷層32之形成前之階段，外部連接端子3之正面3a係露出。因此，可藉由使外部連接端子3之露出之正面3a與電解鍍敷用連接器接腳接觸，而對外部連接端子3之露出之正面3a及側面3b進行電解鍍敷。然而，若使連接器接腳與外部連接端子3之正面3a接觸而進行電解鍍敷，則於正面3a之與連接器接腳接觸之部分未附著有鍍敷金屬，從而成為產生表面氧化膜、腐蝕、或鏽等之原因。
於第2實施形態之記憶卡31中，引線架2具有與外部連接端子3不 同的自密封樹脂層10露出之鍍敷用連接端子。對鍍敷用連接端子之具體構成進行敍述。圖12係表示有鍍敷用連接端子33之第1構成例。圖12所示之引線架2具有鍍敷用連接端子33A，且該鍍敷用連接端子33A係藉由如下方法而形成，即，以使連接於外部連接端子3之引線41之一部分露出於密封樹脂層10之第1面10a的方式，對引線41進行彎曲加工。引線41暫時向密封樹脂層10之第1面10a彎曲，將引線41之一部分配置於與第1面10a相同之高度後，彎回至半導體晶片搭載部6之高度。
如圖12所示，藉由使自密封樹脂層10露出之鍍敷用連接端子33A與電解鍍敷用連接器接腳34接觸而進行電解鍍敷，而於外部連接端子3之露出之正面3a及側面3形成金屬鍍敷層32。藉由以此方式進行電解鍍敷，可於外部連接端子3之露出之整個正面3a及側面3上良好地形成金屬鍍敷層32。於形成金屬鍍敷層32後，如圖13所示，使絕緣樹脂層35以覆蓋鍍敷用連接端子33A之方式形成於密封樹脂層10之第1面10a。絕緣樹脂層35可藉由貼附絕緣膜或塗佈絕緣樹脂漿料而形成。
上述引線41之彎曲加工不僅可藉由鍍敷用連接端子33A之形成而實施，亦可對晶片零件搭載部5實施。即，一般而言，晶片零件7之高度高於控制器晶片8及記憶體晶片9之高度。因此，若將晶片零件搭載部5之高度(自密封樹脂層10之第1面10a起的高度)設為與半導體晶片搭載部6之高度相同，則晶片零件7上之樹脂厚度會變薄，而有密封樹脂層10對晶片零件7之被覆性降低之虞。針對此種情況，如下方法較為有效，即，如圖14所示，將以自半導體晶片搭載部6至第1面10a之樹脂厚度T1、與自控制器晶片8或記憶體晶片9之上表面至第2面10b之樹脂厚度T2大致相等之方式設定半導體晶片搭載部6之高度，並且將晶片零件搭載部5配置於較半導體晶片搭載部6更靠近密封樹脂層10之第1面10a的位置。
以此方式，將半導體晶片搭載部6配置於樹脂厚度T1與樹脂厚度T2大致相等之位置，並且將晶片零件搭載部5配置於晶片零件7可被密封樹脂層10充分地被覆之位置，藉此，可防止晶片零件7之被覆性之降低及隨之產生之晶片零件7向外部之露出等，並且可抑制樹脂密封步驟中之半導體晶片搭載部6之位置偏離及密封樹脂層10之翹曲等發生。即，可提高使用引線架2之記憶卡31之製造性及可靠性等。
圖14所示之晶片零件搭載部5A、5B係以其等配置於較半導體晶片搭載部6更靠近密封樹脂層10之第1面10a之位置的方式而設置於經彎曲加工之引線41、42上。於其等之中，晶片零件搭載部5A係以使引線41之一部分露出於密封樹脂層10之第1面10a的方式而設置於經彎曲加工之引線41上，且兼作鍍敷用連接端子33B。亦可藉由使此種鍍敷用連接端子33B與電解鍍敷用連接器接腳34接觸而進行電解鍍敷。圖14所示之鍍敷用連接端子33B亦與圖13所示之鍍敷用連接端子33A同樣地，於形成金屬鍍敷層32後由絕緣樹脂層35覆蓋。
圖15係表示鍍敷用連接端子33之第2構成例。圖15所示之記憶卡31具有以使外部連接端子3之背面露出的方式而自密封樹脂層10之第2面10b設置的開口部36。外部連接端子3之背面之一部分露出於開口部36內，該部分係作為鍍敷用連接端子33C而發揮作用。即便藉由使露出於開口部36內之外部連接端子3之背面(鍍敷用連接端子33C)與電解鍍敷用連接器接腳34接觸而進行電解鍍敷，亦可在露出於密封樹脂層10之第1面10a側的外部連接端子3之整個正面3a及側面3上良好地形成金屬鍍敷層32。於形成金屬鍍敷層32後，如圖16所示，對開口部36內填充絕緣樹脂37。或，亦可與第1構成例同樣地，於密封樹脂層10之第2面10b形成絕緣樹脂層35而堵塞開口部36。
圖17係表示有鍍敷用連接端子33之第3構成例。於圖17所示之引線架2中，在外部連接端子3之前端設置有懸掛引線17，使自該密封樹 脂層10之前端面10e突出之懸掛引線17作為鍍敷用連接端子33D而發揮作用。即便藉由使自密封樹脂層10之前端面突出之鍍敷用連接端子33D與電解鍍敷用連接器38接觸而進行電解鍍敷，亦可在露出於密封樹脂層10之第1面10a的外部連接端子3之整個正面3a及側面3上良好地形成金屬鍍敷層32。於形成金屬鍍敷層32後，如圖18所示，將懸掛引線17之自密封樹脂層10之前端面10e突出的部分切斷後，於前端面10e形成絕緣樹脂層35。絕緣樹脂層35與第1構成例同樣地，係藉由絕緣膜之貼附或絕緣樹脂漿料之塗佈等而形成。
再者，雖然已對本發明之若干實施形態進行了說明，但是該等實施形態係作為例子而提示，並非意欲限定發明之範圍。該等新穎之實施形態可藉由其他各種形態而實施，且可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。該等實施形態及其變形包含於發明之範圍或主旨中，並且包含於申請專利範圍中所記載之發明與其均等之範圍內。
1‧‧‧記憶卡
2‧‧‧引線架
3‧‧‧外部連接端子
4‧‧‧引線部
5‧‧‧晶片零件搭載部
6‧‧‧半導體晶片搭載部
7‧‧‧晶片零件
8‧‧‧控制器晶片
9‧‧‧記憶體晶片
10‧‧‧密封樹脂層
10a‧‧‧第1面
10b‧‧‧第2面
10c‧‧‧傾斜部
10d‧‧‧抓持部
15‧‧‧凹部
16‧‧‧加工部
20、26‧‧‧金屬線

Claims (5)

  1. 一種半導體記憶卡，其特徵在於包括：引線架，其包含：複數個外部連接端子；引線部，其具有至少一部分連接於上述外部連接端子之複數個引線；晶片零件搭載部，其設置於上述引線部；及半導體晶片搭載部；晶片零件，其搭載於上述晶片零件搭載部，且與上述引線電性連接；控制器晶片及記憶體晶片，該控制器晶片搭載於上述半導體晶片搭載部且與上述引線電性連接，該記憶體晶片與上述控制器晶片電性連接；密封樹脂層，其係將上述引線架與上述晶片零件、上述控制器晶片、及上述記憶體晶片一併密封者，且包含：第1面，其成為上述外部連接端子之露出面；及凹部，其以使上述外部連接端子之正面及側面之一部分露出、並且包圍上述外部連接端子之周圍的方式設置於上述第1面，並且距上述第1面之深度為10~300 μm之範圍；以及金屬鍍敷層，其設置於上述外部連接端子之露出之上述正面及上述側面；且上述引線架包含與上述外部連接端子不同的自上述密封樹脂層露出之鍍敷用連接端子；上述引線架包含：第1懸掛引線，其設置於上述密封樹脂層之一側面；及第2懸掛引線，其設置於上述密封樹脂層之另一側面；上述半導體晶片搭載部係於上述第1懸掛引線與上述第2懸掛引線之間電性獨立。
  2. 一種半導體記憶卡，其特徵在於包括：引線架，其包含：複數個外部連接端子；引線部，其具有至少一部分連接於上述外部連接端子之複數個引線；晶片零件搭載部，其設置於上述引線部；及半導體晶片搭載部；晶片零件，其搭載於上述晶片零件搭載部，且與上述引線電性連接；控制器晶片及記憶體晶片，該控制器晶片搭載於上述半導體晶片搭載部且與上述引線電性連接，該記憶體晶片與上述控制器晶片電性連接；以及密封樹脂層，其係將上述引線架與上述晶片零件、上述控制器晶片、及上述記憶體晶片一併密封者，且包含：第1面，其成為上述外部連接端子之露出面；及凹部，其以使上述外部連接端子之正面及側面之一部分露出、並且包圍上述外部連接端子之周圍的方式設置於上述第1面。
  3. 如請求項2之半導體記憶卡，其進而包含設置於上述外部連接端子之露出之上述正面及上述側面的金屬鍍敷層，且上述引線架包括與上述外部連接端子不同的自上述密封樹脂層露出之鍍敷用連接端子。
  4. 如請求項2或3之半導體記憶卡，其中上述引線架包含：第1懸掛引線，其設置於上述密封樹脂層之一側面；及第2懸掛引線，其設置於上述密封樹脂層之另一側面；且上述半導體晶片搭載部係於上述第1懸掛引線與上述第2懸掛引線之間電性獨立。
  5. 一種半導體記憶卡之製造方法，其特徵在於包括如下步驟：準備引線架，該引線架包含複數個外部連接端子、具有至少一部分連接於上述外部連接端子之複數個引線的引線部、設置 於上述引線部之晶片零件搭載部、及半導體晶片搭載部；將晶片零件搭載於上述晶片零件搭載部；將控制器晶片與記憶體晶片搭載於上述半導體晶片搭載部；使上述控制器晶片與上述引線電性連接；使上述記憶體晶片與上述控制器晶片電性連接；形成將上述引線架與上述晶片零件、上述控制器晶片、及上述記憶體晶片一併密封之密封樹脂層；以及於上述密封樹脂層之成為上述外部連接端子之露出面的第1面上形成凹部，該凹部係使上述外部連接端子之正面及側面之一部分露出、並且包圍上述外部連接端子之周圍。
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