JP2009158739A - 半導体装置と半導体記憶装置 - Google Patents
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Abstract
【解決手段】配線基板上2には第1の半導体素子群12を構成する複数の半導体素子9が階段状に積層されている。第1の半導体素子群12上には第2の半導体素子群13を構成する複数の半導体素子9が第1の半導体素子群12とは逆方向に向けて階段状に積層されている。第2の半導体素子群13における最下段の半導体素子9は、第1の半導体素子群12における最上段の半導体素子9の直上に、スペーサ層として機能する絶縁性接着層15を介して積層されており、かつ最上段の半導体素子に接続された第1の金属ワイヤ14の素子側端部は絶縁性接着層内15に埋め込まれている。
【選択図】図2
Description
Claims (5)
- 素子搭載部と接続パッドとを備える配線基板と、
外形の一辺に沿って配列された電極パッドを有する複数の半導体素子を備え、前記複数の半導体素子は前記配線基板の前記素子搭載部上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように階段状に積層されている第1の半導体素子群と、
外形の一辺に沿って配列された電極パッドを有する複数の半導体素子を備え、前記複数の半導体素子は前記第1の半導体素子群上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように前記第1の半導体素子群の階段方向とは逆方向に向けて階段状に積層されている第2の半導体素子群と、
前記第1の半導体素子群を構成する前記複数の半導体素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第1の金属ワイヤと、
前記第2の半導体素子群を構成する前記複数の半導体素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第2の金属ワイヤと、
前記第1および第2の半導体素子群を前記第1および第2の金属ワイヤと共に封止するように、前記配線基板上に形成された封止樹脂層とを具備し、
前記第2の半導体素子群における最下段の半導体素子は、前記第1の半導体素子群における最上段の半導体素子の直上にスペーサ層として機能する絶縁性接着層を介して積層されており、かつ前記最上段の半導体素子に接続された前記第1の金属ワイヤの素子側端部は、前記絶縁性接着層内に埋め込まれていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1および第2の半導体素子群の少なくとも一方は2組以上の素子集団に分けられており、これら2組以上の素子集団は前記電極パッドの配列方向にずらした状態で配置されていることを特徴とする半導体装置。 - 外部接続端子を備える第1の主面と、素子搭載部と接続パッドとを備え、前記第1の主面とは反対側の第2の主面とを有する配線基板と、
外形の一辺に沿って配列された電極パッドを有する複数のメモリ素子を備え、前記複数のメモリ素子は前記配線基板の前記素子搭載部上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように階段状に積層されている第1のメモリ素子群と、
外形の一辺に沿って配列された電極パッドを有する複数のメモリ素子を備え、前記複数のメモリ素子は前記第1の素子群上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように前記第1のメモリ素子群の階段方向とは逆方向に向けて階段状に積層されている第2のメモリ素子群と、
前記第2のメモリ素子群上に積層され、少なくとも外形の一辺に沿って配列された電極パッドを有するコントローラ素子と、
前記第1のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第1の金属ワイヤと、
前記第2のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第2の金属ワイヤと、
前記コントローラ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第3の金属ワイヤと、
前記第1および第2のメモリ素子群と前記コントローラ素子を前記第1、第2および第3の金属ワイヤと共に封止するように、前記配線基板の前記第2の主面上に形成された封止樹脂層とを具備し、
前記第2のメモリ素子群における最下段のメモリ素子は、前記第1のメモリ素子群における最上段のメモリ素子の直上にスペーサ層として機能する絶縁性接着層を介して積層されており、かつ前記最上段のメモリ素子に接続された前記第1の金属ワイヤの素子側端部は、前記絶縁性接着層内に埋め込まれていることを特徴とする半導体記憶装置。 - 請求項3記載の半導体記憶装置において、
前記第1および第2のメモリ素子群の少なくとも一方は2組以上の素子集団に分けられており、これら2組以上の素子集団は前記電極パッドの配列方向にずらした状態で配置されていることを特徴とする半導体記憶装置。 - 請求項3または請求項4記載の半導体記憶装置において、
前記第1のメモリ素子群における最下段のメモリ素子の厚さをT1、他のメモリ素子の厚さをT2、前記第2のメモリ素子群における最下段のメモリ素子の厚さをT3、他のメモリ素子の厚さをT4としたとき、前記第1のメモリ素子群はT1>T2を満足し、かつ前記第2のメモリ素子群はT3>T4を満足することを特徴とする半導体記憶装置。
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JP2007335666A JP5150243B2 (ja) | 2007-12-27 | 2007-12-27 | 半導体記憶装置 |
US12/343,921 US8004071B2 (en) | 2007-12-27 | 2008-12-24 | Semiconductor memory device |
US13/172,571 US8395268B2 (en) | 2007-12-27 | 2011-06-29 | Semiconductor memory device |
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Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011145294A1 (ja) * | 2010-05-19 | 2011-11-24 | パナソニック電工株式会社 | 配線方法、並びに、表面に配線が設けられた構造物、半導体装置、配線基板、メモリカード、電気デバイス、モジュール及び多層回路基板 |
US8283210B2 (en) | 2010-01-08 | 2012-10-09 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
US8338962B2 (en) | 2010-08-12 | 2012-12-25 | Samsung Electronics Co., Ltd. | Semiconductor package substrate and semiconductor package having the same |
US8376238B2 (en) | 2009-10-30 | 2013-02-19 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
JP2013522887A (ja) * | 2010-03-18 | 2013-06-13 | モサイド・テクノロジーズ・インコーポレーテッド | オフセットダイスタッキングを用いたマルチチップパッケージおよびその作成方法 |
US8691628B2 (en) | 2010-12-10 | 2014-04-08 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device, manufacturing program, and manufacturing apparatus |
US8766412B2 (en) | 2009-04-23 | 2014-07-01 | Kabushiki Kaisha Toshiba | Semiconductor device, method of manufacturing the same, and silane coupling agent |
JP2014187221A (ja) * | 2013-03-25 | 2014-10-02 | Toshiba Corp | 半導体装置とその製造方法 |
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US11721672B2 (en) | 2021-03-05 | 2023-08-08 | Kioxia Corporation | Semiconductor device and manufacturing method thereof |
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