CN101621012B - 具有用于线接合的局部化空腔的堆叠式半导体封装及其制造方法 - Google Patents

具有用于线接合的局部化空腔的堆叠式半导体封装及其制造方法 Download PDF

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CN101621012B
CN101621012B CN200910151524XA CN200910151524A CN101621012B CN 101621012 B CN101621012 B CN 101621012B CN 200910151524X A CN200910151524X A CN 200910151524XA CN 200910151524 A CN200910151524 A CN 200910151524A CN 101621012 B CN101621012 B CN 101621012B
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semiconductor die
nude film
localized cavities
localized
cavities
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CN101621012A (zh
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赫姆·塔基阿尔
什里卡·巴加斯
奇门·于
廖智清
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Delphi International Operations Luxembourg SARL
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SanDisk Corp
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Abstract

本发明揭示一种制造半导体裸片及低轮廓半导体封装的方法。所述半导体封装可包含安装到衬底的至少第一及第二堆叠式半导体裸片。可将所述第一及/或第二半导体裸片制造为具有沿所述半导体裸片的侧边缘穿过所述半导体裸片的底表面的若干局部化空腔。侧中的所述一个或一个以上局部化空腔占据少于整个侧。因此，所述局部化空腔允许半导体裸片的低高度堆叠同时为每一裸片提供高程度的结构完整性，以防止所述裸片边缘在制造期间破裂或断裂。

Description

具有用于线接合的局部化空腔的堆叠式半导体封装及其制造方法
相关申请案交叉参考
以下申请案在本文中被交叉参考且其整体内容以引用方式并入本文中：
由塔基尔(Takiar)等人与本专利同日申请的名称为“Stacked SemiconductorPackage with Localized Cavities For Wire Bonding(具有用于线接合的局部化空腔的堆叠式半导体封装)”的美国专利申请案第____号[代理档案号SAND-01322US1]。
技术领域
本发明实施例涉及一种低轮廓半导体装置及制造所述低轮廓半导体装置的方法。
背景技术
对便携式消费者电子装置的需求的强劲增长正推动对高容量存储装置的需要。例如快闪存储器存储卡的非易失性半导体存储器装置正变得广泛用于满足对数字信息存储及交换的不断增长的需求。其便携性、多功能性及坚固设计，连同其高可靠性及大容量已使此类存储器装置可理想地用于各种各样的电子装置，其中包含(例如)数码相机、数字音乐播放器、视频游戏控制台、PDA及蜂窝式电话。
虽然已知各种各样的封装配置，但快闪存储器存储卡一般可制造为单封装系统(SiP)或多芯片模块(MCM)，其中多个裸片以堆叠式配置安装在衬底上。现有技术图1及2中显示常规半导体封装20(不具有模制复合物)的边视图。典型的封装包含安装到衬底26的多个半导体裸片22、24。虽然图1及2中未显示，但所述半导体裸片形成有位于所述裸片的上表面上的裸片接合垫。衬底26可由夹在上传导层与下传导层之间的电绝缘核心形成。所述上传导层及/或下传导层可经蚀刻以形成包含电引线及接触垫的电导图案。将线接合焊接在半导体裸片22、24的裸片接合垫与衬底26的接触垫之间以将所述半导体裸片电耦合到所述衬底。所述衬底上的电引线又提供裸片与主机装置之间的电路径。一旦在裸片与衬底之间形成电连接，即通常可将组合件封闭在模制复合物中以提供保护性封装。
已知以一定偏移(现有技术图1)或以堆叠式配置(现有技术图2)将半导体裸片层叠在彼此上方。在图1的偏移配置中，以一定偏移堆叠所述裸片以使得下一下裸片的接合垫被暴露。此类配置显示于(例如)林(Lin)等人的名称为“Multichip ModuleHaving A Stacked Chip Arrangement(具有堆叠式芯片布置的多芯片模块)”的美国专利第6,359,340号中。偏移配置提供便于接近所述半导体裸片中的每一者上的接合垫的优点。然而，所述偏移在空间非常宝贵的衬底上需要较大占地面积。
在图2的堆叠式配置中，两个或两个以上半导体裸片直接彼此上下堆叠，从而与偏移配置相比在衬底上占据较小占地面积。然而，在堆叠式配置中，必须在邻近半导体裸片之间提供用于接合线30的空间。除接合线30本身的高度之外，必须在接合线上方留有额外空间，因为一个裸片的接合线30与上面的下一裸片接触可导致短路。因此，如图2中所示，已知提供介电间隔层34以为待接合到下裸片24上的裸片接合垫的线接合30提供充足的空间。
现在参照现有技术图3及4，替代间隔层34，还已知沿上裸片(例如裸片22)的底部(不活动)表面42的边缘蚀刻沟槽40。沟槽40允许将两个裸片没有间隔层地直接彼此上下堆叠，同时仍具有用于来自下裸片的线接合30的空间。如图4中所示，沟槽40已沿裸片的整个边缘常规地形成。在(例如)谭(Tan)的美国专利第7,309,623中可见沿整个边缘形成的沟槽的实例，其显示具有垂直与水平侧壁(还显示于现有技术图4中)的沟槽。在(例如)塔克曼(Tuckerman)等人的美国专利第5,804,004号中可见沿整个边缘形成的沟槽的又一实例，其显示具有有角度或有斜面的侧道的沟槽。这两个专利均以引用方式并入本文中。
包含沿整个边缘的沟槽的现有技术半导体封装的一个缺点是，所述沟槽的形成会在结构上削弱半导体裸片。也就是说，当沟槽仅在沟槽上方留有很薄量的材料时，所述裸片可能会在沟槽上方破裂或断裂。在囊封工艺期间情况尤其如此，其中对半导体裸片施加较大力以将裸片适当地封闭在模制复合物中。
发明内容
本发明实施例涉及一种半导体裸片及一种由所述半导体裸片形成的低轮廓半导体封装，所述封装包含安装到衬底的至少第一及第二堆叠式半导体裸片。所述第一及/或第二半导体裸片可制造为具有沿所述半导体裸片的侧边缘的穿过所述半导体裸片的底表面的局部化空腔。所述半导体裸片的既定侧可不包含局部化空腔或包含一个或一个以上局部化空腔。当所述裸片的侧包含一个或一个以上局部化空腔时，所述局部化空腔占据少于整个侧。
当组装到衬底上的裸片堆叠中时，将来自第一半导体裸片的线接合接纳在安装于所述第一裸片的顶部上的半导体裸片的局部化空腔内。因此，可在来自第一裸片的线接合不使安装于第一裸片上的半导体裸片发生短路的情况下将裸片直接彼此上下堆叠。因为所述空腔被局部化且不占据裸片的整个侧，所以所述局部化空腔允许半导体裸片的低高度堆叠同时为每一裸片提供高程度的结构完整性，以防止裸片边缘在制造期间破裂或断裂。
在实施例中，局部化空腔在裸片的底表面中的位置对应于裸片接合垫在所述裸片的顶表面中的位置。因此，多个此半导体裸片可彼此上下堆叠，其中接合垫及线接合从中延伸以在堆叠中的下一较高半导体裸片的局部化空腔内对准。
半导体裸片还可包含从半导体裸片的各侧中的每一侧向内留出空间的局部化空腔。在包含这一局部化空腔的实施例中，例如无源组件或辅助半导体裸片的组件可安装在位于所述局部化空腔下面的表面上且接纳在所述局部化空腔内。所述空腔用于将所述组件与包含所述空腔的裸片隔离。这一配置增加了可供安装组件的位置(例如在衬底上)的灵活性。
附图说明
图1是包含以偏移关系而堆叠的一对半导体裸片的常规半导体装置的现有技术边视图。
图2是包含以重叠关系而堆叠且由间隔层分开的一对半导体裸片的常规半导体装置的现有技术边视图。
图3是包含以重叠关系而堆叠的一对半导体裸片的常规半导体装置的现有技术边视图，其中上裸片包含沿所述半导体裸片的下边缘的沟槽。
图4是具有如图3中所示的沟槽的常规半导体裸片的现有技术底部透视图。
图5是用于形成根据根据本发明实施例的半导体裸片的流程图。
图6是可用以制造根据本发明实施例的多个半导体裸片的半导体晶片的俯视图。
图7是在制造期间的半导体裸片的俯视图。
图8是图7的在制造期间的半导体裸片的透视图。
图9是半导体裸片的俯视图，所述半导体裸片包含在所述半导体裸片的底表面中形成的局部化空腔。
图10是图9的半导体裸片的底部透视图，所述半导体裸片包含在所述半导体裸片的底表面中形成的局部化空腔。
图10A是通过图10中的线10-10的截面图。
图10B是从与图10A相同的视角看到的包含成斜角的表面的局部化空腔的替代实施例的截面图。
图11是半导体裸片的边视图，所述半导体裸片包含埋入在所述半导体裸片的底表面的中央部分内的局部化空腔。
图12是图11的半导体裸片的底部透视图，所述半导体裸片包含在所述半导体裸片的底表面的中央部分内形成的局部化空腔。
图13是显示根据本发明的半导体装置的制造的流程图。
图14是在制造期间的半导体装置的透视图，其包含定位于下一邻近半导体裸片的局部化空腔内的线接合。
图15是根据本发明实施例的成品半导体装置的边视图。
图16是包含根据本发明替代实施例的局部化空腔及线接合配置的俯视图。
图17是根据图16的替代实施例的半导体装置的端视图。
图18是包含根据本发明又一替代实施例的局部化空腔及线接合配置的俯视图。
图19是根据图18的替代实施例的半导体装置的端视图。
图20是根据替代实施例的半导体装置的俯视图，所述半导体装置包含位于所述半导体裸片的中央部分内的局部化空腔。
图21是根据图20的替代实施例的半导体装置的截面图。
图22是显示制造期间的半导体装置的替代实施例的透视图，所述半导体装置包含定位于半导体裸片之间的间隔层的局部化空腔内的线接合。
具体实施方式
现在将参照图5到22描述关于低轮廓半导体封装的实施例。应了解，本发明可体现为许多不同形式，且不应视为仅限于本文中所述的实施例。而是，提供这些实施例以使得本发明将透彻且完整并将本发明全面传达给所属领域的技术人员。实际上，希望本发明涵盖这些实施例的替代、修改及等效形式，这些实施例的替代、修改及等效形式归属于所附权利要求书所界定的本发明范围及精神内。此外，在本发明的以下详细说明中，阐述了众多特定细节以提供对本发明的透彻了解。然而，所属领域的技术人员应清楚，可在没有此类特定细节的情况下实践本发明。
本文中使用术语“顶部”和“底部”及“上”和“下”仅用于方便及说明性目的且不希望限定本发明说明，因为所参照的物项可交换位置。
现在将参照图5的流程图及图6到12的各俯视图及透视图来描述用于形成根据本发明的半导体裸片的过程。图6显示用于批量处理多个半导体裸片102(其中一个裸片标示于图6中)的半导体晶片100的俯视图。每一裸片102均形成有接合垫104，如(例如)图7及8中裸片102的放大图中所显示。接合垫104用于将半导体裸片102电耦合到另一半导体裸片或电耦合到印刷电路板、引线框或如下文中解释的其它衬底。虽然在图7及8中显示接合垫104沿裸片102的所有边缘，但应了解，在进一步实施例中，接合垫104可沿一个边缘、两个相对或邻近边缘或三个边缘形成。应了解，沿半导体裸片102的既定边缘的接合垫104的数目可比图中所显示的更多或更少。
现在参照图5的流程图，可在步骤200中通过例如膜沉积、光刻、图案化及杂质扩散的已知工艺在晶片100上形成半导体裸片102的集成电路组件。可在步骤202中通过包含但不限于镀覆、蒸发、网版印刷或各种沉积工艺的已知工艺在相应的裸片中形成裸片接合垫104。
根据本发明，接下来可在步骤210中在晶片100的裸片102的背面(不活动)表面中形成局部化空腔。此类局部化空腔110例如在图9的俯视图中及图10的底部透视图中以幻图形式看到。局部化空腔110可通过各种已知工艺形成，其中包含(例如)化学湿蚀刻、干蚀刻、激光烧蚀或可控制地移除裸片102的背面表面的若干部分的其它化学或机械手段。为制造局部化空腔，可将晶片100的顶部(活动)表面固定到卡盘以便可对所述背面表面执行上文所描述的工艺中的一种工艺以界定晶片100中的每一半导体裸片的局部化空腔。
局部化空腔110在裸片102的底表面中的位置对应于线接合垫104在裸片102的顶表面中的位置。也就是说，局部化空腔110在裸片102的底表面上形成，直接在位于裸片102的顶表面上的接合垫104下面。如下文更详细解释，具有相同配置的裸片接合垫104及局部化空腔1 10的多个裸片可没有间隔层地直接彼此上下堆叠，且局部化空腔110在线接合不使下一上裸片发生短路的情况下允许下裸片的线接合。
每一局部化空腔110的长度尺寸可不同，但一般可略大于在其上方形成于裸片的相对表面上的接触垫群组。因此，局部化空腔110的位于单个接触垫(例如接触垫104a)下面的长度可小于局部化空腔110的位于多个接触垫(例如接触垫104b)下面的长度。应了解，在替代实施例中，所有局部化空腔可具有相同长度(例如接触垫104的最大群组的长度)。
图10A显示通过图10中的线10-10的截面图。在替代实施例中，每一局部化空腔110的垂直于裸片102的边缘的水平深度尺寸x及每一局部化空腔110的垂直于裸片102的下表面的垂直深度尺寸y可不同。然而，每一局部化空腔的水平及垂直深度尺寸均可足以允许将一个或一个以上线接合连接到第一半导体裸片102且在不接触第二半导体裸片102的情况下定位在安装于第一裸片上的第二裸片102的局部化空腔110内。任何局部化空腔110均可替代地由成角度的或成斜角的表面112部分地界定(而不是具有水平或垂直表面)，从而与裸片102的底表面形成偏斜的角度，例如图10中所显示(从与图10A的截面图相同的视角可见)。
如图中所见，空腔110是局部化的。也就是说，空腔110不会沿裸片102的边缘的整个长度延伸。当侧包含若干局部化空腔时，所述侧中的局部化空腔加起来小于所述侧的总长度。因此，局部化空腔110允许半导体裸片的低高度堆叠同时为每一裸片提供高程度的结构完整性，以防止裸片边缘在制造期间破裂或断裂。
参照图11的俯视图及图12的底部透视图，除了沿裸片102的一个或一个以上边缘的局部化空腔110之外或替代所述空腔110，可在裸片102的内部内形成局部化空腔114。也就是说，空腔114可向下形成到裸片102的背面表面中且与裸片102的边缘中的每一者间隔开。如下文更详细解释，半导体裸片中的此类空腔114可用于接纳安装于半导体裸片下面的表面上的无源或辅助裸片。所述表面可以是下裸片或衬底的表面。
在步骤212中，可对晶片100的背面(不活动)表面执行此项技术中已知的背面研磨工艺以将裸片102薄化到所需厚度。虽然在图7到12中显示单个裸片102，但上文描述的步骤是对所有裸片102同时仍在晶片100上执行的。在步骤216中，可从晶片100单个化经处理裸片中的每一者。通常仅存储器裸片在半导体封装内彼此上下堆叠，因此裸片102通常可以是例如快闪存储器的存储器裸片。然而，应了解，如上文所描述而形成的半导体裸片的类型可不同。
现在将参照图13的流程图及图14到21的各图来解释用于使用上文所描述的半导体裸片102来形成根据本发明的半导体封装的工艺。首先参照图14，可在步骤300中将第一半导体裸片102a安装在衬底120上。可在已知的粘合或共晶裸片接合工艺中经由裸片附装粘合剂将裸片102a安装到衬底120。图14中显示的裸片102a不包含局部化空腔110(因为裸片102a是底部裸片)。虽然不必要，但在替代实施例中裸片102a可包含局部化空腔110，例如，在替代实施例中以与裸片堆叠中的包含局部化空腔110的其它裸片相同的方式从晶片处理底部裸片102a。
虽然未显示，但衬底120可以是衬底的板的一部分，以便可为实现规模经济而批量处理根据本发明的半导体封装。虽然下文描述了单个半导体封装的制造，但应了解，以下说明可适用于在所述衬底板上形成的所有封装。衬底120可以是各种不同的芯片载体媒介，其中包含PCB、引线框或卷带式自动接合(TAB)卷带。当衬底102是PCB时，所述衬底可由上面形成有顶部及/或底部传导层的核心形成。所述核心可以是各种介电材料，例如聚酰亚胺层压片、包含FR4及FR5的环氧树脂、双马来酰亚胺三嗪(BT)等等。
传导层可由以下材料形成：铜或铜合金、镀铜或镀铜合金、合金42(42FE/58NI)、镀铜钢、或已知可用于衬底上的其它金属或材料。可将所述传导层蚀刻到已知用于在半导体裸片102与外部装置(未显示)之间传送信号的电导图案中。衬底120可另外包含在衬底120的上表面上形成接触垫122的暴露金属部分。当半导体封装是焊盘网格阵列(LGA)封装时，还可在衬底120的下表面上界定接触指(未显示)。接触垫122及/或接触指可在(例如)如此项技术中已知的电镀工艺中镀覆有一个或一个以上金层。
在步骤200中将半导体裸片102a附加到衬底120之后，可在步骤302中将线接合130附接在裸片102a上的线接合垫104与衬底120上的接触垫122之间。线接合130可在已知的线接合工艺中形成，例如正向或反向球形接合。在图中所显示的实施例中，线接合130将沿裸片102a的所有四个边缘被提供，但应了解，在进一步实施例中，裸片102a的一个或一个以上边缘可不包含接合垫104或线接合130。
根据本发明，局部化空腔110在不必以间隔层等将重叠的裸片间隔开的情况下允许多个半导体裸片以完全重叠的关系堆叠。因此，在步骤310中，可使用已知的裸片附接粘合剂将第二半导体裸片102b附加在半导体裸片102a顶上。当将裸片102b安装在裸片102a顶上时，来自底部裸片102a的线接合130配合在裸片102b的下侧上的局部化空腔110内。因此，来自裸片102a的线接合130不接触裸片102b也不使其短路。以此方式，局部化空腔允许在不使用间隔层的情况下将裸片102b直接安装在裸片102a顶上。在步骤312中，可以类似于上文所描述的方式将裸片102b线接合到具有第二组线接合130的衬底120。
如图13的流程图中的虚线箭头所指示，可重复步骤310及312来以类似于将裸片102b安装在裸片102a顶上的方式在裸片堆叠顶部上添加额外的裸片。图14显示安装于裸片堆叠(不具有线接合)上的一个额外裸片102c，但在进一步实施例中，裸片堆叠可包含仅两个裸片或三个以上裸片。对于每一堆叠式裸片，堆叠中的裸片的线接合配合在由安装在其上的下一裸片的局部化空腔110所形成的空间内。因此，所述堆叠可在仍具有低总高度的同时包含若干裸片。
在上文所描述的实施例中，线接合130可以是未经涂覆的金，但是其也可替代地为铜、铝或其它金属。在本发明进一步实施例中，可以聚合物绝缘将所述线接合预绝缘从而使得导线的表面不导电。此经预绝缘的接合线将允许在不用担心使裸片表面发生短路的情况下将导线拉紧到裸片102的上表面。这一实施例将允许局部化空腔110形成有更浅的垂直深度(因为接合线具有低高度)。适合用于本发明的经预绝缘的接合线的两个实例揭示于以下专利中：名称为“Resin Coated Bonding Wire，Method OfManufacturing The Same，And Semiconductor Device(经树脂涂布的接合线、制造经树脂涂布的接合线及半导体装置的方法)”的美国专利第5,396,104号及名称为“HighDensity Integrated Circuits And The Method Of Packaging the Same(高密度集成电路及封装高密度集成电路的方法)”的美国公开专利申请案第2004/0124545号，这两个专利的整体内容均以引用方式并入本文中。
现在参照图15的侧视图，在形成裸片堆叠并将其线接合到衬底120上的接合垫之后，可在步骤316中将裸片堆叠封闭在模制复合物150内，并在步骤318中将其从所述板单个化，从而形成成品半导体裸片封装160。模制复合物150可以是(例如)可从住友(Sumitomo)公司及日东电工(Nitto Denko)公司(总部均在日本)购得的已知环氧树脂。在某些实施例中，可在步骤320中将成品封装160任选地封闭在盖内。
在实施例中，用于封装160内的半导体裸片102可包含一个或一个以上快闪存储器芯片，且可能包含例如ASIC的控制器，以使得封装160可用作快闪存储器装置。应了解，封装160可包含半导体裸片，在本发明进一步实施例中所述半导体裸片经配置以执行其它功能。
应了解，局部化空腔110可以各种各样的配置在位于裸片102下侧处的边缘的一部分中形成以提供用于各种各样的线接合配置的空间。图16-19中显示两个此进一步实例。在图16及17的俯视及侧视图中，局部化空腔110提供用于将沿裸片102的第一边缘140的裸片接合垫104线接合到沿裸片102的第二邻近边缘142的接触垫122的空间。在俯视及侧视图18及19中，局部化空腔形成在裸片边缘140及142中具有开口的弯曲隧道，但经形成以使得边缘140与142之间的角完好无损。这一配置同样允许将沿裸片102的第一边缘的裸片接合垫104线接合到沿裸片102的第二边缘142的接触垫122。侧壁显示为弯曲的，但应了解，在替代实施例中，所述侧壁可以是直的且在邻近侧之间延伸。
在图20及21的俯视图及侧视图中，局部化空腔114不用于提供用于线接合的空间，而是提供用于组件146的空间，所述组件可以是无源组件或辅助半导体裸片。空腔114允许在衬底上将裸片102直接定位在组件146上部。空腔114将组件146与裸片102隔离。这一配置增加了可供组件表面安装到衬底120的位置的灵活性。
到此时为止，局部化空腔110已被揭示为在半导体裸片内形成。在图22中所示的替代实施例中，局部化空腔172可替代地在间隔层170中形成。间隔层170定位在一对裸片102a与102b之间。间隔层170可具有已知构造，只是一个或一个以上局部化空腔172可形成且提供于上文所描述的层170中。相比之下，间隔层170中的局部化空腔172与裸片102中的局部化空腔110之间的一个不同是，局部化空腔172可如图22中所示一直穿过间隔层170的厚度而形成。因此，例如图22中所示的间隔层170已将整个前角移除。应了解，在替代实施例中，局部化空腔172可在间隔层170的底表面中形成且仅部分地穿过如局部化空腔110中的厚度而延伸。
间隔层170的厚度仅需要足以防止来自裸片102a的线接合130接触裸片102b的下表面。在存在间隔层170的情况下，裸片102a、102b无需包含局部化空腔。
在进一步实施例中，间隔层170可提供为最底层，且包含用于容纳经表面安装的组件的一个或一个以上局部化空腔172，类似于上文针对图20及21所描述的裸片102。此实施例中的空腔172允许在衬底上将间隔层170直接定位在经表面安装的组件的顶部上。空腔172将所述组件与安装在其上方的裸片102隔离。这一配置增加了可供组件表面安装到所述衬底的位置的灵活性。本文中使用的术语“最底层”可指代安装在衬底120上的包含空腔172的间隔层170或安装在衬底120上的包含空腔114的裸片102。
出于图解说明及说明目的，上文已提供了对本发明的详细说明。不希望本发明为穷举性或将本发明限定为所揭示的具体形式。依据上述教示，可做出许多修改及改变。选择所描述的实施例以最好地解释本发明原理及其实际应用，从而使所属领域的技术人员能够在各种实施例中且使用适合于所预期的特定应用的各种修改来最好地利用本发明。希望本发明的范围由所附权利要求书来界定。

Claims (15)

1.一种制造半导体装置的方法，其包括以下步骤：
(a)将第一半导体裸片附加到衬底；
(b)对在邻近所述第一半导体裸片的侧的垫与位于所述衬底上的垫之间的导线进行线接合；
(c)形成第二半导体裸片，所述第二半导体裸片包含位于所述第二半导体裸片的侧中且占据少于整个侧的局部化空腔；及
(d)将所述第二半导体裸片附加在所述第一半导体裸片的顶部上，其中在所述步骤(b)中经线接合的所述导线定位于所述局部化空腔内。
2.如权利要求1所述的方法，其中所述形成在侧中包含局部化空腔的第二半导体裸片的步骤(c)包括形成具有局部化空腔的所述第二半导体裸片的步骤，所述局部化空腔形成于所述第二半导体裸片的底表面中且延伸到去往与所述第二半导体裸片的所述底表面相对的顶表面的途中。
3.如权利要求2所述的方法，其进一步包括在所述第二半导体裸片的所述顶表面上形成裸片接合垫的步骤(e)，所述裸片接合垫在所述顶表面中的位置对应于所述局部化空腔在所述第二半导体裸片的所述底表面中的位置。
4.如权利要求3所述的方法，其进一步包括以下步骤：形成第三半导体裸片的步骤(g)，所述第三半导体裸片包含位于所述第三半导体裸片的侧中且占据少于所述整个侧的局部化空腔；及将所述第三半导体裸片附加在所述第二半导体裸片的顶部上的步骤(h)，其中在所述步骤(f)中经连接的所述导线定位于所述第三半导体裸片的所述局部化空腔内。
5.如权利要求1或4所述的方法，其进一步包括在所述第二半导体裸片的一个或一个以上侧中形成多个局部化空腔的步骤(j)，所述第二半导体裸片的侧上的所有局部化空腔加起来占据少于所述整个侧。
6.如权利要求5所述的方法，其进一步包括对在位于所述第一半导体裸片上的垫与位于所述衬底上的垫之间的多个额外导线进行线接合的步骤(k)，每一线接合被接纳于所述第二半导体裸片的局部化空腔内。
7.如权利要求6所述的方法，其进一步包括沿所述第二半导体裸片的边缘在所述第二半导体裸片的顶表面上形成多个裸片接合垫的步骤(m)，在所述步骤(j)中形成于所述第二半导体裸片的所述表面的底部中的所述第二半导体裸片中的所述局部化空腔对应于在所述步骤(m)中形成于所述第二半导体裸片的所述顶表面中的所述裸片接合垫的位置。
8.如权利要求1所述的方法，其中所述形成在侧中包含局部化空腔的第二半导体裸片的步骤(c)包括形成穿过所述第二半导体裸片的底部部分的隧道的步骤，所述隧道在所述第二半导体裸片的邻近侧上具有开口。
9.一种半导体裸片，其包括：
集成电路；
一个或一个以上裸片接合垫，其形成于所述半导体裸片的活动表面上；及
一个或一个以上局部化空腔，其形成于所述半导体裸片的不活动表面中且沿着所述裸片的一个或一个以上侧，所述半导体裸片的任一侧中的所述一个或一个以上局部化空腔占据少于所述半导体裸片的整个侧。
10.如权利要求9所述的半导体裸片，其中所述一个或一个以上裸片接合垫在所述半导体裸片的所述活动表面上的位置对应于所述一个或一个以上局部化空腔在所述半导体裸片的所述不活动表面中的位置。
11.如权利要求10所述的半导体裸片，其进一步包括额外空腔，所述额外空腔形成于所述不活动表面内且从所述半导体裸片的每一侧向内留出空间以用于在其中接纳组件。
12.如权利要求11所述的半导体裸片，其中所述额外空腔经大小设定以在其中接纳所述额外组件而不使所述额外组件接触所述额外空腔的侧壁。
13.如权利要求12所述的半导体裸片，其中局部化空腔包括穿过所述半导体裸片的底部部分的隧道，所述隧道在所述半导体裸片的邻近侧上具有开口。
14.如权利要求13所述的半导体裸片，其中所述隧道包含弯曲侧壁。
15.如权利要求13所述的半导体裸片，其中所述隧道包含直侧壁。
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CN104681510A (zh) * 2013-12-03 2015-06-03 晟碟信息科技（上海）有限公司 用于嵌入半导体裸片的桥结构

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