KR100771874B1 - 반도체 탭 패키지 및 그 제조방법 - Google Patents
반도체 탭 패키지 및 그 제조방법 Download PDFInfo
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- KR100771874B1 KR100771874B1 KR1020060063506A KR20060063506A KR100771874B1 KR 100771874 B1 KR100771874 B1 KR 100771874B1 KR 1020060063506 A KR1020060063506 A KR 1020060063506A KR 20060063506 A KR20060063506 A KR 20060063506A KR 100771874 B1 KR100771874 B1 KR 100771874B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000010410 layer Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 20
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 5
- 239000012790 adhesive layer Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
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- 230000001070 adhesive effect Effects 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 51
- 230000007547 defect Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
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- 229920005989 resin Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
Abstract
Description
Claims (18)
- 장착 홀이 마련되어 있는 필름 기판;상기 필름 기판의 장착홀내에 삽입 고정되며, 표면에 범프를 포함하는 반도체 칩; 및상기 필름 기판 및 반도체 칩 일면에 상기 범프와 콘택되도록 형성되는 회로 배선을 포함하는 탭 패키지.
- 제 1 항에 있어서, 상기 범프 사이에 절연막이 형성되어 있는 탭 패키지.
- 제 2 항에 있어서, 상기 범프 및 절연막은 상기 필름 기판의 표면과 동일평면상에 위치되는 탭 패키지.
- 제 1 항에 있어서, 상기 반도체 칩은 그 가장자리에, 상기 필름 기판의 장착홀에 반도체 칩의 삽입시 걸림 턱 역할을 하는 홈부가 구비된 탭 패키지.
- 제 4 항에 있어서, 상기 장착 홀의 폭은 상기 반도체 칩의 홈부 사이의 거리인 탭 패키지.
- 제 4 항에 있어서, 상기 범프 표면으로부터 홈부 저부까지의 길이는 상기 필 름 기판의 두께가 같은 탭 패키지.
- 제 1 항에 있어서, 상기 반도체 칩과 필름 기판의 모서리 부분에 접착 부재가 더 형성되는 탭 패키지.
- 제 1 항에 있어서, 상기 회로 배선 상부에 회로 배선의 가장자리를 노출시키는 솔더 레지스트, 및상기 노출된 회로 배선상에 형성되는 도금층을 더 포함하는 탭 패키지.
- 가장자리에 홈부가 마련되어 있으며 일 표면에 범프를 포함하는 절연막이 형성된 반도체 칩을 제공하는 단계;장착 홀이 마련된 필름 기판을 준비하는 단계;상기 필름 기판의 장착 홀내에 상기 반도체 칩을 삽입 고정시키는 단계; 및상기 필름 기판 상부에 상기 반도체 칩의 범프와 콘택되도록 회로 배선을 형성하는 단계를 포함하는 탭 패키지의 제조방법.
- 제 9 항에 있어서, 반도체 칩을 제공하는 단계는,복수의 칩으로 구분하기 위한 경계선이 마련되어 있으며, 패드 전극을 구비하는 반도체 기판의 최종 결과물 상부에 절연막을 형성하는 단계;상기 패드 전극이 노출되도록 절연막을 식각하는 단계;노출된 패드 전극 상부에 선택적으로 범프를 형성하는 단계;상기 절연막과 범프를 평탄화하는 단계;상기 경계선 및 그 인접 부분을 소정 깊이만큼 식각하여 홈부를 형성하는 단계; 및상기 경계선을 따라 쏘잉하여 복수의 단위 칩을 형성하는 단계를 포함하는 탭 패키지의 제조방법.
- 제 10 항에 있어서, 상기 범프를 형성하는 단계는,상기 노출된 패드 전극 및 절연막 상부에 씨드층을 형성하는 단계;상기 패드 전극상의 씨드층이 노출되도록 씨드층 상부에 레지스트 패턴을 형성하는 단계; 및노출된 패드 전극상의 씨드층 상부에 선택적으로 범프를 도금하는 단계를 포함하는 탭 패키지 제조방법.
- 제 10 항에 있어서, 상기 범프를 형성하는 단계는,상기 노출된 패드 전극 상부에 도금 방식으로 범프를 형성하는 탭 패키지의 제조방법.
- 제 9 항에 있어서, 상기 필름 기판의 장착 홀내에 상기 반도체 칩을 삽입 고정시키는 단계는 상기 필름 기판의 표면과 상기 반도체 칩의 범프 표면이 동일 평 면상에 위치하도록 삽입 고정시키는 탭 패키지의 제조방법.
- 제 13 항에 있어서, 상기 필름 기판의 장착 홀 내에 상기 반도체 칩을 삽입 고정시키는 단계는,상기 필름 기판의 장착홀내에 상기 반도체 칩을 삽입시킨 다음, 상기 반도체칩과 필름 기판이 이루는 모서리 부분에 접착층을 형성하는 단계를 더 포함하는 탭 패키지의 제조방법.
- 제 9 항에 있어서, 상기 회로 배선을 형성하는 단계 이후에,상기 회로 배선의 가장자리는 노출시키면서 회로 배선의 상부를 덮는 솔더 레지스트 패턴을 형성하는 단계; 및상기 회로 배선의 가장자리에 도금 전극층을 형성하는 단계를 더 포함하는 탭 패키지의 제조방법.
- 가장자리에 홈부가 마련되어 있으며 일 표면에 범프를 포함하는 절연막이 형성된 반도체 칩을 제공하는 단계;장착 홀이 마련된 필름 기판을 준비하는 단계;상기 필름 기판의 장착 홀내에 상기 반도체 칩을 삽입 고정시키는 단계; 및상기 필름 기판 상부에 상기 반도체 칩의 범프와 콘택되도록 회로 배선을 형성하는 단계를 포함하며,상기 반도체 칩은 상기 가장자리의 홈부에 의해 상기 장착홀에 걸리게 되어 고정되고, 상기 범프 및 절연막의 표면과 상기 필름 기판의 표면과 일치되도록 반도체 칩이 삽입 고정되는 탭 패키지의 제조방법.
- 제 16 항에 있어서, 상기 필름 기판의 장착 홀 내에 상기 반도체 칩을 삽입 고정시키는 단계는,상기 필름 기판의 장착홀내에 상기 반도체 칩을 삽입시킨 다음, 상기 반도체칩과 필름 기판이 이루는 모서리 부분에 접착층을 형성하는 단계를 더 포함하는 탭 패키지의 제조방법.
- 제 16 항에 있어서, 상기 회로 배선을 형성하는 단계 이후에,상기 회로 배선의 가장자리는 노출시키면서 회로 배선의 상부를 덮는 솔더 레지스트 패턴을 형성하는 단계; 및상기 회로 배선의 가장자리에 도금 전극층을 형성하는 단계를 더 포함하는 탭 패키지의 제조방법.
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KR1020060063506A KR100771874B1 (ko) | 2006-07-06 | 2006-07-06 | 반도체 탭 패키지 및 그 제조방법 |
US11/812,307 US7560805B2 (en) | 2006-07-06 | 2007-06-18 | Semiconductor package and method of manufacturing the same |
US12/457,277 US20090246914A1 (en) | 2006-07-06 | 2009-06-05 | Semiconductor package and method of manufacturing the same |
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JP2010287592A (ja) * | 2009-06-09 | 2010-12-24 | Renesas Electronics Corp | 半導体装置、半導体ウェハおよびその製造方法 |
US20120199960A1 (en) * | 2011-02-07 | 2012-08-09 | Texas Instruments Incorporated | Wire bonding for interconnection between interposer and flip chip die |
US9830708B1 (en) | 2015-10-15 | 2017-11-28 | Snap Inc. | Image segmentation of a video stream |
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JP2001118882A (ja) | 1999-10-20 | 2001-04-27 | Matsushita Electronics Industry Corp | 半導体装置および半導体装置の実装構造 |
JP2003158141A (ja) | 2001-11-26 | 2003-05-30 | Shindo Denshi Kogyo Kk | 半導体装置 |
KR20030095460A (ko) * | 2002-06-10 | 2003-12-24 | 주식회사 하이닉스반도체 | 칩 사이즈 패키지 제조방법 |
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US4670770A (en) * | 1984-02-21 | 1987-06-02 | American Telephone And Telegraph Company | Integrated circuit chip-and-substrate assembly |
EP0683517B1 (en) * | 1994-05-09 | 2002-07-24 | Nec Corporation | Semiconductor device having semiconductor chip bonded to circuit board through bumps and process of mounting thereof |
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JPH11307624A (ja) | 1998-04-24 | 1999-11-05 | Fujitsu Ltd | 半導体装置用キャリア及びその製造方法 |
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2006
- 2006-07-06 KR KR1020060063506A patent/KR100771874B1/ko active IP Right Grant
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2007
- 2007-06-18 US US11/812,307 patent/US7560805B2/en active Active
-
2009
- 2009-06-05 US US12/457,277 patent/US20090246914A1/en not_active Abandoned
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JP2001118882A (ja) | 1999-10-20 | 2001-04-27 | Matsushita Electronics Industry Corp | 半導体装置および半導体装置の実装構造 |
JP2003158141A (ja) | 2001-11-26 | 2003-05-30 | Shindo Denshi Kogyo Kk | 半導体装置 |
KR20030095460A (ko) * | 2002-06-10 | 2003-12-24 | 주식회사 하이닉스반도체 | 칩 사이즈 패키지 제조방법 |
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US20080006941A1 (en) | 2008-01-10 |
US20090246914A1 (en) | 2009-10-01 |
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