JP4737995B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4737995B2 JP4737995B2 JP2005007277A JP2005007277A JP4737995B2 JP 4737995 B2 JP4737995 B2 JP 4737995B2 JP 2005007277 A JP2005007277 A JP 2005007277A JP 2005007277 A JP2005007277 A JP 2005007277A JP 4737995 B2 JP4737995 B2 JP 4737995B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring
- external electrode
- wiring board
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
第1の面に複数の電極パッドを有し、前記第1の面の反対面となる第2の面に複数の外部電極端子を有し、前記電極パッドと前記外部電極端子は前記第1の面から前記第2の面に亘って貫通して設けられる導体で電気的に接続され、前記第2の面には前記外部電極端子から所定寸法離れて設けられかつ前記外部電極端子の厚さ以下になる絶縁性の第1の絶縁層(例えば、外部電極端子と同程度の厚さの絶縁層)を有し、前記第1の面には第2の絶縁層を有する配線基板と、
前記配線基板の前記第1の面の前記第2の絶縁層上に接着剤を介して固定される複数の電極を有する半導体チップと、
前記半導体チップの電極と前記配線基板の前記電極パッドを接続する導電性のワイヤと、
前記配線基板の前記第1の面全体に設けられ、前記半導体チップ及び前記ワイヤを覆う絶縁体からなる封止体とを有することを特徴とする。
(a)第1の面及び前記第1の面の反対面となる第2の面を有し、かつ製品形成部がマトリックス状に配列され、前記製品形成部は、前記第1の面に複数の電極パッドを有し、前記第2の面に複数の外部電極端子を有し、前記電極パッドと前記外部電極端子は前記第1の面から前記第2の面に亘って貫通して設けられる導体で電気的に接続され、前記第2の面には前記外部電極端子から所定寸法離れて設けられかつ前記外部電極端子の厚さ以下になる絶縁性の第1の絶縁層(例えば、外部電極端子と同程度の厚さの絶縁層)を有し、前記第1の面に第2の絶縁層を有する構造となる配線基板を準備する工程と、
(b)前記製品形成部の前記第1の面の前記第2の絶縁層上に接着剤によって複数の電極を有する半導体チップを固定する工程と、
(c)前記製品形成部において、前記半導体チップの電極と電極パッドを導電性のワイヤで電気的に接続する工程と、
(d)前記各製品形成部の前記半導体チップ及び前記接続手段を覆うように前記配線母基板の前記第1の面に絶縁性の樹脂層を形成する工程と、
(e)前記配線母基板及び前記樹脂層を前記製品形成部の境界で切断して複数の半導体装置を形成する工程とによって製造される。
Claims (4)
- 第1の面、前記第1の面に形成された複数の電極パッド、前記第1の面の反対面となる第2の面、前記第1の面から前記第2の面に亘って貫通して設けられる複数の貫通孔、前記複数の貫通孔のそれぞれの内部に形成された複数の導体、前記第2の面に形成され、かつ前記複数の導体を介して前記複数の電極パッドとそれぞれ電気的に接続された複数の外部電極端子、および前記複数の外部電極端子が露出するように、前記第2の面の中央部に形成された第1の絶縁層を有する配線基板と、
上面、前記上面に形成された複数の電極、および前記上面の反対面となる下面を有し、前記下面が前記配線基板の前記第1の面と対向するように、前記配線基板の前記第1の面に固定された半導体チップと、
前記半導体チップの前記複数の電極と前記配線基板の前記複数の電極パッドとをそれぞれ電気的に接続する複数のワイヤと、
前記半導体チップ、前記複数のワイヤ、および前記配線基板の前記第1の面を封止する封止体と、
を含み、
前記配線基板の前記第2の面の平面形状は、四角形から成り、
前記複数の外部電極端子は、前記第2の面における辺に沿って形成されており、
前記配線基板の外形寸法は、前記半導体チップの外形寸法よりも大きく、
前記複数の外部電極端子のそれぞれの周面は、全周に亘って前記第1の絶縁層から露出しており、
前記複数の外部電極端子のそれぞれと、前記配線基板の前記第2の面における前記外縁との間には、前記第1の絶縁層は形成されていなく、
前記複数の外部電極端子のそれぞれの前記辺と交差する方向における長さは、前記複数の電極パッドのそれぞれの前記辺と交差する方向における長さよりも長いことを特徴とする半導体装置。 - 前記第1の絶縁層は前記外部電極端子の厚さ以下になっていることを特徴とする請求項1に記載の半導体装置。
- 前記複数の外部電極端子のそれぞれの外縁は、前記配線基板の前記第2の面における外縁よりも内側に位置していることを特徴とする請求項2に記載の半導体装置。
- 前記配線基板の前記第1の面には、前記複数の電極パッドを露出するように、第2の絶縁層が形成されており、
前記半導体チップは、接着剤を介して前記第2絶縁層に固定されており、
前記第2の絶縁層において、前記半導体チップが搭載される領域と前記複数の電極パッドとの間にはスリットが設けられていることを特徴とする請求項3に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005007277A JP4737995B2 (ja) | 2005-01-14 | 2005-01-14 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005007277A JP4737995B2 (ja) | 2005-01-14 | 2005-01-14 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006196734A JP2006196734A (ja) | 2006-07-27 |
JP4737995B2 true JP4737995B2 (ja) | 2011-08-03 |
Family
ID=36802557
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005007277A Expired - Fee Related JP4737995B2 (ja) | 2005-01-14 | 2005-01-14 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4737995B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007019275A (ja) * | 2005-07-07 | 2007-01-25 | Rohm Co Ltd | 半導体装置、基板及び半導体装置の製造方法 |
JP2009182104A (ja) * | 2008-01-30 | 2009-08-13 | Toshiba Corp | 半導体パッケージ |
JP5299549B1 (ja) * | 2012-10-12 | 2013-09-25 | 富士ゼロックス株式会社 | 露光装置、画像形成装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06334061A (ja) * | 1993-05-19 | 1994-12-02 | Ibiden Co Ltd | 半導体搭載用基板 |
JP4397111B2 (ja) * | 2000-09-08 | 2010-01-13 | 新日本無線株式会社 | チップサイズパッケージ |
JP2002176120A (ja) * | 2000-12-07 | 2002-06-21 | Sanyo Electric Co Ltd | 半導体装置 |
-
2005
- 2005-01-14 JP JP2005007277A patent/JP4737995B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2006196734A (ja) | 2006-07-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10431556B2 (en) | Semiconductor device including semiconductor chips mounted over both surfaces of substrate | |
JP3619773B2 (ja) | 半導体装置の製造方法 | |
US8659151B2 (en) | Semiconductor device and manufacturing method thereof | |
US7518250B2 (en) | Semiconductor device and a method for manufacturing of the same | |
US7719104B2 (en) | Circuit board structure with embedded semiconductor chip and method for fabricating the same | |
US20070164457A1 (en) | Semiconductor package, substrate with conductive post, stacked type semiconductor device, manufacturing method of semiconductor package and manufacturing method of stacked type semiconductor device | |
US20120086111A1 (en) | Semiconductor device | |
KR100212607B1 (ko) | 반도체 칩 팩키지 | |
JP2009212315A (ja) | 半導体装置及びその製造方法 | |
US20160079207A1 (en) | Semiconductor device and method for manufacturing same | |
KR980012316A (ko) | 반도체 장치 및 그 제조 방법 | |
KR20100069589A (ko) | 반도체 디바이스 | |
US10811378B2 (en) | Electronic package and manufacturing method thereof | |
US8098496B2 (en) | Wiring board for semiconductor device | |
JP5378643B2 (ja) | 半導体装置及びその製造方法 | |
JP4737995B2 (ja) | 半導体装置 | |
JP4963989B2 (ja) | 半導体素子搭載用基板およびその製造方法 | |
JP2010010269A (ja) | 半導体装置、半導体装置製造用中間体およびそれらの製造方法 | |
JP2010278138A (ja) | 半導体装置及びその製造方法 | |
JP4038021B2 (ja) | 半導体装置の製造方法 | |
US20120048595A1 (en) | Wiring board and method of manufacturing a semiconductor device | |
JP5587464B2 (ja) | 半導体装置の製造方法 | |
KR20060017294A (ko) | 소형화된 반도체 집적회로 패키지 및 이에 사용되는인쇄회로기판 | |
JP4552777B2 (ja) | 半導体装置の製造方法 | |
JP4917979B2 (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071213 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091215 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100112 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100308 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100427 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20100511 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100621 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100713 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100910 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110426 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110426 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140513 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |