CN107437545B - 半导体器件与其的制造方法 - Google Patents

半导体器件与其的制造方法 Download PDF

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Publication number
CN107437545B
CN107437545B CN201610951558.7A CN201610951558A CN107437545B CN 107437545 B CN107437545 B CN 107437545B CN 201610951558 A CN201610951558 A CN 201610951558A CN 107437545 B CN107437545 B CN 107437545B
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contact pad
width
semiconductor device
solder layer
contact
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CN107437545A (zh
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陈英儒
苏安治
吴集锡
余振华
叶德强
陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体器件结构的制造方法包括在第一器件与第二器件之间形成结合体或接点。第一器件包括集成无源器件及设置在其上的第一接触垫。第二器件包括第二接触垫。第一接触垫具有带有第一横向范围的第一表面。第二接触垫具有带有第二横向范围的第二表面。第二横向范围的宽度小于第一横向范围的宽度。接点结构包括第一接触垫、第二接触垫以及夹置于第一接触垫与第二接触垫之间的焊料层。焊料层具有锥形侧壁，且锥形侧壁在从第一接触垫的第一表面远离而朝向第二接触垫的第二表面的方向上延伸。第一表面或第二表面中的至少一者实质上是平坦的。

Description

半导体器件与其的制造方法
技术领域
本发明实施例是涉及一种半导体器件与其制造方法，且尤其涉及一种具有无间隙、空隙、及/或孔洞的接点结构的半导体器件与其制造方法。
背景技术
半导体器件被用于例如个人计算机、手机、数码相机、及其他电子设备等各种电子应用中。半导体器件通常是通过以下方式来制作：在半导体衬底上依序沉积各种绝缘层或介电层、导电层、以及半导体材料层；以及利用光刻(lithography)对所述各种材料层进行图案化以在其上形成电路组件及元件。可在单个半导体晶片(semiconductorwafer)上制造数十或数百个集成电路。通过沿着切割道(scribe line)锯切集成电路来单体化多个个别的管芯(die)。接着将所述个别的管芯单独地封装，例如在多芯片模组中封装、或以其他类型的封装方式进行封装。
半导体行业通过不断缩小最小特征大小来不断地提高各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，以使得更多的组件能够被集成到给定区域中。在某些应用中，这些较小的电子组件使用比过去的封装件更小且更先进的封装系统。
发明内容
根据本发明的一些实施例，一种半导体器件的制造方法至少包括以下步骤。提供第一半导体器件以及第二半导体器件。第一半导体器件包括第一接触垫，第二半导体器件包括第二接触垫。在第一接触垫或第二接触垫中的一者上形成实质上凹的表面轮廓。在第一接触垫上电镀焊料层。焊料层具有与第一接触垫的第二表面外形轮廓实质上相似的第一表面外形轮廓。将焊料层在第二接触垫上对齐。使焊料层落在第二接触垫上。结合焊料层与第二接触垫。
根据本发明的另一些实施例，一种半导体器件的制造方法至少包括以下步骤。提供第一半导体器件以及第二半导体器件，第二半导体器件包括接触垫，接触垫具有第一实质上平坦的表面。在第一半导体器件的一部分上电镀焊料层，焊料层具有第二实质上平坦的表面。将第一实质上平坦的表面在第二实质上平坦的表面上对齐。使第一实质上平坦的表面落在第二实质上平坦的表面上。结合第一实质上平坦的表面与第二实质上平坦的表面。
根据本发明的又一些实施例，一种器件封装件可包括第一半导体器件、第二半导体器件以及接点结构。第一半导体器件包括集成无源器件及设置在集成无源器件上的第一接触垫，第一接触垫的第一部分设置在第一半导体器件的外部部分的第一凹陷开口中，第一部分耦合至集成无源器件，第一接触垫具有包括第一横向范围的第一表面。第二半导体器件包括重布线层及设置在重布线层上的第二接触垫，第二接触垫的第二部分设置在第二半导体器件的外部部分的第二凹陷开口中，第二部分耦合至重布线层，第二接触垫具有包括第二横向范围的第二表面，其中跨越第二横向范围的第一距离小于跨越第一横向范围的第二距离。接点结构夹置于第一半导体器件与第二半导体器件之间，接点结构包括第一接触垫、第二接触垫、及焊料层，焊料层夹置于第一接触垫与第二接触垫之间，焊料层具有锥形的侧壁轮廓，锥形的侧壁轮廓以连续减小的宽度从第一表面往第二表面延伸，其中第一表面或第二表面中的至少一者是实质上平坦的。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征可不按比例绘制。事实上，为论述或说明清晰起见，可任意增大或缩小各种特征的尺寸。
图1A及图1B为根据代表性实施例所示出的一种在第一器件与第二器件之间形成的接点结构的剖视图。
图2A及图2B为根据另一代表性实施例所示出的一种在第一器件与第二器件之间形成的接点结构的剖视图。
图3A及图3B为根据又一代表性实施例所示出的一种在第一器件与第二器件之间形成的接点结构的剖视图。
图4为根据图1A中大体示出的代表性实施例所示出的接点总成的元件的相对尺寸的剖视图。
图5为根据图2A中大体示出的代表性实施例所示出的接点总成的元件的相对尺寸的剖视图。
图6为根据图3A中大体示出的代表性实施例所示出的接点总成的元件的相对尺寸的剖视图。
图7为根据代表性实施例所示出的锥形接点结构的剖视图。
图8为根据另一代表性实施例所示出的锥形接点结构的剖视图。
图9为根据又一代表性实施例所示出的锥形接点结构的剖视图。
图10是根据代表性实施例的一种形成接点结构的方法的流程图。
图11是根据另一代表性实施例的一种形成接点结构的方法的流程图。
图12是根据又一代表性实施例的一种形成接点结构的方法的流程图。
图13是根据代表性实施例的一种具有经结合的集成无源器件(integratedpassive device，IPD)的叠层封装(Package-on-Package，PoP)结构的剖视图，所述经结合的集成无源器件具有结合接点。
附图标记：
110、210、310：第一半导体器件；
111、211、311：集成无源器件封装衬底；
112、212、312、1312：集成无源器件；
113、213、313：第一接触垫；
114、214、314、714、814、914：焊料层；
120、220、320：第二半导体器件；
121、221、321：封装体层；
122、222、322：第二接触垫；
123、223、323：重布线层；
195、295、395：接点结构；
795、895、995：锥形接点结构；
1000、1100、1200：方法；
1010、1020、1030、1040、1050、1110、1120、1130、1140、1150、1210、1220、1230、1240、1250：步骤；
1300：叠层封装结构；
1301a、1301b、1311：导电连接件；
1302：电性连接件；
1303：集成电路管芯；
1315：第一器件封装件；
1320：衬底；
1325、1335：结合垫；
1330：穿孔；
1340：打线接合；
1350、1360：堆叠管芯；
1355：第二器件封装件；
1390：模塑材料；
A、B、W、W’：宽度；
C、C’：凹腔。
具体实施方式
以下发明内容提供用于实施所提供的目标的不同特征的许多不同实施例或实例。以下所描述的构件及配置的具体实例是为了以简化的方式传达本发明为目的。当然，这些仅仅为实例而非用以限制。举例来说，在以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且也可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外，本发明在各种实例中可使用相同的元件符号和/或字母来指代相同或类似的部件。元件符号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例和/或配置本身之间的关系。
另外，为了易于描述附图中所示出的一个构件或特征与另一元件或特征的关系，本文中可使用例如”在...下”、”在...下方”、”下部”、”在…上”、”在…上方”、”上部”及类似术语的空间相对术语。除了附图中所示出的定向之外，所述空间相对术语意欲涵盖元件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地作出解释。
传统的接点结构及其形成方法可包括或生成位于在经结合的半导体器件之间形成的接点结构内的一个或多个间隙、空隙、或孔洞。此种间隙、空隙、或孔洞可夹置于在经结合的半导体器件之间的导电材料(例如，焊料)内，且导电材料将经结合的半导体器件电耦合于一起。本文中使用的用语“焊料”可被理解为意指可应用热能来进行回焊(或可以通过其他方式实现至少局部的相变或相转变)的任何导电材料或局部导电材料。此种间隙、空隙、或孔洞一般会使与其相关联的接点结构在品质控制测试期间易于出现可靠性考虑因素。本发明的代表性实施例在经接合/经结合的半导体器件之间提供实质上无间隙、空隙、及/或孔洞的改良的接点结构/结合体结构。
图1A及图1B代表性地示出根据实施例的第一半导体器件110与第二半导体器件120之间的接点结构195的形成。第一半导体器件110包括集成无源器件(integratedpassive device，IPD)112以及集成无源器件封装衬底111。在代表性实施例中，第一半导体器件110可包括硅衬底。在其他实施例中，第一半导体器件110可包括一个或多个其他适合的元素半导体(例如金刚石或锗)、适合的化合物半导体(例如砷化镓、碳化硅、砷化铟、或磷化铟)、或适合的合金半导体(例如碳化硅锗、磷化镓砷、或磷化镓铟)。衬底可为绝缘体上硅(silicon on insulator，SOI)或蓝宝石上硅(silicon on sapphire)。在一些实施例中，第一半导体器件110可包括梯度半导体层及/或可进一步包括上覆于不同类型的另一半导体层上的半导体层，例如硅层在硅锗层上。在其他实施例中，化合物半导体衬底可包括多层硅结构，或硅衬底可包括多层化合物半导体结构。衬底在一个实施例中可基于例如玻璃纤维强化树脂芯(fiberglass reinforced resin core)等绝缘芯。代表性芯材料包括例如FR4等玻璃纤维树脂。其他芯材料包括双马来酰亚胺三嗪(bismaleimide-triazine，BT)树脂、或作为另外一种选择，包括其他印刷电路板(printed circuit board，PCB)材料或膜。可使用例如味之素构成膜(Ajinomoto build-up film，ABF)或层压材料等构成膜(build-upfilm)来制作第一半导体器件110。在替代实施例或联合实施例中，第一半导体器件110以及集成无源器件封装衬底111可包含封装体或模塑化合物材料、聚合物(例如，环氧树脂、乙烯酯、聚酯及/或类似聚合物)、纤维强化(fiber-reinforced)聚合物(例如包含玻璃、碳、芳族聚酰胺(aramid)、玄武岩等)及/或类似材料。
除无源器件外，第一半导体器件110还可包括有源器件。有源器件可包括多种多样的器件(例如，二极管、晶体管、场效晶体管、晶闸管(thyristor)及/或类似器件)。无源器件(例如，电容器、电阻器、电感器及/或类似器件)可用于提供第一半导体器件110的特定设计所需的结构特征及/或功能特征。可利用任何适合的方法在集成无源器件封装衬底111内或集成无源器件封装衬底111上形成有源器件以及无源器件。
通过图案化以及刻蚀，例如可自集成无源器件封装衬底111面对前侧(或顶部)的外部表面形成凹陷，以暴露出集成无源器件112的至少一部分。图案化可通过任何可接受的工艺来实现，例如可通过对光敏材料采用光刻曝光、然后进行显影以及刻蚀(例如，各向异性刻蚀)来实现。可随后采用沉积导电特征结构于凹陷中及凹陷上并图案化导电特征结构的方式来产生第一接触垫113。在一些实施例中，晶种层(seed layer)可包括在暴露出集成无源器件112的凹陷中沉积的金属层。晶种层可为单层或具有由不同材料形成的多个子层的复合层。在一些实施例中，晶种层可包括钛层以及位于钛层上的铜层。晶种层可利用例如物理气相沈积(physical vapor deposition，PVD)等来形成。可接着在晶种层上形成光刻胶并对光刻胶进行图案化。光刻胶可被沉积(例如，通过旋转涂布(spin coating)或类似方法)并被暴露至光下来进行图案化。光刻胶的图案对应于随后形成的第一接触垫113所定义的特征。图案化会形成贯穿光刻胶的开口以暴露出晶种层。在光刻胶的开口中以及晶种层被暴露出的部分上形成导电材料。导电材料可通过镀覆(plating)(例如，电镀(electroplating)或无电电镀(electroless plating)等)、溅镀(sputtering)、物理气相沉积等方法来形成。导电材料可包含例如铜、钛、钨、铝等金属。其后，移除光刻胶以及未形成有导电材料在其上的部分晶种层。光刻胶可通过可接受的灰化工艺(ashing process)或剥除工艺(stripping process)(例如利用氧等离子(oxygen plasma)等)来移除。一旦光刻胶被移除，便可例如利用适合的刻蚀工艺(例如，湿式刻蚀(wet etching)或干式刻蚀(dryetching))移除晶种层被暴露出的部分。晶种层的剩余部分以及导电材料形成第一接触垫113。第一接触垫113可被形成为具有约10μm至约70μm之间(例如约50μm)的厚度(例如，从集成无源器件封装衬底111面对前侧的表面到第一接触垫113面对前侧的表面)。
如本文中将参照图4、图5以及图6进一步论述，通过选择第一接触垫113的凹陷部分的横向宽度(例如，图4的宽度B)对第一接触垫113的横向范围的宽度(例如，图4的宽度W’)的比率，可产生第一接触垫113的实质上平坦且面对前侧的表面。参见在2015年7月31日提出申请且标题为“具有堆叠孔的重布线(Redistribution Lines Having StackingVias)”的美国专利申请第14/815,169号，所述美国专利申请在此并入本文供参考。
将焊料层114沉积在第一接触垫113的顶表面上。在代表性实施例中，可通过将焊料材料电镀至第一接触垫113的顶表面来沉积焊料层114；然而，可替代地或联合地采用用于形成焊料层114的各种其他沉积技术(例如，蒸镀(evaporation)、印刷、焊料转移(soldertransfer)等)。在焊料材料被电镀在第一接触垫113上的情形中，第一接触垫113的顶表面的形状会被转移至焊料层114(例如，在此种情形中，平坦的或实质上平坦的表面)。本文中使用的“实质上平坦的”可被理解为意指特定特征的表面的任何两个区域的高度差不超过所述特征的厚度的约10％。例如，若顶表面中任何两个区域均不具有大于第一接触垫113的厚度的约10％(例如，第一接触垫113的顶表面与集成无源器件封装衬底111的顶表面之间的最小距离)的高度差，则可将第一接触垫113的顶表面视为平坦的或实质上平坦的。再例如，若顶表面中的任何两个区域均不具有大于焊料层114的厚度的约10％的高度差，则可将焊料层114的顶表面视为平坦的或实质上平坦的。
第二半导体器件120包括封装体层121、重布线层(redistribution layer，RDL)123以及第二接触垫122。封装体层121可包含模塑化合物、聚合物及/或类似材料。在一些代表性实施例中，如以上对第一半导体器件110进行的代表性陈述一样，第二半导体器件120可包括硅衬底或其他衬底材料。第二半导体器件120可包括有源器件以及无源器件。有源器件可包括多种多样的器件(例如，二极管、晶体管、场效晶体管、晶闸管及/或类似器件)。无源器件(例如，电容器、电阻器、电感器、及/或类似器件)可用于提供特定第二半导体器件120的特定设计所需的结构特征及/或功能特征。可利用任何适合的方法形成有源器件以及无源器件。
通过光刻图案化及刻蚀，例如可自封装体层121面对前侧的外部表面形成凹陷，以暴露出重布线层123的至少一部分。图案化可通过任何可接受的工艺来实现。可随后采用沉积金属化特征结构于凹陷中及凹陷上并图案化金属化特征结构的方式来产生第二接触垫122。在一些实施例中，晶种层可包括沉积在被形成至重布线层123的凹陷中的金属层。用于形成第二接触垫122的晶种层可具有与用于形成第一接触垫113的晶种层相同的组成物(或与用于形成第一接触垫113的晶种层不同的组成物)。用于形成第二接触垫122的晶种层的工艺可相同于(或不同于)用于形成第一接触垫113的晶种层的工艺。可接着在所述晶种层上形成光刻胶并对所述光刻胶进行图案化。光刻胶的图案对应于随后形成的第二接触垫122所定义的特征。其后，可在晶种层上沉积导电材料以形成第二接触垫122。用于形成第二接触垫122的工艺及材料可相同于(或不同于)用于形成第一接触垫113的工艺及材料。第二接触垫122可被形成为具有约10μm至约70μm之间(例如约50μm)的厚度(例如，从封装体层121面对前侧的表面到第二接触垫122面对前侧的表面)。
例如在图1A中代表性地示出般，可将第二接触垫122形成为具有面对前侧且实质上呈现为凹的形状或中凹(dished)形状的顶表面轮廓。例如，在采用在晶种层上电镀导电材料的情形中，导电材料将会大体以实质上各向同性的方式来沉积，而大体产生第二接触垫122的凹的形状或中凹形状的顶表面轮廓。第二接触垫122的实质上凹的凹腔C的深度例如是约1.0μm到约7.0μm。
参照图1B，可使用拾取及放置(pick-and-place)工具使第一半导体器件110与第二半导体器件120在实体上对齐(physically align)。在对齐之后，拾取及放置工具通过将焊料层114的顶表面接触第二接触垫122的顶表面而使第一半导体器件110落在第二半导体器件120上。实行热(例如，回焊)工艺来形成接点结构195。接点结构195将第一半导体器件110与第二半导体器件120在实体上结合且电结合。如图1B中代表性示出般，焊料层114的一部分可润湿第二接触垫122位于第二接触垫122的横向范围外的侧壁的一部分。其后可实行可选的焊剂清洁工艺(flux cleaning process)。在其他实施例中，可使用例如金属对金属结合(metal-to-metal bonding)等任何适合的连接件或连接工艺。
本文中使用的“相似于(或不同于)”及其在上下文中的变型可被理解为意指所提及的元件可通过一个或多个相似的(或不同的)工艺形成及/或可包含一种或多种相似的(或不同的)材料。
图2A及图2B代表性地示出根据实施例的第一半导体器件210与第二半导体器件220之间的接点结构295的形成。第一半导体器件210可相似于(或不同于)第一半导体器件110。第一半导体器件210包括集成无源器件212，且集成无源器件212可相似于(或不同于)集成无源器件112。第一半导体器件210包括集成无源器件封装衬底211，且集成无源器件封装衬底211可相似于(或不同于)集成无源器件封装衬底111。集成无源器件封装衬底211可包括有源器件以及无源器件，且有源器件以及无源器件相似于(或不同于)构成集成无源器件封装衬底111的有源器件以及无源器件。集成无源器件封装衬底211可包括第一接触垫213，且第一接触垫213可相似于(或不同于)第一接触垫113。可将第一接触垫213形成为具有约10μm至约70μm之间(例如约50μm)的厚度(例如，从集成无源器件封装衬底211面对前侧的表面到第一接触垫213面对前侧的表面)。
例如在图2A中代表性地示出般，可将第一接触垫213形成为具有面对前侧且实质上呈现为凹的形状或中凹形状的顶表面轮廓。例如，在晶种层上电镀导电材料来形成第一接触垫213的情形中，导电材料将会大体以实质上各向同性的方式来沉积，而大体产生第一接触垫213的凹的形状或中凹形状的顶表面轮廓。第一接触垫213的凹的或实质上凹的凹腔C’的深度例如是约1.0μm至约7.0μm。
焊料层214可相似于(或不同于)焊料层114。在代表性实施例中，可通过将焊料材料电镀至第一接触垫213的顶表面来沉积焊料层214；然而，可替代地或联合地采用用于形成焊料层214的各种其他沉积技术。在焊料材料被电镀在第一接触垫213上的情形中，第一接触垫213的顶表面的形状会被转移至焊料层214(例如，在此种情形中，凹的或实质上凹的凹腔或形状)。
第二半导体器件220可相似于(或不同于)第二半导体器件120。例如，第二半导体器件220可包括封装体层221、重布线层223以及第二接触垫222。第二接触垫222可被形成为具有约10μm至约70μm之间(例如约50μm)的厚度(例如，从封装体层221面对前侧的表面到第二接触垫222面对前侧的表面)。
通过选择第二接触垫222的凹陷部分的横向宽度(例如，图5的宽度A)对第二接触垫222的横向范围的宽度(例如，图5的宽度W)的比率，可产生第二接触垫222的实质上平坦且面对前侧的表面。
参照图2B，可使用拾取及放置工具使第一半导体器件210与第二半导体器件220在实体上对齐。在对齐之后，拾取及放置工具通过将焊料层214的顶表面接触第二接触垫222的顶表面而使第一半导体器件210落在第二半导体器件220上。实行热工艺来形成接点结构295。接点结构295将第一半导体器件210与第二半导体器件220在实体上结合且电结合。如图2B中代表性地示出般，焊料层214的一部分可润湿第二接触垫222位于第二接触垫222的横向范围外的侧壁的一部分。其后可实行可选的焊剂清洁工艺。在其他实施例中，可使用例如金属对金属结合等任何适合的连接件或连接工艺。
图3A及图3B代表性地示出根据另一实施例的第一半导体器件310与第二半导体器件320之间的接点结构395的形成。第一半导体器件310可相似于(或不同于)第一半导体器件110。第一半导体器件310包括集成无源器件312，且集成无源器件312可相似于(或不同于)集成无源器件112。第一半导体器件包括集成无源器件封装衬底311，且集成无源器件封装衬底311可相似于(或不同于)集成无源器件封装衬底111。集成无源器件封装衬底311可包括有源器件以及无源器件，且有源器件以及无源器件相似于(或不同于)构成集成无源器件封装衬底111的有源器件以及无源器件。集成无源器件封装衬底311可包括第一接触垫313，且第一接触垫313可相似于(或不同于)第一接触垫113。可将第一接触垫313形成为具有约10μm至约70μm之间(例如约50μm)的厚度(例如，从集成无源器件封装衬底311面对前侧的表面到第一接触垫313面对前侧的表面)。
例如在图3A中代表性地示出般，可将第一接触垫313形成为具有面对前侧且实质上呈现为平坦的形状。通过选择第一接触垫313的凹陷部分的横向宽度(例如，图6的宽度B)对第一接触垫313的横向范围的宽度(例如，图6的宽度W’)的比率，可产生第一接触垫313的实质上平坦且面对前侧的表面。
将焊料层314沉积在第一接触垫313的顶表面上。在代表性实施例中，可将焊料层314电镀至第一接触垫313的顶表面；然而，可替代地或联合地采用用于形成焊料层314的各种其他沉积技术(例如，蒸镀、印刷、焊料转移等)。在焊料材料被电镀在第一接触垫313上的情形中，第一接触垫313的顶表面的形状会被转移至焊料层314(例如，在此种情形中，平坦的或实质上平坦的形状)。
第二半导体器件320可相似于(或不同于)第二半导体器件320。例如，第二半导体器件320可包括封装体层321、重布线层323以及第二接触垫322。第二接触垫322可被形成为具有约10μm至约70μm之间(例如约50μm)的厚度(例如，从封装体层321面对前侧的表面到第二接触垫322面对前侧的表面)。
通过选择第二接触垫322的凹陷部分的横向宽度(例如，图6的宽度A)对第二接触垫322的横向范围的宽度(例如，图6的宽度W)的比率，可产生第二接触垫322的实质上平坦且面对前侧的表面。
参照图3B，可使用拾取及放置工具使第一半导体器件310与第二半导体器件320在实体上对齐。在对齐之后，拾取及放置工具通过将焊料层314的顶表面接触第二接触垫322的顶表面而使第一半导体器件310落在第二半导体器件320上。实行热工艺来形成接点结构395。接点结构395将第一半导体器件310与第二半导体器件320在实体上结合且电结合。如图3B中代表性地示出般，焊料层314的一部分可润湿第二接触垫322位于第二接触垫322的横向范围外的侧壁的一部分。其后可实行可选的焊剂清洁工艺。在其他实施例中，可使用例如金属对金属结合等任何适合的连接件或连接工艺。
图4代表性地示出根据图1A中针对第一半导体器件110以及第二半导体器件120所大体示出的代表性实施例在后续形成接点结构或总成的元件的相对尺寸。宽度B表示第一接触垫113的凹陷部分的横向宽度。宽度W’表示第一接触垫113的横向宽度。在宽度W’以及宽度B的数量级为约1E-06μm至1E-05μm的情形中，根据前面并入本文供参考的美国专利申请第14/815,169号，约为5:2的W’:B的比率将产生第一接触垫113的实质上平坦且面对前侧的(或顶)表面。通过在第一接触垫113上随后电镀焊料层114，将会把第一接触垫113的平坦的顶表面的形状转移至焊料层114的顶表面。在代表性实施例中，宽度W’可为约50μm且宽度B可为约20μm。W’可小于或等于约50μm。B可小于或等于约20μm。
图5代表性地示出根据图2A中针对第一半导体器件210以及第二半导体器件220所大体示出的代表性实施例在后续形成接点结构或总成的元件的相对尺寸。宽度A表示第二接触垫222的凹陷部分的横向宽度。宽度W表示第二接触垫222的横向宽度。在宽度W以及宽度A的数量级为约1E-06μm至1E-05μm的情形中，约为5:2的W:A的比率将产生第二接触垫222的实质上平坦且面对前侧的(或顶)表面。在代表性实施例中，宽度W可为约50μm且宽度A可为约20μm。W可小于或等于约50μm。A可小于或等于约20μm。
图6代表性地示出根据图3A中针对第一半导体器件310以及第二半导体器件320所大体示出的代表性实施例在后续形成接点结构或总成的元件的相对尺寸。宽度A表示第二接触垫322的凹陷部分的横向宽度。宽度W表示第二接触垫322的横向宽度。宽度B表示第一接触垫313的凹陷部分的横向宽度。宽度W’表示第一接触垫313的横向宽度。在宽度W、宽度W’、宽度A以及宽度B的数量级为约1E-06μm至1E-05μm的情形中，约为5:2的W:A的比率将产生第二接触垫322的实质上平坦且面对前侧的(或顶)表面，且约为5:2的W’:B的比率将产生第一接触垫313的实质上平坦且面对前侧的(或顶)表面。通过在第一接触垫313上随后电镀焊料层314，将会把第一接触垫313的平坦的顶表面的形状转移至焊料层314的顶表面。在代表性实施例中，宽度W可为约50μm，宽度A可为约20μm，宽度W’可为约50μm，且宽度B可为约20μm。宽度W可小于或等于约50μm。宽度A可小于或等于约20μm。宽度W’可小于或等于约50μm。宽度B可小于或等于约20μm。
图7代表性地示出根据代表性实施例的锥形接点结构795，其中第一接触垫113的横向范围宽度大于第二接触垫122的横向范围宽度。焊料层714具有宽度从第一接触垫113的顶表面向第二接触垫122的顶表面逐渐减小的锥形侧壁轮廓。也就是说，焊料层714沿着与集成无源器件封装衬底111的主表面(或封装体层121的主表面)实质上平行的维度测得的横向范围宽度在较接近第一接触垫113顶表面处得到的测量值与在较不接近第一接触垫113顶表面处得到的测量值相比往较不接近第一接触垫113顶表面处减小或降低，且所述减小/降低是在朝第二接触垫122的顶表面的方向上实质上连续的函数。
图8代表性地示出根据另一代表性实施例的锥形接点结构895，其中第一接触垫213的横向范围宽度大于第二接触垫222的横向范围宽度。焊料层814具有宽度从第一接触垫213的顶表面向第二接触垫222的顶表面逐渐减小的锥形侧壁轮廓。也就是说，焊料层814沿着与集成无源器件封装衬底211的主表面(或封装体层221的主表面)实质上平行的维度测得的横向范围宽度在较接近第二接触垫222顶表面处得到的测量值与在较不接近第二接触垫222顶表面处得到的测量值相比往较不接近第二接触垫222顶表面处变大或增大，且所述变大/增大是在朝第一接触垫213的顶表面的方向上实质上连续的函数。
图9代表性地示出根据又一代表性实施例的锥形接点结构995，其中第一接触垫313的横向范围宽度大于第二接触垫322的横向范围宽度。焊料层914具有宽度从第一接触垫313的顶表面向第二接触垫322的顶表面逐渐减小的锥形侧壁轮廓。也就是说，焊料层914沿着与集成无源器件封装衬底311的主表面(或封装体层321的主表面)实质上平行的尺寸测得的横向范围宽度在较接近第一接触垫313顶表面且较不接近第二接触垫322处得到的测量值与在较不接近第一接触垫313的顶表面且较接近第二接触垫322处得到的测量值相比往较不接近第一接触垫313的顶表面且较接近第二接触垫322处减小或降低，且所述减小/降低是在朝第二接触垫322的顶表面的方向上实质上连续的函数。
如图10中代表性地示出般，一种形成实质上无空隙的接点结构的方法1000可包括在第一半导体器件上形成焊料层的步骤1010，其中焊料层具有实质上平坦的顶表面。可例如通过电镀第一半导体器件的接触垫来形成焊料层，其中接触垫具有实质上平坦的表面形状。在随后的步骤1020中，在第二半导体器件上形成接触垫，其中接触垫具有实质上凹的顶表面。在进一步的步骤1030中，将第一半导体器件的焊料层在第二半导体器件的接触垫上对齐。在步骤1040中，使第一半导体器件的焊料层的顶表面落在第二半导体器件的接触垫的顶表面上。在步骤1050中，例如应用热能结合第一半导体器件的焊料层与第二半导体器件的接触垫。
如图11中代表性地示出般，一种形成实质上无空隙的接点结构的方法1100可包括在第一半导体器件上形成焊料层的步骤1110，其中焊料层具有实质上凹的顶表面。可例如通过电镀第一半导体器件的接触垫来形成焊料层。可例如通过将焊料电镀至第一半导体器件的接触垫上来实现焊料层的顶表面的凹的形状，其中接触垫具有实质上凹的表面形状。在随后的步骤1120中，在第二半导体器件上形成接触垫，其中接触垫具有实质上平坦的顶表面。在进一步的步骤1130中，将第一半导体器件的焊料层在第二半导体器件的接触垫上对齐。在步骤1140中，使第一半导体器件的焊料层的顶表面落在第二半导体器件的接触垫的顶表面上。在步骤1150中，例如应用热能结合第一半导体器件的焊料层与第二半导体器件的接触垫。
如图12中代表性地示出般，一种形成实质上无空隙的接点结构的方法1200可包括在第一半导体器件上形成焊料层的步骤1210，其中焊料层具有实质上平坦的顶表面。可例如通过电镀第一半导体器件的接触垫来形成焊料层，其中接触垫具有实质上平坦的表面形状。在随后的步骤1220中，在第二半导体器件上形成接触垫，其中所述接触垫具有实质上平坦的顶表面。在进一步的步骤1230中，将第一半导体器件的焊料层在第二半导体器件的接触垫上对齐。在步骤1240中，使第一半导体器件的焊料层的顶表面落在第二半导体器件的接触垫的顶表面上。在步骤1250中，例如应用热能结合第一半导体器件的焊料层与第二半导体器件的接触垫。
图13代表性地示出包括集成无源器件1312的叠层封装(PoP)结构1300。叠层封装结构1300包括第一器件封装件1315及第二器件封装件1355。第一器件封装件1315包括结合至第一器件封装件1315的集成无源器件1312。集成无源器件1312可根据本文中公开的各种代表性实施例结合至第一器件封装件1315。第二器件封装件1355包括衬底1320及一个或多个耦合至衬底1320的堆叠管芯(stacked dies)1350、1360。衬底1320可在一个实施例中基于例如玻璃纤维强化树脂芯等绝缘芯。代表性的芯材料包括例如FR4等玻璃纤维树脂。其他芯材料包括双马来酰亚胺三嗪(BT)树脂，或作为另外一种选择，包括其他印刷电路板(PCB)材料或膜。可使用例如味之素构成膜(ABF)或层压材料等构成膜来制作衬底1320。
衬底1320可包括有源器件以及无源器件(图中未示出)。在代表性实施例中，衬底1320可包括例如与第二器件封装件1355的下伏表面结合的集成无源器件，且经结合的集成无源器件夹置在第一器件封装件1315与第二器件封装件1355之间。如所属领域中的普通技术人员将知，可使用各种器件(例如，晶体管、电容器、电阻器、电感器及/或类似器件)来满足对叠层封装结构1300的设计的各种结构要求及/或功能要求。可利用任何适合的方法来形成这类器件。
衬底1320还可包括金属化层(图中未示出)及穿孔(through via)1330。金属化层可形成在有源器件以及无源器件上，并被设计成连接各种器件组件以形成功能性电路系统。金属化层可由绝缘(例如低k介电)材料与导电材料(例如铜)的多个交替的膜层所形成。通孔(via)将各个导电材料层内连(interconnect)。金属化层可利用任何适合的工艺(例如，沉积、镶嵌(damascene)、双镶嵌(dual damascene)等)来形成。在一些实施例中，衬底1320可实质上不含有源器件以及无源器件。
衬底1320可在衬底1320的第一侧上具有结合垫1335，以与堆叠管芯1350、1360耦合。在衬底1320的第二侧上具有结合垫1325，以与导电连接件1311耦合。衬底1320的第二侧与衬底1320的第一侧相对。尽管可使用其他连接形式(例如，导电凸块(conductivebump))，然而堆叠管芯1350、1360可通过打线接合1340耦合至衬底1320。在代表性实施例中，堆叠管芯1350、1360可包括例如堆叠存储器管芯。堆叠存储器管芯可包括低功率(low-power，LP)双倍数据速率(double data rate，DDR)存储器模块(例如，LPDDR1、LPDDR2、LPDDR3、或类似的存储器模块)或其组合。在一些实施例中，可通过模塑材料1390来封装堆叠管芯1350、1360及打线接合1340。
在形成第二器件封装件1355之后，可通过导电连接件1311、结合垫1325以及电性连接件1302将第二器件封装件1355与第一器件封装件1315结合。在一些实施例中，堆叠管芯1350、1360可通过打线接合1340、结合垫1335、1325、穿孔1330、导电连接件1311以及电性连接件1302耦合至集成电路管芯1303。集成电路管芯1303可包括半导体衬底，例如绝缘层体上硅(SOI)衬底的硅(经掺杂或未经掺杂)或绝缘层体上硅(SOI)衬底的有源层。半导体衬底可包含其他半导体材料(例如锗)、化合物半导体(例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟)、合金半导体(例如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP)及/或类似材料。也可使用例如多层衬底或梯度衬底等其他衬底。例如晶体管、二极管、电容器、电阻器、电感器等器件可形成在半导体衬底中及/或在半导体衬底上，且可通过所形成的内连线结构进行内连(例如通过半导体衬底的一个或多个绝缘层中的金属化图案进行内连，以形成集成电路)。
导电连接件1311可相似于导电连接件1301a、1301b。导电连接件1301a、1301b、1311可包括球栅阵列封装(ball grid array，BGA)连接件、焊球、金属柱、受控塌陷芯片连接(controlled collapse chip connection，C4)凸块、微凸块(micro bump)、化学镀镍钯浸金技术(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸块等。导电连接件1301a、1301b、1311可包含例如焊料、铜、铝、金、镍、银、钯、锡或其组合等导电材料。在一些实施例中，可通过利用各种方法(例如，蒸镀、电镀、印刷、焊料转移、植球(ball placement)等)先沉积焊料层来形成导电连接件1301a、1301b、1311。一旦已在所述结构上形成了焊料层，便可实行热处理(例如，回焊)来将所述材料成形为所需的凸块形状。在另一实施例中，导电连接件1301a、1301b、1311可包括通过溅镀、印刷、电镀、无电电镀、化学气相沉积等形成的金属柱(例如铜柱)。金属柱可实质上不含焊料。在一些实施例中，可在金属柱连接件上形成金属顶盖层(metal cap layer)。金属顶盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等、或其组合，且可通过镀覆工艺形成。根据代表性实施例，导电连接件1301a、1301b、1311可包括焊球，且焊球具有介于例如约150μm至约300μm范围的直径。导电连接件1311以及1301a、1301b不必为相同的。
如所属领域中的普通技术人员将知，可使用各种器件(例如，晶体管、电容器、电阻器、电感器、及/或类似器件)来满足叠层封装结构1300的设计的结构要求及/或功能要求，且可利用任何适合的方法来形成这类器件。在一些实施例中，可例如利用导电连接件1301a、1301b将叠层封装结构1300与封装衬底(图中未示出)结合。在实施例中，可将叠层封装结构1300与实质上不含有源器件以及无源器件的封装衬底(图中未示出)结合。叠层封装结构1300可包括集成扇出型(integrated fan out，InFO)器件封装结构，但也可使用其他任何适合的器件封装结构。
根据本发明的一些实施例，一种半导体器件的制造方法至少包括以下步骤。提供第一半导体器件以及第二半导体器件。第一半导体器件包括第一接触垫，第二半导体器件包括第二接触垫。在第一接触垫或第二接触垫上形成实质上凹的表面轮廓。在第一接触垫上电镀焊料层。将焊料层在第二接触垫上对齐。使焊料层落在第二接触垫上。结合焊料层与第二接触垫，其中焊料层或第二接触垫中的一者在进行结合之前具有实质上凹的形状。焊料层具有与第一接触垫的表面外形轮廓实质上相似的表面外形轮廓。第一半导体器件可包括集成无源器件(integrated passive device；IPD)。集成无源器件可包括电容器、电阻器、电感器、或二极管。第一半导体器件可包括阻抗匹配电路(impedance matchingcircuit)、谐波滤波器(harmonic filter)、带通滤波器(bandpass filter)、低通滤波器(low pass filter)、高通滤波器(high pass filter)、耦合器(coupler)、平衡-不平衡转换器(balun)、功率组合器(power combiner)、或功率分配器(power divider)。第二半导体器件可包括叠层封装(PoP)器件。第二接触垫或焊料层中的一者可在进行结合之前具有实质上平坦的顶表面。实质上凹的形状可包括约1μm至约7μm的凹腔深度。
根据本发明的另一些实施例，一种半导体器件的制造方法至少包括以下步骤。提供第一半导体器件以及第二半导体器件。第二半导体器件包括接触垫，且接触垫具有第一表面。在第一半导体器件的一部分上电镀焊料层，且焊料层具有第二表面。将第一表面在第二表面上对齐。使第一表面落在第二表面上。结合第一表面与第二表面，其中第一表面以及第二表面在进行结合之前实质上是平坦的。第一半导体器件可包括集成无源器件。集成无源器件可包括电容器、电阻器、电感器、或二极管。第一半导体器件可包括阻抗匹配电路、谐波滤波器、带通滤波器、低通滤波器、高通滤波器、耦合器、平衡-不平衡转换器、功率组合器、或功率分配器。第二半导体器件可包括叠层封装器件。
根据本发明的又一些实施例，一种器件封装件可包括第一半导体器件、第二半导体器件以及接点结构。第一半导体器件包括集成无源器件及设置在集成无源器件上的第一接触垫，其中第一接触垫的第一部分设置在第一半导体器件的外部部分的第一凹陷开口中。第一部分耦合至集成无源器件。第一接触垫具有包括第一横向范围的第一表面。第二半导体器件包括重布线层(RDL)以及设置在重布线层上的第二接触垫，其中第二接触垫的第二部分设置在第二半导体器件的外部部分的第二凹陷开口中。第二部分耦合至重布线层。第二接触垫具有包括第二横向范围的第二表面。跨越第二横向范围的第一距离小于跨越第一横向范围的第二距离。接点结构夹置于第一半导体器件与第二半导体器件之间。接点结构包括第一接触垫、第二接触垫以及焊料层。焊料层夹置于第一接触垫与第二接触垫之间。焊料层具有锥形的侧壁轮廓，锥形的侧壁轮廓以连续减小的宽度从第一表面往第二表面延伸。第一表面或第二表面中的至少一者实质上是平坦的。第一距离可小于或等于约50μm。第二距离可小于或等于约49μm。第一凹陷开口的第一宽度可小于或等于约20μm。第二凹陷开口的第二宽度可小于或等于约20μm。第一接触垫或第二接触垫中的至少一者可包含铜，且焊料层可包含锡。第二半导体器件可包括叠层封装(PoP)器件。集成无源器件可包括电容器、电阻器、电感器、或二极管。第一半导体器件可包括阻抗匹配电路、谐波滤波器、带通滤波器、低通滤波器、高通滤波器、耦合器、平衡-不平衡转换器、功率组合器、或功率分配器。焊料层可包括在第一表面与第二表面之间实质上连续分布的材料。焊料层具有第三横向范围，其中跨越第三横向范围的第三距离小于或等于第二距离。焊料层在剖视立面图中可包括沿着从第二表面垂直延伸到第一表面的主轴线具有实质上扁的半球体形状的部分。
以上概述了数个实施例的特征，使本领域普通技术人员可更佳了解本发明的实施方式。本领域普通技术人员应理解，其可轻易地使用本发明作为设计或修改其他工艺与结构的依据，以实行本文所介绍的实施例的相同目的和/或达到相同优点。本领域普通技术人员还应理解，这种等效的配置并不悖离本发明的精神与范畴，且本领域普通技术人员在不悖离本发明的精神与范畴的情况下可对本文做出各种改变、置换以及变更。

Claims (20)

1.一种半导体器件的制造方法，其特征在于，所述方法包括：
提供第一半导体器件以及第二半导体器件，所述第一半导体器件包括第一接触垫以及衬底，所述第一接触垫背对所述衬底的第一表面，所述第一接触垫具有接触所述衬底的金属特征的第二表面，所述第二半导体器件包括封装体、再分布层以及接触所述再分布层的第二接触垫，所述第二接触垫具有朝向所述第一表面的第三表面，所述第二接触垫具有接触所述再分布层的第四表面，所述封装体接触所述再分布层的侧壁、所述再分布层的顶表面以及所述第二接触垫的侧壁；
在所述第一表面或所述第三表面中的一者上形成实质上凹的表面轮廓，所述第一表面或所述第三表面中的另一者具有实质上平坦的表面轮廓，其中所述第一接触垫的所述第二表面或所述第二接触垫的所述第四表面包括所述第一表面或所述第三表面中的所述另一者具有第一宽度，其中所述第一表面或所述第三表面中的所述另一者具有第二宽度，且其中所述第二宽度与所述第一宽度的比率为5:2；
在所述第一接触垫的所述第一表面上电镀焊料层，所述焊料层具有背对所述第一表面的第五表面，所述第五表面与所述第一表面具有相同的外形轮廓；
将所述焊料层在所述第二接触垫上对齐；
使所述焊料层的所述第五表面落在所述第二接触垫的所述第三表面上；以及
结合所述焊料层与所述第二接触垫以形成接合结构，所述接合结构具有与所述第一表面接触的第六表面，所述第六表面具有等于所述第一表面的宽度的第三宽度，所述接合结构具有与所述第三表面接触的第七表面，所述第七表面具有等于所述第三表面宽度的第四宽度，所述接合结构具有从所述第三宽度到所述第四宽度逐渐内缩的侧壁。
2.根据权利要求1所述的制造方法，其特征在于，提供所述第一半导体器件包括提供集成无源器件。
3.根据权利要求2所述的制造方法，其特征在于，提供所述集成无源器件包括：提供阻抗匹配电路、谐波滤波器、带通滤波器、低通滤波器、高通滤波器、耦合器、平衡-不平衡转换器、功率组合器、或功率分配器。
4.根据权利要求2所述的制造方法，其特征在于，提供所述集成无源器件包括：提供电容器、电阻器、电感器、或二极管。
5.根据权利要求1所述的制造方法，其特征在于，提供所述第二半导体器件包括提供叠层封装器件。
6.根据权利要求1所述的制造方法，其特征在于，在结合所述焊料层与所述第二接触垫之前，进一步包括：
在所述第二接触垫或所述第一接触垫中的一者上形成具有实质上平坦的顶表面。
7.根据权利要求1所述的制造方法，其特征在于，形成凹的表面包括形成实质上凹的形状，所述实质上凹的形状具有1μm至7μm的凹腔深度。
8.一种半导体器件的制造方法，其特征在于，所述方法包括：
提供第一半导体器件以及第二半导体器件，所述第二半导体器件包括接触垫，所述接触垫具有第一实质上平坦的表面以及与所述第一实质上平坦的表面相对的第二表面，所述第二表面接触金属特征，所述第二表面具有第一宽度，所述第一实质上平坦的表面具有第二宽度，其中所述第二宽度与所述第一宽度的比率为5:2，其中所述第一实质上平坦的表面是所述接触垫的最外表面；
在所述第一半导体器件的第二接触垫上电镀焊料层，所述焊料层具有第二实质上平坦的表面，所述第二接触垫具有朝向所述焊料层的第一表面，所述第一表面具有第三宽度并且实质上平坦，所述第二接触垫具有相对于所述第一表面的第三表面，所述第三表面具有第四宽度，其中所述第三宽度与所述第二宽度的比率为5:2；
将所述第一实质上平坦的表面在所述第二实质上平坦的表面上对齐；
使所述第一实质上平坦的表面落在所述第二实质上平坦的表面上，其中所述第一实质上平坦的表面直接邻接所述第二实质上平坦的表面；以及
通过接合结构结合所述第一实质上平坦的表面与所述第二实质上平坦的表面，所述接合结构由位于所述第二接触垫和所述接触垫之间的所述焊料层形成，其中所述接合结构具有锥形侧壁，其从所述接合结构邻接所述第二接触垫的第四表面处的第五宽度连续减小至所述接合结构邻接所述接触垫的第五表面处的第六宽度，所述第五宽度等于所述第三宽度，所述第六宽度等于所述第二宽度。
9.根据权利要求8所述的制造方法，其特征在于，提供所述第一半导体器件包括提供集成无源器件。
10.根据权利要求9所述的制造方法，其特征在于，提供所述集成无源器件包括：提供阻抗匹配电路、谐波滤波器、带通滤波器、低通滤波器、高通滤波器、耦合器、平衡-不平衡转换器、功率组合器、或功率分配器。
11.根据权利要求9所述的制造方法，其特征在于，提供所述集成无源器件包括：提供电容器、电阻器、电感器、或二极管。
12.根据权利要求9所述的制造方法，其特征在于，提供所述第二半导体器件包括提供叠层封装器件。
13.一种器件结构，其特征在于，包括：
第一半导体器件，包括设置在封装衬底中的集成无源器件及设置在所述集成无源器件上的第一接触垫，所述第一接触垫的第一部分延伸穿过所述封装衬底，所述第一部分耦合至所述集成无源器件，所述第一接触垫具有包括第一横向范围的第一表面；
第二半导体器件，包括设置在封装体中的重布线层及设置在所述重布线层上的第二接触垫，所述第二接触垫的第二部分延伸穿过所述封装体，所述第二部分耦合至所述重布线层，所述第二接触垫具有包括第二横向范围的第二表面，其中跨越所述第二横向范围的第一距离小于跨越所述第一横向范围的第二距离；以及
接点结构，夹置于所述第一接触垫与所述第二接触垫之间，所述接点结构包括焊料层，所述焊料层具有锥形的侧壁轮廓，所述锥形的侧壁轮廓以连续减小的宽度从所述第一表面往所述第二表面延伸，其中所述第二表面是实质上平坦的，其中所述第一表面是凹形的并且是从相对的所述第一横向范围延伸的V形，其中所述接点结构的与所述第一表面接触的第三表面包括第三横向范围，其中跨越所述第三横向范围的第三距离是等于所述第二距离，其中所述接点结构的与所述第二表面接触的第四表面包括第四横向范围，并且其中跨越所述第四横向范围的第四距离等于所述第一距离。
14.根据权利要求13所述的器件结构，其特征在于，
所述第一距离小于或等于50μm；
所述第二距离小于或等于49μm；
所述第一部分的第一宽度小于或等于20μm；且
所述第二部分的第二宽度小于或等于20μm。
15.根据权利要求13所述的器件结构，其特征在于，所述第一接触垫或所述第二接触垫中的至少一者包含铜，且所述焊料层包含锡。
16.根据权利要求13所述的器件结构，其特征在于，所述第二半导体器件包括叠层封装器件。
17.根据权利要求16所述的器件结构，其特征在于，所述集成无源器件包括电容器、电阻器、电感器、或二极管。
18.根据权利要求17所述的器件结构，其特征在于，所述第一半导体器件包括阻抗匹配电路、谐波滤波器、带通滤波器、低通滤波器、高通滤波器、耦合器、平衡-不平衡转换器、功率组合器、或功率分配器。
19.根据权利要求13所述的器件结构，其特征在于，所述焊料层包括在所述第一表面与所述第二表面之间实质上连续分布的材料。
20.根据权利要求19所述的器件结构，其特征在于，
所述焊料层在剖视立面图中包括沿着从所述第二表面垂直地延伸到所述第一表面的主轴线具有实质上扁的半球体形状的部分。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9971970B1 (en) 2015-04-27 2018-05-15 Rigetti & Co, Inc. Microwave integrated quantum circuits with VIAS and methods for making the same
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture
US11521862B2 (en) * 2017-12-15 2022-12-06 Chih-Liang Hu Process for fabricating circuit components in matrix batches
JP7100980B2 (ja) * 2018-01-22 2022-07-14 ローム株式会社 Ｌｅｄパッケージ
KR102666153B1 (ko) 2018-06-15 2024-05-17 삼성전자주식회사 반도체 장치
CN108766489B (zh) * 2018-08-01 2023-08-08 灿芯半导体(上海)股份有限公司 一种用于倒装封装的ddr接口
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件
US10847408B2 (en) 2019-01-31 2020-11-24 Sandisk Technologies Llc Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip
WO2020159604A1 (en) * 2019-01-31 2020-08-06 Sandisk Technologies Llc Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip
US11114406B2 (en) 2019-01-31 2021-09-07 Sandisk Technologies Llc Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip
US11810882B2 (en) * 2022-03-01 2023-11-07 Micron Technology, Inc. Solder based hybrid bonding for fine pitch and thin BLT interconnection

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173846A (ja) * 1993-11-16 2007-07-05 Formfactor Inc 半導体パッケージアセンブリ
CN102254872A (zh) * 2010-05-20 2011-11-23 台湾积体电路制造股份有限公司 半导体结构以及半导体元件的形成方法
CN104752391A (zh) * 2010-03-04 2015-07-01 日月光半导体制造股份有限公司 具有单侧基板设计的半导体封装及其制造方法

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5470787A (en) * 1994-05-02 1995-11-28 Motorola, Inc. Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same
US6013571A (en) * 1997-06-16 2000-01-11 Motorola, Inc. Microelectronic assembly including columnar interconnections and method for forming same
US6578754B1 (en) * 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6506671B1 (en) * 2000-06-08 2003-01-14 Micron Technology, Inc. Ring positionable about a periphery of a contact pad, semiconductor device components including same, and methods for positioning the ring around a contact pad
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US20060223313A1 (en) * 2005-04-01 2006-10-05 Agency For Science, Technology And Research Copper interconnect post for connecting a semiconductor chip to a substrate and method of fabricating the same
TWI273667B (en) * 2005-08-30 2007-02-11 Via Tech Inc Chip package and bump connecting structure thereof
JP2009158593A (ja) * 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
US8017515B2 (en) * 2008-12-10 2011-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief
JP5335931B2 (ja) * 2008-12-26 2013-11-06 メギカ・コーポレイション 電力管理集積回路を有するチップ・パッケージおよび関連技術
US8659172B2 (en) * 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
TWI445147B (zh) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng 半導體元件
US8901736B2 (en) * 2010-05-28 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Strength of micro-bump joints
US9484279B2 (en) * 2010-06-02 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die
US8241963B2 (en) * 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
US8669651B2 (en) * 2010-07-26 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structures with reduced bump bridging
TWI478303B (zh) * 2010-09-27 2015-03-21 Advanced Semiconductor Eng 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構
US9105533B2 (en) * 2011-07-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure having a single side recess
US9425136B2 (en) * 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) * 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
TW201401456A (zh) * 2012-06-19 2014-01-01 矽品精密工業股份有限公司 基板結構與封裝結構
US9553053B2 (en) * 2012-07-25 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure for yield improvement
US10991669B2 (en) * 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
TWI562295B (en) * 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US8970035B2 (en) * 2012-08-31 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
US9111817B2 (en) * 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
US8957524B2 (en) * 2013-03-15 2015-02-17 Globalfoundries Inc. Pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
US9679868B2 (en) * 2013-06-19 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Ball height control in bonding process
JP2015170725A (ja) * 2014-03-07 2015-09-28 イビデン株式会社 複合基板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173846A (ja) * 1993-11-16 2007-07-05 Formfactor Inc 半導体パッケージアセンブリ
CN104752391A (zh) * 2010-03-04 2015-07-01 日月光半导体制造股份有限公司 具有单侧基板设计的半导体封装及其制造方法
CN102254872A (zh) * 2010-05-20 2011-11-23 台湾积体电路制造股份有限公司 半导体结构以及半导体元件的形成方法

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